System and method for testing chip immunity of SRAM (Static Random Access Memory)

Abstract

The invention provides a system and a method for testing the immunity of a chip of an SRAM (Static Random Access Memory). The system comprises an upper computer, a test board, an FPGA (Field Programmable Gate Array) monitoring unit and an electromagnetic interference tester, the upper computer is used for configuring test parameters of the FPGA monitoring unit and acquiring and displaying a read-write result fed back by the FPGA monitoring unit in real time; the test board is used for bearing a to-be-tested SRAM chip and at least comprises an interference injection network and a signal connection interface; and the FPGA monitoring unit is used for performing read-write test on the to-be-tested SRAM chip according to the test parameters and uploading a read-write result to the upper computer in real time. In the test process, the upper computer configures the FPGA monitoring unit through the test parameters to execute different test vectors, the FPGA monitoring unit communicates with the to-be-tested SRAM chip and feeds back read-write results to the upper computer in real time, the read-write results are visually displayed by the upper computer, and the flexible, controllable, visual and visible immunity test process is achieved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit testing, and in particular to a chip anti-interference testing system and method for SRAM. Background Art

[0002] Static Random-Access Memory (SRAM) is a type of random access memory. The so-called "static" means that as long as the memory remains powered on, the data stored in it can be kept constant. Because of its advantages such as fast reading and writing, large storage capacity, and low power consumption, it is often used in embedded systems, such as microcontrollers and digital signal processors in the fields of industrial control, automotive electronics, and communication equipment. Or it is used in real-time signal processing fields, such as image processing and audio processing. However, in actual use, integrated circuits usually need to work in an environment with interference, so it is necessary to ensure that the SRAM chip has high anti-interference characteristics, especially the electromagnetic shielding (EMC) of the chip.

[0003] The electromagnetic compatibility immunity test method for integrated circuits has developed into a standard test method, formulated and published by IEC, using different types of interference sources and different injection methods to complete the immunity test. However, in the actual test process, for SRAM chips, there are many types and large numbers of signal lines. Simply using a conventional oscilloscope as a failure monitor cannot display the waveforms of all signals; in addition, the oscilloscope cannot generate signals as a signal source, that is, it cannot generate read and write test vectors input to the SRAM. Summary of the invention

[0004] The purpose of the embodiments of the present disclosure is to provide a chip immunity testing system and method for SRAM to solve the above-mentioned problems existing in the prior art.

[0005] The embodiment of the present disclosure adopts the following technical scheme: a chip immunity test system of SRAM, comprising: a host computer, a test board, an FPGA monitoring unit and an electromagnetic interference tester; wherein the host computer is communicatively connected with the FPGA monitoring unit, and is used to configure the test parameters of the FPGA monitoring unit, and obtain the read and write results fed back by the FPGA monitoring unit in real time for display; the test board is used to carry the SRAM chip to be tested, and at least includes an interference injection network and a signal connection interface; the FPGA monitoring unit is communicatively connected with the SRAM chip to be tested through the signal connection interface, and is used to perform read and write tests on the SRAM chip to be tested according to the test parameters, and upload the read and write results to the host computer in real time; the electromagnetic interference tester is connected with the test board, and is used to generate an interference source, and inject the interference source into the SRAM chip to be tested through the interference injection network.

[0006] In some embodiments, the FPGA test board is specifically used to: determine the read-write mode and preset content according to the test parameters; write the preset content into the SRAM chip to be tested according to the read-write mode, and read the current storage content in the SRAM chip to be tested in real time; and upload the read-write results formed by the write data, read data, write time, read time and current test address to the host computer.

[0007] In some embodiments, the read / write mode includes at least any one of the following: Checkerboard mode, March mode, fixed address mode, and fixed data mode.

[0008] In some embodiments, the FPGA monitoring unit is further used to configure its own clock division and test timing according to the test parameters.

[0009] In some embodiments, the host computer is also used to: determine whether the write data is consistent with the read data based on the read and write results; when the write data is inconsistent with the read data, send a stop test instruction to the FPGA monitoring unit to make the FPGA monitoring unit stop performing read and write tests on the SRAM chip to be tested.

[0010] In some embodiments, the signal connection interface includes at least: a control signal line interface, an address signal line interface, and a data signal line interface.

[0011] In some embodiments, the electromagnetic interference tester includes at least: an RF signal source, an RF amplifier, a directional coupler, a forward power meter, and a reverse power meter.

[0012] The disclosed embodiment also provides a chip immunity test method for SRAM, which at least includes: building a chip immunity test system as described above; sending test parameters from a host computer to an FPGA monitoring unit to configure the FPGA monitoring unit to perform a read and write test on the SRAM chip to be tested according to the test parameters, and uploading the read and write results in real time; in the case where no interference is applied, the host computer determines whether a read and write failure occurs in the SRAM chip to be tested according to the read and write results of the SRAM chip to be tested; in the case where no read and write failure occurs, turning on an electromagnetic interference tester to inject interference into the SRAM chip to be tested, and the host computer monitors the read and write results uploaded by the FPGA monitoring unit in real time and displays them.

[0013] In some embodiments, it also includes: when interference is applied, the host computer determines whether the write data is consistent with the read data based on the read and write results; when the write data is inconsistent with the read data, a stop test instruction is sent to the FPGA monitoring unit to make the FPGA monitoring unit stop the read and write test on the SRAM chip to be tested.

[0014] The beneficial effects of the disclosed embodiments are as follows: during the test process, the host computer configures the FPGA monitoring unit through test parameters to execute different test vectors, and the FPGA monitoring unit communicates with the SRAM chip to be tested, and feeds back the reading and writing results to the host computer in real time, which is displayed intuitively by the host computer, thereby realizing a flexible, controllable, intuitive and visual anti-interference test process, and at the same time, the test system structure is simple and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0016] Figure 1 It is a structural schematic diagram of the chip immunity test system of SRAM in the first embodiment of the present disclosure;

[0017] Figure 2 This is a schematic diagram of the structure of the FPGA monitoring unit in the first embodiment of the present disclosure;

[0018] Figure 3 It is a schematic diagram of the architecture of the SRAM chip immunity test system in the first embodiment of the present disclosure;

[0019] Figure 4It is a flow chart of the chip immunity testing method of SRAM in the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will be combined with the drawings in one or more embodiments of this specification to clearly and completely describe the technical solutions in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this document.

[0021] SRAM is a type of random access memory. The so-called "static" means that as long as the memory remains powered on, the data stored in it can be kept constant. Because of its advantages such as fast reading and writing, large storage capacity, and low power consumption, it is often used in embedded systems, such as microcontrollers and digital signal processors in the fields of industrial control, automotive electronics, and communication equipment. Or it is used in real-time signal processing fields, such as image processing and audio processing. However, in actual use, integrated circuits usually need to work in an environment with interference, so it is necessary to ensure that the SRAM chip has high anti-interference characteristics, especially the electromagnetic shielding of the chip.

[0022] The electromagnetic compatibility immunity test method for integrated circuits has developed into a standard test method, formulated and published by IEC, using different types of interference sources and different injection methods to complete the immunity test. However, in the actual test process, for SRAM chips, there are many types and large numbers of signal lines. Simply using a conventional oscilloscope as a failure monitor cannot display the waveforms of all signals; in addition, the oscilloscope cannot generate signals as a signal source, that is, it cannot generate read and write test vectors input to the SRAM.

[0023] In order to solve the above problems, the first embodiment of the present disclosure provides a chip immunity test system of SRAM, and its structural diagram is as follows: Figure 1As shown, it mainly includes: a host computer 10, a test board 20, an FPGA monitoring unit 30 and an electromagnetic interference tester 40; wherein the host computer 10 is connected in communication with the FPGA monitoring unit 30 to configure the test parameters of the FPGA monitoring unit 30, and obtains the read and write results fed back by the FPGA monitoring unit 30 in real time for display; the test board 20 is used to carry the SRAM chip to be tested (i.e., the device under test DUT), which at least includes an interference injection network and a signal connection interface; the FPGA monitoring unit 30 is connected in communication with the SRAM chip to be tested through the signal connection interface, and is used to perform read and write tests on the SRAM chip to be tested according to the test parameters, and upload the read and write results to the host computer 10 in real time; the electromagnetic interference tester 40 is connected to the test board 20, and is used to generate an interference source, and inject the interference source into the SRAM chip to be tested through the interference injection network.

[0024] Specifically, the host computer 10 can be implemented using any conventional device with computing and processing functions. The tester can adjust the test parameters by operating the host computer 10 to adjust the test method and test content related to the anti-disturbance test; after receiving the test parameters sent by the host computer 10, the FPGA monitoring unit 30 performs its own functional configuration based on the content of the test parameters to determine the read and write mode and preset content of this test. The preset content here mainly refers to the pre-set data content that needs to be written to the SRAM chip to be tested, or it can be called the write content. During the test process, it is necessary to combine the pre-determined write content with the actual read content to determine whether the SRAM chip to be tested is valid.

[0025] Further, the read-write mode mainly refers to the sequential mode when the FPGA monitoring unit 30 writes and reads data to the SRAM chip to be tested, and in this embodiment, at least any one of the following is included: Checkerboard mode, March mode, fixed address mode, and fixed data mode. Among them, in the Checkerboard mode (also known as the chessboard mode or chb mode), adjacent storage cells are alternately written with different values ​​(usually 0 and 1), and this mode helps to detect errors caused by capacitive coupling and interference between storage cells; in the March mode, the FPGA monitoring unit 30 accesses the storage address of the SRAM chip to be tested in a specific order and reads it out in the same order. It also has multiple variants such as March C, March C-, March B, etc., and this embodiment can be implemented by configuring the FPGA; the fixed address mode limits the specific storage address in the SRAM chip to be tested for testing; the fixed data mode performs write and read operations on the SRAM chip to be tested for a certain specific data.

[0026] In some embodiments, the FPGA monitoring unit 30 includes at least a communication interface driver module, a clock management module, a test parameter configuration module, a test algorithm storage module, and a RAM interface module. Figure 2 As shown; wherein, the communication interface driver module is used to communicate with the host computer, receive the test parameters sent by the host computer and send them to the clock management module and the test parameter configuration module; the clock management module will configure and generate the clock reference required by the entire FPGA monitoring unit and the reference clock for DUT communication; the test parameter configuration module is used for parameter configuration and test algorithm selection of read and write operations, and realizes the configuration of clock division, test timing, test switch control and read and write mode selection. Tables 1 to 6 give an example of specific configuration parameters of an FPGA monitoring unit. Other different parameter configurations can also be performed during actual testing, which is not limited in this embodiment; the test algorithm storage module is used to store different read and write modes, and the corresponding read and write modes are called according to the configuration of the test parameter configuration module; the RAM interface module is used to perform read and write operations with the SRAM chip to be tested, and generate different timing waveforms according to the timing parameters.

[0027] Table 1 Test clock frequency division register

[0028]

[0029] Table 2 Test Timing Register

[0030]

[0031] Table 3 Test general registers

[0032]

[0033]

[0034] Table 4 Test fixed address register

[0035]

[0036] Table 5 Test Data Mask Register

[0037]

[0038] Table 6 Test error statistics register

[0039]

[0040] After the FPGA monitoring unit is configured, it will write preset content to the SRAM chip under test according to the selected read-write mode, and read the current storage content in the SRAM chip under test in real time. Subsequently, the FPGA monitoring unit will upload the read-write results of the write data, read data, write time, read time and current test address to the host computer, so that the host computer can evaluate whether the SRAM chip under test is affected by interference and causes failure according to the read-write situation.

[0041] In the actual test process, first, without applying external interference, it is detected whether the SRAM chip to be tested is in a valid state. If it is determined to be valid, interference is injected into the SRAM chip to be tested through an electromagnetic interference tester. When external interference is applied, the FPGA monitoring unit is continuously driven to communicate with the SRAM chip to read and write, and the read and write results are uploaded.

[0042] In the absence of external interference, the SRAM chip under test should be in a valid state, that is, the read data should be consistent with the written data. If the read and written data are inconsistent at this time, it means that the SRAM chip under test itself is in a failed state, and the test should be stopped and repaired in time. In the case of external interference, the data that can be read by the FPGA monitoring unit may be different from the written data. This difference may be caused by the interference of the SRAM chip under test during the data writing process, or the written data may be correct but the data is changed due to interference during the storage process, or the data may be changed during the reading process.

[0043] After receiving the read and write results uploaded by the FPGA monitoring unit, the host computer analyzes and processes the content to determine whether the write data and read data recorded in the read and write results are consistent. If the write data and the read data are consistent, it is determined that the SRAM chip under test has effectively resisted the influence of interference during the interference injection process up to the current moment. If the write data and the read data are inconsistent, it means that the SRAM chip under test can no longer resist the electromagnetic interference applied from the outside. To avoid causing more serious chip damage, the host computer can send a stop test instruction to the FPGA monitoring unit to stop the FPGA monitoring unit from performing read and write tests on the SRAM chip under test.

[0044] In this embodiment, when the host computer determines that the write data and read data in the current read-write result are inconsistent, the write time, read time and current test address corresponding to the current read-write result should also be displayed to facilitate the tester to intuitively understand the problem. In the actual test process, the tester can combine the error address and other information displayed by the host computer with the chip reset and other operations to determine the failure type of the chip, as shown in Table 7.

[0045] Table 7 Definition of failure types for immunity test

[0046]

[0047] Figure 3 FIG. 1 shows a schematic diagram of the architecture of an SRAM chip immunity test system. Figure 3 As shown, the SRAM chip to be tested is placed on the test board and communicated with the FPGA monitoring unit through the signal connection interface of the test board, and the FPGA monitoring unit is communicated with the host computer; the electromagnetic interference tester includes at least an RF (Radio Frequency) signal source, an RF amplifier, a directional coupler, a forward power meter, and a reverse power meter. The above equipment can be connected according to conventional testing and connection requirements, and the RF interference can be injected into the SRAM chip to be tested through the RF injection point in the interference injection network. In some embodiments, the host computer can also communicate with any one or more of the RF signal source, forward power meter, and reverse power meter in the electromagnetic interference tester, such as Figure 3 As shown in the dotted line connection in the figure, unified drive control of the electromagnetic interference tester is realized. The upper computer can detect that the SRAM chip to be tested is in a valid state without applying external interference, and then autonomously drive the electromagnetic interference tester to inject a radio frequency interference signal of a specific frequency, and adjust the injection of the radio frequency interference signal in combination with the test results and test procedures.

[0048] It should be noted that the test board needs to meet the design requirements of the standard. It needs to be configured with the minimum hardware system that meets the work of the DUT. It also needs to configure the coupling path of the interference injection network and the signal connection interface with the FPGA monitoring unit. The signal connection interface in this embodiment includes at least a control signal line interface, an address signal line interface, and a data signal line interface, which are respectively used to determine the type of read and write operation on the SRAM chip to be tested, the read and write position for performing this read / write operation, and the data content read / written by this read / write operation; the FPGA monitoring unit can be implemented using a mature FPGA board on the market that meets the test requirements. By configuring its internal functional logic through test parameters, it can be used as the main body for generating test vectors in the anti-disturbance test, communicate with the SRAM chip to be tested, and use its own read and write operations on the SRAM chip to be tested to complete the read and write result feedback of the SRAM chip to be tested under interference conditions; Figure 3The electromagnetic interference tester shown is only the instrument configuration used for the direct RF power injection method in the conducted immunity test method. If other test methods are used in the actual test process, such as the BCI (bulk current injection) method or the TEM (transverse electromagnetic wave and broadband transverse electromagnetic wave chamber, TEM and wideband TEM cell) chamber method, the structure of the corresponding electromagnetic interference tester can be replaced. If the reading and writing methods of the DUT need to be adjusted, the configuration of the FPGA monitoring unit can be adjusted accordingly.

[0049] In the test process of this embodiment, the host computer configures the FPGA monitoring unit through test parameters to execute different test vectors, and the FPGA monitoring unit communicates with the SRAM chip to be tested, and feeds back the read and write results to the host computer in real time, which is displayed intuitively by the host computer, realizing a flexible, controllable, intuitive and visual anti-interference test process, while the test system structure is simple and easy to implement. In addition, due to the design flexibility of the FPGA structure itself, it can cover more and more comprehensive test algorithms, and the independent design optimization technology of FPGA is more mature, and the overall manufacturing cost is lower than the cost of chip design tape-out.

[0050] The second embodiment of the present disclosure provides a method for testing the chip immunity of an SRAM, that is, using the chip immunity testing system provided by the first embodiment of the present disclosure to test the immunity of an SRAM chip, and the flow chart thereof is as follows: Figure 4 As shown, it mainly includes:

[0051] S10, building a chip immunity test system as in the first embodiment of the present disclosure;

[0052] S20, the host computer sends test parameters to the FPGA monitoring unit to configure the FPGA monitoring unit to perform a read and write test on the SRAM chip to be tested according to the test parameters, and upload the read and write results in real time;

[0053] S30, when no interference is applied, the host computer determines whether a read / write failure occurs in the SRAM chip to be tested according to the read / write result of the SRAM chip to be tested;

[0054] S40, when no read or write failure occurs, the electromagnetic interference tester is turned on to inject interference into the SRAM chip to be tested, and the host computer monitors the read and write results uploaded by the FPGA monitoring unit in real time and displays them.

[0055] It should be noted that, corresponding to step S30, the host computer detects and determines in real time whether the write data and the read data in the read and write results fed back by the FPGA monitoring unit are consistent, and when the two are consistent, it is determined that the SRAM chip under test has not experienced a read or write failure. If the write data and the read data are inconsistent at this time, it is determined that a read or write error has occurred in the SRAM chip under test, and the test should be stopped in time and it should be determined that the SRAM chip under test itself has a functional problem.

[0056] Corresponding to step S40, when it has been determined that the SRAM chip to be tested is functioning normally, an RF interference signal is injected, and the read and write results are monitored in real time. Once a read and write error occurs, the host computer will display and record the failed address and related data content, and at the same time send a stop test instruction to the FPGA monitoring unit, so that the FPGA monitoring unit stops the read and write test on the SRAM chip to be tested to prevent further damage to the chip.

[0057] Other execution details of this embodiment have been described in detail in the first embodiment of the present disclosure and will not be repeated here.

[0058] During the test process of this embodiment, the host computer configures the FPGA monitoring unit through test parameters to execute different test vectors, and the FPGA monitoring unit communicates with the SRAM chip to be tested, and feeds back the reading and writing results to the host computer in real time, which is displayed intuitively by the host computer, thereby realizing a flexible, controllable, intuitive and visual anti-interference test process. At the same time, the test method can cover a variety of different test methods, with higher flexibility.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A chip immunity test system for SRAM, characterized in that: include: Host computer, test board, FPGA monitoring unit and electromagnetic interference tester; among them, The host computer is connected to the FPGA monitoring unit for communication, and is used to configure the test parameters of the FPGA monitoring unit, and obtain the read and write results fed back by the FPGA monitoring unit in real time for display; The test board is used to carry the SRAM chip to be tested, and at least includes an interference injection network and a signal connection interface; The FPGA monitoring unit is connected to the SRAM chip to be tested through the signal connection interface, and is used to perform a read and write test on the SRAM chip to be tested according to the test parameters, and upload the read and write results to the host computer in real time; The electromagnetic interference tester is connected to the test board and is used to generate an interference source, and inject the interference source into the SRAM chip to be tested through the interference injection network.

2. The chip immunity test system according to claim 1, characterized in that: The FPGA test board is specifically used for: Determine the read / write mode and preset content according to the test parameters; Writing the preset content into the SRAM chip to be tested according to the read-write mode, and reading the current storage content in the SRAM chip to be tested in real time; The write data, read data, write time, read time and current test address form the read-write result and upload it to the host computer.

3. The chip immunity test system according to claim 2, characterized in that: The read / write mode includes at least one of the following: Checkerboard mode, March mode, fixed address mode, fixed data mode.

4. The chip immunity test system according to claim 2, characterized in that: The FPGA monitoring unit is also used to configure its own clock frequency division and test timing according to the test parameters.

5. The chip immunity test system according to claim 1, characterized in that: The host computer is also used for: Determining whether the written data is consistent with the read data according to the read-write result; When the written data is inconsistent with the read data, a stop test instruction is sent to the FPGA monitoring unit, so that the FPGA monitoring unit stops performing read and write tests on the SRAM chip to be tested.

6. The chip immunity test system according to claim 1, characterized in that: The signal connection interface at least includes: a control signal line interface, an address signal line interface, and a data signal line interface.

7. The chip immunity test system according to any one of claims 1 to 6, characterized in that: The electromagnetic interference tester at least comprises: an RF signal source, an RF amplifier, a directional coupler, a forward power meter and a reverse power meter.

8. A method for testing the chip immunity of SRAM, characterized in that: At least: Building a chip immunity test system as described in any one of claims 1 to 7; The host computer sends test parameters to the FPGA monitoring unit to configure the FPGA monitoring unit to perform a read and write test on the SRAM chip to be tested according to the test parameters, and upload the read and write results in real time; In the case where no interference is applied, the host computer determines whether a read-write failure occurs in the SRAM chip to be tested according to the read-write result of the SRAM chip to be tested; In the case where no read or write failure occurs, the electromagnetic interference tester is turned on to inject interference into the SRAM chip to be tested, and the host computer monitors the read and write results uploaded by the FPGA monitoring unit in real time and displays them.

9. The chip immunity testing method according to claim 8, characterized in that: Also includes: In the case of interference, the host computer determines whether the written data is consistent with the read data according to the read and write results; When the written data is inconsistent with the read data, a stop test instruction is sent to the FPGA monitoring unit, so that the FPGA monitoring unit stops performing read and write tests on the SRAM chip to be tested.

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