Photoelectric system packaging structure and preparation method thereof

Abstract

According to the photoelectric system packaging structure and the preparation method thereof provided by the invention, the complete photoelectric system packaging structure can be formed through the arrangement of the 3D stacked logic storage module, the storage module, the optical module, the rewiring layer, the metal columns, the ASIC chip and the TSV composite adapter plate, the transmission distance of each module can be shorter, the signal transmission is faster, and the reliability of the photoelectric system packaging structure is improved. Transmission power consumption is effectively reduced, and the packaging area is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing, and relates to a photoelectric system packaging structure and a preparation method thereof. Background Art

[0002] As global Internet traffic grows, the demand for data center interconnection bandwidth will continue to grow at an exponential rate. In order to meet Internet traffic demand, data center node bandwidth needs to reach 10Tb / s. In order to slow down the trend of increasing energy consumption in data centers, we must find ways to reduce the power consumption of systems and devices. Lower cost, more reliable, faster and higher density circuits are the goals pursued by integrated circuit packaging.

[0003] Among them, the number of input / output (I / O) pins of the package structure doubles at a rate of about every 6 years, while the total I / O bandwidth doubles at a rate of about every 3 to 4 years, so there is a rate difference. Since light has the performance of low signal attenuation, low energy consumption, high bandwidth and compatibility with CMOS, the industry generally believes that the organic combination of silicon photonics can not only reduce chip size, reduce cost and power consumption, but also improve reliability. Therefore, it is necessary to introduce silicon photonics technology. Among them, how to package optical integrated circuits (PICs) and electrical integrated circuits (EICs) is crucial. Improper integration of light and electricity will offset the potential advantages of silicon photonics.

[0004] Most of the existing optoelectronic integrated semiconductor packaging structures directly bond the optical integrated chip and the electrical integrated chip to the substrate, and electrically connect them to the substrate through wire bonding and flip-chip bonding. However, this packaging method has defects such as long transmission distance, high transmission power consumption, and large packaging area, making it difficult to meet the needs of high-density and high-performance integrated packaging.

[0005] Therefore, it is necessary to provide an optoelectronic system packaging structure and a preparation method thereof. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an optoelectronic system packaging structure and a preparation method thereof, so as to solve the problem that the optoelectronic interconnect packaging in the prior art is difficult to meet the requirements of high-density, high-performance integrated packaging.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing an optoelectronic system packaging structure, comprising the following steps:

[0008] providing a supporting substrate;

[0009] forming a metal column on the supporting substrate;

[0010] Providing an ASIC chip and a TSV composite adapter board, bonding the ASIC chip and the TSV composite adapter board to the support substrate, wherein the surface of the ASIC chip has a first connector electrically connected to the ASIC chip, and the surface of the TSV composite adapter board has a second connector electrically connected to the TSV composite adapter board;

[0011] Forming a packaging layer on the supporting substrate, wherein the packaging layer covers the ASIC chip, the TSV composite adapter plate and the metal column, and exposes the metal column, the first connector and the second connector;

[0012] forming a first rewiring layer on the packaging layer, wherein the first rewiring layer is electrically connected to the metal pillar, the first connector, and the second connector;

[0013] Providing a 3D stacked logic storage module, a storage module and an optical module, and bonding the 3D stacked logic storage module, the storage module and the optical module to the first rewiring layer, wherein the 3D stacked logic storage module, the storage module and the optical module are all electrically connected to the first rewiring layer, and the 3D stacked logic storage module, the ASIC chip and the optical module are electrically connected, and the 3D stacked logic storage module, the TSV composite adapter board and the storage module are electrically connected;

[0014] removing the supporting substrate to expose the encapsulation layer;

[0015] forming a second redistribution layer on the surface of the packaging layer, wherein the second redistribution layer is electrically connected to the metal pillar;

[0016] A metal bump is formed on the second redistribution layer, and the metal bump is electrically connected to the second redistribution layer.

[0017] Optionally, the method further includes providing a substrate and bonding the substrate to the metal bump, and the substrate is electrically connected to the metal bump.

[0018] Optionally, the method further includes providing a heat sink and bonding the heat sink to the substrate.

[0019] Optionally, the 3D stacked logic memory module comprises stacked interconnected memory chips and back-side power supply logic chips, wherein the steps of preparing the 3D stacked logic memory module include:

[0020] providing a first semiconductor substrate;

[0021] forming a first transistor layer on the front surface of the first semiconductor substrate;

[0022] forming a first signal wiring layer on the first transistor layer, wherein the first signal wiring layer is electrically connected to the first transistor layer;

[0023] forming a third rewiring layer on the first signal wiring layer, wherein the third rewiring layer is electrically connected to the first signal wiring layer;

[0024] A memory chip is provided, the memory chip comprising a stacked second semiconductor substrate, a second transistor layer and a composite wiring layer, the composite wiring layer comprising a second signal wiring layer and a second power wiring layer, and the second signal wiring layer and the second power wiring layer are both electrically connected to the second transistor layer;

[0025] forming a fourth rewiring layer on the composite wiring layer, wherein the fourth rewiring layer is electrically connected to the second signal wiring layer and the second power wiring layer;

[0026] Bonding the third rewiring layer to the fourth rewiring layer, and the third rewiring layer is electrically connected to the fourth rewiring layer;

[0027] thinning the first semiconductor substrate from the back side of the first semiconductor substrate;

[0028] forming a passivation layer on the back side of the first semiconductor substrate;

[0029] forming a metal connection column penetrating the passivation layer, the first semiconductor substrate and the first transistor layer, wherein a first end of the metal connection column is electrically connected to both the first signal wiring layer and the first transistor layer;

[0030] forming a first power wiring layer on the surface of the passivation layer, wherein the first power wiring layer is electrically connected to the second end of the metal connection column;

[0031] A metal connection bump is formed on the surface of the first power wiring layer, and the metal connection bump is electrically connected to the first power wiring layer.

[0032] Optionally, the line width of the TSV composite adapter plate is 0.4 μm to 1 μm, and the line spacing is 0.4 μm to 1 μm.

[0033] Optionally, the method further includes forming a bottom filling layer between the first rewiring layer and the 3D stacked logic memory module, the memory module and the optical module.

[0034] The present invention also provides a photoelectric system packaging structure, the photoelectric system packaging structure comprising:

[0035] a first re-distribution layer, the first re-distribution layer comprising a first side and an opposite second side;

[0036] 3D stacked logic storage module, storage module and optical module, wherein the 3D stacked logic storage module, the storage module and the optical module are bonded to the first surface of the first rewiring layer, and the 3D stacked logic storage module, the storage module and the optical module are all electrically connected to the first rewiring layer;

[0037] a second redistribution layer, the second redistribution layer comprising a first side and an opposite second side;

[0038] A metal column, wherein the metal column is located between the second surface of the first re-distribution layer and the first surface of the second re-distribution layer, and a first end of the metal column is electrically connected to the first re-distribution layer, and a second end of the metal column is electrically connected to the second re-distribution layer;

[0039] An ASIC chip and a TSV composite adapter board, wherein the ASIC chip and the TSV composite adapter board are located between the second surface of the first rewiring layer and the first surface of the second rewiring layer, the surface of the ASIC chip has a first connector electrically connected to the ASIC chip, the surface of the TSV composite adapter board has a second connector electrically connected to the TSV composite adapter board, the first connector and the second connector are both electrically connected to the first rewiring layer, and the 3D stacked logic storage module, the ASIC chip and the optical module are electrically connected, and the 3D stacked logic storage module, the TSV composite adapter board and the storage module are electrically connected;

[0040] A packaging layer, the packaging layer is located between the second surface of the first rewiring layer and the first surface of the second rewiring layer, and covers the ASIC chip, the TSV composite adapter plate and the metal pillar;

[0041] A metal bump is located on the second surface of the second re-distribution layer and is electrically connected to the second re-distribution layer.

[0042] Optionally, the line width of the TSV composite adapter plate is 0.4 μm to 1 μm, and the line spacing is 0.4 μm to 1 μm.

[0043] Optionally, the method further includes a substrate electrically connected to the metal bump, and a heat sink bonded to the substrate.

[0044] Optionally, the 3D stacked logic storage module includes stacked interconnected storage chips and back-side power supply logic chips.

[0045] As described above, the optoelectronic system packaging structure and preparation method of the present invention can form a complete optoelectronic system packaging structure by 3D stacking logic storage modules, storage modules, optical modules, rewiring layers, metal pillars, ASIC chips and TSV composite adapter boards, and can make the transmission distance of each module shorter, the signal transmission faster, effectively reduce the transmission power consumption, and reduce the packaging area. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a schematic diagram of the process flow of preparing the optoelectronic system packaging structure in an embodiment of the present invention.

[0047] Figure 2 Shown is a schematic structural diagram of a support substrate provided in an embodiment of the present invention.

[0048] Figure 3 It is a schematic diagram of the structure after the ASIC chip, TSV composite adapter plate and metal pillars are formed in an embodiment of the present invention.

[0049] Figure 4 It is a schematic diagram of the structure after the encapsulation layer is formed in an embodiment of the present invention.

[0050] Figure 5 It is a schematic diagram of the structure after the encapsulation layer is thinned in an embodiment of the present invention.

[0051] Figure 6 It is a schematic diagram of the structure after the first rewiring layer is formed in an embodiment of the present invention.

[0052] Figure 7 It is a schematic diagram of the structure after bonding the 3D stacked logic storage module, storage module and optical module in an embodiment of the present invention.

[0053] Figure 8 It is a schematic diagram of the structure after forming the metal bump in the embodiment of the present invention.

[0054] Fig. 9 It is a schematic diagram of the structure after the heat sink is formed in an embodiment of the present invention.

[0055] Fig.10 It is a schematic diagram of the structure after bonding the third rewiring layer and the fourth rewiring layer when preparing a 3D stacked logic memory module in an embodiment of the present invention.

[0056] Fig.11 It is a schematic diagram of the structure after metal connecting pillars are formed when preparing a 3D stacked logic storage module in an embodiment of the present invention.

[0057] Fig.12 Shown is a schematic structural diagram of a 3D stacked logic storage module prepared in an embodiment of the present invention.

[0058] Description of Reference Numerals

[0059] 100 Support substrate

[0060] 200 Separation Layer

[0061] 300 Dielectric layer

[0062] 400 Metal Column

[0063] 500 ASIC chips

[0064] 501 First connecting piece

[0065] 600 TSV composite adapter plate

[0066] 601 Second connecting piece

[0067] 700 Encapsulation Layer

[0068] 810 First rewiring layer

[0069] 820 Second rewiring layer

[0070] 910 3D stacked logic memory module

[0071] 911 backside power supply logic chip

[0072] 9111 First semiconductor substrate

[0073] 9112 First transistor layer

[0074] 9113 First signal wiring layer

[0075] 9114 Passivation layer

[0076] 9115 First power wiring layer

[0077] 912 Memory Chip

[0078] 9121 Second semiconductor substrate

[0079] 9122 Second transistor layer

[0080] 9123 Composite wiring layer

[0081] 913 Third rewiring layer

[0082] 914 Fourth rewiring layer

[0083] 915 Metal Connecting Column

[0084] 916 Metal connection bumps

[0085] 920 Storage Module

[0086] 930 Optical Module

[0087] 110 Bottom filling layer

[0088] 120 metal bumps

[0089] 130 substrate

[0090] 140 Heat sink DETAILED DESCRIPTION

[0091] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0092] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0093] For ease of description, spatial relational terms such as “under”, “below”, “below”, “below”, “over”, etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.

[0094] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0095] like Figure 1The present embodiment provides a method for preparing an optoelectronic system packaging structure. By 3D stacking logic storage modules, storage modules, optical modules, rewiring layers, metal pillars, ASIC chips and TSV composite adapter boards, a complete optoelectronic system packaging structure can be formed. The transmission distance of each module can be shortened, the signal transmission can be faster, the transmission power consumption can be effectively reduced, and the packaging area can be reduced.

[0096] The following instructions Figures 1 to 12 , the optoelectronic system packaging structure and the preparation method thereof in this embodiment are further introduced.

[0097] First, see Figure 1 and Figure 2 , perform step S1 and provide a supporting substrate 100 .

[0098] Specifically, the support substrate 100 may include a glass substrate, a silicon substrate, a germanium substrate, etc., so as to provide a support function through the support substrate 100. There is no excessive restriction on the type of the support substrate 100, and it can be selected according to needs.

[0099] The supporting substrate 100 may include a wafer level or a substrate level, and the specific size may be selected according to the needs, and no excessive limitation is made here.

[0100] Furthermore, to facilitate the subsequent separation operation of the support substrate 100, a separation layer 200 may be formed on the surface of the support substrate 100, and the separation layer 200 may include one of a tape layer or a polymer layer to facilitate the peeling operation by laser irradiation or thermal processing.

[0101] Next, see Figure 1 and Figure 3 , executing step S2 to form a metal column 400 on the supporting substrate 100 .

[0102] Specifically, the metal column 400 may include but is not limited to one of a copper column, a silver column, a gold column, and a titanium column. When forming the metal column 400, a dielectric layer 300 can be first formed on the supporting substrate 100, and then the metal column 400 can be formed on the dielectric layer 300 by methods such as electroplating.

[0103] Next, see Figure 1 and Figure 3, execute step S3, provide an ASIC chip 500 and a TSV composite adapter board 600, bond the ASIC chip 500 and the TSV composite adapter board 600 to the support substrate 100, and the surface of the ASIC chip 500 has a first connector 501 electrically connected to the ASIC chip 500, and the surface of the TSV composite adapter board 600 has a second connector 601 electrically connected to the TSV composite adapter board 600.

[0104] Specifically, the first connector 501 is electrically connected to the pad on the ASIC chip 500, and the ASIC chip 500 can be electrically connected to external components through the first connector 501, and damage to the ASIC chip 500 can be avoided in the subsequent thinning operation. Similarly, the provision of the second connector 601 can realize the electrical connection between the TSV composite adapter board 600 and external components, and damage to the TSV composite adapter board 600 can be avoided in the subsequent thinning operation.

[0105] The TSV composite adapter board 600 may include a TSV layer and a rewiring layer located on the surface of the TSV layer and electrically connected to the TSV layer, so as to achieve a smaller line width / line spacing through the TSV composite adapter board 600 to meet the requirements of high-density electrical connection, wherein the line width of the TSV composite adapter board 600 may be 0.4μm to 1μm, such as 0.4μm, 0.5μm, 0.8μm, 1μm, etc., and the line spacing of the TSV composite adapter board 600 may be 0.4μm to 1μm, such as 0.4μm, 0.5μm, 0.8μm, 1μm, etc. The preparation and specific structure of the TSV composite adapter board 600 are not excessively limited here.

[0106] Next, see Figure 1 , Figure 4 and Figure 5 , executing step S4, forming a packaging layer 700 on the supporting substrate 100, the packaging layer 700 covers the ASIC chip 500, the TSV composite adapter 600 and the metal column 400, and exposes the metal column 400, the first connector 501 and the second connector 601.

[0107] Specifically, the material of the encapsulation layer 700 may include epoxy resin, etc., and the method of forming the encapsulation layer 700 may include compression molding, etc. After forming the encapsulation layer 700, the encapsulation layer 700 is preferably flattened by a grinding method to form a flat surface. The specific material and preparation method of the encapsulation layer 700 are not excessively limited here.

[0108] Next, see Figure 1 and Figure 6, executing step S5, forming a first rewiring layer 810 on the packaging layer 700, and the first rewiring layer 810 is electrically connected to the metal pillar 400, the first connector 501 and the second connector 601.

[0109] Specifically, the first rewiring layer 810 may be prepared by coating, exposing, developing, depositing, etching and other steps. The first rewiring layer 810 includes a dielectric layer and a metal wiring layer. The material of the dielectric layer may include one or a combination of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass. The material of the metal wiring layer may include one or a combination of copper, aluminum, nickel, gold, silver and titanium. The specific structure, material and preparation method of the first rewiring layer 810 are not overly limited here and can be selected according to needs.

[0110] Next, see Figure 1 and Figure 7 , execute step S6, provide a 3D stacked logic storage module 910, a storage module 920 and an optical module 930, and bond the 3D stacked logic storage module 910, the storage module 920 and the optical module 930 to the first rewiring layer 810, the 3D stacked logic storage module 910, the storage module 920 and the optical module 930 are all electrically connected to the first rewiring layer 810, and the 3D stacked logic storage module 910, the ASIC chip 500 and the optical module 930 are electrically connected, and the 3D stacked logic storage module 910, the TSV composite adapter board 600 and the storage module 920 are electrically connected.

[0111] Among them, since the 3D stacked logic storage module 910, the TSV composite adapter board 600 and the storage module 920 are electrically connected, the setting of the storage module 920 can further expand the storage unit in the horizontal direction, and the TSV composite adapter board 600 is used to bridge the 3D stacked logic storage module 910 and the storage module 920 to achieve high integration and high density connection. Since the 3D stacked logic storage module 910, the ASIC chip 500 and the optical module 930 are electrically connected, the electrical signal can be converted into an optical signal for transmission through the ASIC chip 500 and the optical module 930, thereby realizing optoelectronic interconnection.

[0112] The specific structures of the ASIC chip 500 and the optical module 930 are not limited here.

[0113] See also Fig.12 The 3D stacked logic storage module 910 preferably includes a stacked interconnected storage chip 912 and a back-side power supply logic chip 911, wherein Figure 10 to Figure 12 The steps of preparing the 3D stacked logic memory module 910 may include but are not limited to the following steps:

[0114] Providing a first semiconductor substrate 9111;

[0115] forming a first transistor layer 9112 on the front surface of the first semiconductor substrate 9111;

[0116] A first signal wiring layer 9113 is formed on the first transistor layer 9112, and the first signal wiring layer 9113 is electrically connected to the first transistor layer 9112;

[0117] forming a third rewiring layer 913 on the first signal wiring layer 9113, and the third rewiring layer 913 is electrically connected to the first signal wiring layer 9113;

[0118] A memory chip 912 is provided, wherein the memory chip 912 includes a stacked second semiconductor substrate 9121, a second transistor layer 9122, and a composite wiring layer 9123, wherein the composite wiring layer 9123 includes a second signal wiring layer and a second power wiring layer, and the second signal wiring layer and the second power wiring layer are both electrically connected to the second transistor layer 9122;

[0119] forming a fourth rewiring layer 914 on the composite wiring layer 9123, and the fourth rewiring layer 914 is electrically connected to the second signal wiring layer and the second power wiring layer;

[0120] Bonding the third rewiring layer 913 to the fourth rewiring layer 914, and electrically connecting the third rewiring layer 913 to the fourth rewiring layer 914;

[0121] Thinning the first semiconductor substrate 9111 from the back side of the first semiconductor substrate 9111;

[0122] forming a passivation layer 9114 on the back side of the first semiconductor substrate 9111;

[0123] A metal connection column 915 is formed to penetrate the passivation layer 9114, the first semiconductor substrate 9111, and the first transistor layer 9112, and a first end of the metal connection column 915 is electrically connected to the first signal wiring layer 9113 and the first transistor layer 9112;

[0124] A first power wiring layer 9115 is formed on the surface of the passivation layer 9114, and the first power wiring layer 9115 is electrically connected to the second end of the metal connection column 915;

[0125] A metal connection bump 916 is formed on the surface of the first power wiring layer 9115 , and the metal connection bump 916 is electrically connected to the first power wiring layer 9115 .

[0126] Among them, both the first semiconductor substrate 9111 and the second semiconductor substrate 9121 can be silicon substrates, but are not limited to this. The thickness of the first semiconductor substrate 9111 after thinning can be 1 to 10 μm, such as 1 μm, 2 μm, 3 μm, 5 μm, 8 μm, 10 μm, etc. The first semiconductor substrate 9111 reserved after thinning can protect the first transistor layer 9112 to avoid damaging the first transistor layer 9112. Regarding the specific thickness of the reserved first semiconductor substrate 9111, this embodiment is preferably 1 to 3 μm, so as to shorten the transmission path of power and signals as much as possible and reduce the package size. By thinning the first semiconductor substrate 9111, the thickness of the package structure can be effectively reduced, and in the vertical direction, due to the thinning of the first semiconductor substrate 9111, the transmission path of power and signals can be effectively shortened, the transmission efficiency can be improved, and the power consumption can be reduced.

[0127] The provision of the passivation layer 9114 can prevent short circuits caused by diffusion of metal materials into the first transistor layer 9112 when preparing the metal connection pillars 915. The passivation layer 9114 can include, for example, an epoxy resin layer, a polyamide layer, a silicon nitride layer, or a silicon oxide layer. The material, thickness, and preparation method of the passivation layer 9114 are not overly limited herein.

[0128] For further information, see Figure 8 After bonding the 3D stacked logic memory module 910, the TSV composite adapter board 600, and the memory module 920, a bottom filling layer 110 may be formed between the 3D stacked logic memory module 910, the TSV composite adapter board 600, the memory module 920, and the first rewiring layer 810, so as to protect the 3D stacked logic memory module 910, the TSV composite adapter board 600, and the memory module 920 through the bottom filling layer 110. The filling method and material type of the bottom filling layer 110 are not limited here, and can be selected according to needs.

[0129] Next, see Figure 1 and Figure 8 , perform step S7 to remove the supporting substrate 100 to expose the encapsulation layer 700 .

[0130] Specifically, due to the application of the separation layer 200, a peeling operation can be conveniently performed by laser irradiation or thermal processing to remove the separation layer 200 and the support substrate 100 for subsequent processes.

[0131] Next, see Figure 1 and Figure 8 , executing step S8 , forming a second rewiring layer 820 on the surface of the packaging layer 700 , and the second rewiring layer 820 is electrically connected to the metal pillar 400 .

[0132] Specifically, the material, structure and preparation of the second rewiring layer 820 may refer to the first rewiring layer 810 , which will not be described in detail here.

[0133] Next, see Figure 1 and Figure 8 , executing step S9, forming a metal bump 120 on the second re-distribution layer 820, and the metal bump 120 is electrically connected to the second re-distribution layer 820.

[0134] For details, see Figure 8 By setting the second rewiring layer 820, power can be provided vertically to the 3D stacked logic storage module 910, storage module 920 and optical module 930, thereby effectively shortening the transmission distance, making the signal transmission faster, and effectively reducing the transmission power consumption.

[0135] In this embodiment, a complete optoelectronic system packaging structure can be formed by stacking the 3D stacked logic storage module 910, the storage module 920, the optical module 930, the first rewiring layer 810, the second rewiring layer 820, the metal pillar 400, the ASIC chip 500 and the TSV composite adapter board 600, and the transmission distance of each module can be shortened, the signal transmission is faster, the transmission power consumption is effectively reduced, and the packaging area is reduced.

[0136] Furthermore, when the support substrate 100 is at the wafer level or substrate level, a cutting process step may be included to divide the prepared wafer level or substrate level packaging structure into a plurality of independently arranged packaging monomer structures to improve production efficiency. The cutting process may be mechanical cutting or laser cutting, which is not excessively limited here.

[0137] For further information, see Fig. 9 , and may further include the steps of providing a substrate 130 and bonding the substrate 130 to the metal bump 120, and the substrate 130 is electrically connected to the metal bump 120. The type and size of the substrate 130 are not limited herein.

[0138] For further information, see Fig. 9 , may further include the steps of providing a heat sink 140 and bonding the heat sink 140 to the substrate 130 .

[0139] Specifically, the heat sink 140 is in contact with the 3D stacked logic storage module 910, the storage module 920 and the optical module 930. By disposing the heat sink 140, good heat dissipation can be achieved for the 3D stacked logic storage module 910, the storage module 920 and the optical module 930. The specific type of the heat sink 140 is not excessively limited here.

[0140] See also Figure 2 to Figure 12 This embodiment further provides an optoelectronic system packaging structure, the optoelectronic system packaging structure comprising:

[0141] A first re-distribution layer 810, wherein the first re-distribution layer 810 includes a first surface and an opposite second surface;

[0142] 3D stacked logic memory module 910, memory module 920 and optical module 930, wherein the 3D stacked logic memory module 910, the memory module 920 and the optical module 930 are bonded to the first surface of the first rewiring layer 810, and the 3D stacked logic memory module 910, the memory module 920 and the optical module 930 are all electrically connected to the first rewiring layer 810;

[0143] A second re-distribution layer 820, wherein the second re-distribution layer 820 includes a first surface and an opposite second surface;

[0144] A metal pillar 400, wherein the metal pillar 400 is located between the second surface of the first re-distribution layer 810 and the first surface of the second re-distribution layer 820, and a first end of the metal pillar 400 is electrically connected to the first re-distribution layer 810, and a second end of the metal pillar 400 is electrically connected to the second re-distribution layer 820;

[0145] An ASIC chip 500 and a TSV composite adapter board 600, wherein the ASIC chip 500 and the TSV composite adapter board 600 are located between the second surface of the first rewiring layer 810 and the first surface of the second rewiring layer 820, the surface of the ASIC chip 500 has a first connector 501 electrically connected to the ASIC chip 500, the surface of the TSV composite adapter board 600 has a second connector 601 electrically connected to the TSV composite adapter board 600, the first connector 501 and the second connector 601 are both electrically connected to the first rewiring layer 810, and the 3D stacked logic storage module 910, the ASIC chip 500 and the optical module 930 are electrically connected, and the 3D stacked logic storage module 910, the TSV composite adapter board 600 and the storage module 920 are electrically connected;

[0146] The packaging layer 700 is located between the second surface of the first rewiring layer 810 and the first surface of the second rewiring layer 820, and covers the ASIC chip 500, the TSV composite adapter plate 600 and the metal pillar 400;

[0147] The metal bump 120 is located on the second surface of the second re-distribution layer 820 , and the metal bump 120 is electrically connected to the second re-distribution layer 820 .

[0148] As an example, the line width of the TSV composite adapter plate 600 is 0.4 μm to 1 μm, and the line spacing is 0.4 μm to 1 μm.

[0149] As an example, a substrate 130 electrically connected to the metal bump 120 is further included, and a heat sink 140 bonded to the substrate 130 is further included.

[0150] As an example, the 3D stacked logic memory module 910 includes a stacked and interconnected memory chip 912 and a backside power supply logic chip 911 .

[0151] Among them, the optoelectronic system packaging structure can be directly prepared using the above-mentioned preparation process, so the material, structure, etc. of the optoelectronic system packaging structure can refer to the above content and will not be repeated here. Of course, according to needs, the optoelectronic system packaging structure can also be prepared using other preparation processes.

[0152] In summary, the optoelectronic system packaging structure and preparation method of the present invention can form a complete optoelectronic system packaging structure by 3D stacking logic storage modules, storage modules, optical modules, rewiring layers, metal pillars, ASIC chips and TSV composite adapter boards, and can shorten the transmission distance of each module, speed up signal transmission, effectively reduce transmission power consumption, and reduce packaging area.

[0153] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing an optoelectronic system packaging structure, characterized in that: The following steps are involved: providing a supporting substrate; forming a metal column on the supporting substrate; Providing an ASIC chip and a TSV composite adapter board, bonding the ASIC chip and the TSV composite adapter board to the support substrate, wherein the surface of the ASIC chip has a first connector electrically connected to the ASIC chip, and the surface of the TSV composite adapter board has a second connector electrically connected to the TSV composite adapter board; Forming a packaging layer on the supporting substrate, wherein the packaging layer covers the ASIC chip, the TSV composite adapter plate and the metal column, and exposes the metal column, the first connector and the second connector; forming a first rewiring layer on the packaging layer, wherein the first rewiring layer is electrically connected to the metal pillar, the first connector, and the second connector; Providing a 3D stacked logic storage module, a storage module and an optical module, and bonding the 3D stacked logic storage module, the storage module and the optical module to the first rewiring layer, wherein the 3D stacked logic storage module, the storage module and the optical module are all electrically connected to the first rewiring layer, and the 3D stacked logic storage module, the ASIC chip and the optical module are electrically connected, and the 3D stacked logic storage module, the TSV composite adapter board and the storage module are electrically connected; removing the supporting substrate to expose the encapsulation layer; forming a second redistribution layer on the surface of the packaging layer, wherein the second redistribution layer is electrically connected to the metal pillar; A metal bump is formed on the second redistribution layer, and the metal bump is electrically connected to the second redistribution layer.

2. The method for preparing the optoelectronic system packaging structure according to claim 1, characterized in that: The method also includes the steps of providing a substrate and bonding the substrate to the metal bump, and the substrate is electrically connected to the metal bump.

3. The method for preparing the optoelectronic system packaging structure according to claim 2, characterized in that: The method also includes the steps of providing a heat sink and bonding the heat sink to the substrate.

4. The method for preparing the optoelectronic system packaging structure according to claim 1, characterized in that: The 3D stacked logic memory module includes stacked interconnected memory chips and back-side power supply logic chips, wherein the steps of preparing the 3D stacked logic memory module include: providing a first semiconductor substrate; forming a first transistor layer on the front surface of the first semiconductor substrate; forming a first signal wiring layer on the first transistor layer, wherein the first signal wiring layer is electrically connected to the first transistor layer; forming a third rewiring layer on the first signal wiring layer, wherein the third rewiring layer is electrically connected to the first signal wiring layer; A memory chip is provided, the memory chip comprising a stacked second semiconductor substrate, a second transistor layer and a composite wiring layer, the composite wiring layer comprising a second signal wiring layer and a second power wiring layer, and the second signal wiring layer and the second power wiring layer are both electrically connected to the second transistor layer; forming a fourth rewiring layer on the composite wiring layer, wherein the fourth rewiring layer is electrically connected to the second signal wiring layer and the second power wiring layer; Bonding the third rewiring layer to the fourth rewiring layer, and the third rewiring layer is electrically connected to the fourth rewiring layer; thinning the first semiconductor substrate from the back side of the first semiconductor substrate; forming a passivation layer on the back side of the first semiconductor substrate; forming a metal connection column penetrating the passivation layer, the first semiconductor substrate and the first transistor layer, wherein a first end of the metal connection column is electrically connected to both the first signal wiring layer and the first transistor layer; forming a first power wiring layer on the surface of the passivation layer, wherein the first power wiring layer is electrically connected to the second end of the metal connection column; A metal connection bump is formed on the surface of the first power wiring layer, and the metal connection bump is electrically connected to the first power wiring layer.

5. The method for preparing the optoelectronic system packaging structure according to claim 1, characterized in that: The line width of the TSV composite adapter plate is 0.4 μm to 1 μm, and the line spacing is 0.4 μm to 1 μm.

6. The method for preparing the optoelectronic system packaging structure according to claim 1, characterized in that: The method also includes forming a bottom filling layer between the first rewiring layer and the 3D stacked logic memory module, the memory module and the optical module.

7. An optoelectronic system packaging structure, characterized in that: The optoelectronic system packaging structure comprises: a first re-distribution layer, the first re-distribution layer comprising a first side and an opposite second side; 3D stacked logic storage module, storage module and optical module, wherein the 3D stacked logic storage module, the storage module and the optical module are bonded to the first surface of the first rewiring layer, and the 3D stacked logic storage module, the storage module and the optical module are all electrically connected to the first rewiring layer; a second redistribution layer, the second redistribution layer comprising a first side and an opposite second side; A metal column, wherein the metal column is located between the second surface of the first re-distribution layer and the first surface of the second re-distribution layer, and a first end of the metal column is electrically connected to the first re-distribution layer, and a second end of the metal column is electrically connected to the second re-distribution layer; An ASIC chip and a TSV composite adapter board, wherein the ASIC chip and the TSV composite adapter board are located between the second surface of the first rewiring layer and the first surface of the second rewiring layer, the surface of the ASIC chip has a first connector electrically connected to the ASIC chip, the surface of the TSV composite adapter board has a second connector electrically connected to the TSV composite adapter board, the first connector and the second connector are both electrically connected to the first rewiring layer, and the 3D stacked logic storage module, the ASIC chip and the optical module are electrically connected, and the 3D stacked logic storage module, the TSV composite adapter board and the storage module are electrically connected; A packaging layer, the packaging layer is located between the second surface of the first rewiring layer and the first surface of the second rewiring layer, and covers the ASIC chip, the TSV composite adapter plate and the metal pillar; A metal bump is located on the second surface of the second re-distribution layer and is electrically connected to the second re-distribution layer.

8. The optoelectronic system packaging structure according to claim 7, characterized in that: The line width of the TSV composite adapter plate is 0.4 μm to 1 μm, and the line spacing is 0.4 μm to 1 μm.

9. The optoelectronic system packaging structure according to claim 7, characterized in that: The invention also includes a substrate electrically connected to the metal bump and a heat sink bonded to the substrate.

10. The optoelectronic system packaging structure according to claim 7, characterized in that: The 3D stacked logic storage module includes stacked and interconnected storage chips and back-side power supply logic chips.

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