Semiconductor packaging structure, preparation method thereof and chip

Abstract

The invention relates to a semiconductor packaging structure, a preparation method thereof and a chip, and the semiconductor packaging structure comprises a substrate layer which comprises a substrate body with a first cavity and a second cavity; the power adjusting assembly comprises an MOS device and a magnetic core piece, the MOS device is installed in the first cavity, and the magnetic core piece is installed in the second cavity; and the metal layer comprises a coil part which is wound in the circumferential direction of the magnetic core piece. According to the semiconductor packaging structure, the inductor with low cost and high L / R is formed in the semiconductor packaging structure, so that the parasitic inductance can be reduced, and the current requirement can be quickly responded.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor device design and manufacturing, and in particular, to a semiconductor packaging structure and a preparation method thereof and a chip. Background Art

[0002] In the related technology, the power supply of semiconductor devices is usually converted from a higher voltage (12V or 48V) to a lower voltage (0.75-01V) through a regulating component on a PCB (printed circuit board). When the SOC (chip part) of the semiconductor device is high-power, a large current will flow through the PCB (for example, greater than 1000A at 1000W power). The large current on the printed circuit board will generate high Joule heat, thereby reducing the power delivered to the SOC. In addition, the printed circuit board and packaging structure have parasitic inductance, which will delay the power supply to the SOC when the large current increases, resulting in a decrease in the voltage at the SOC bump. Therefore, in order to maintain the circuit function at the same frequency, we need to increase the output voltage of the VRM (voltage regulation module), which will increase power consumption. Summary of the invention

[0003] The purpose of the present disclosure is to provide a semiconductor packaging structure, a preparation method and a chip thereof. The semiconductor packaging structure forms a low-cost, high L / R inductor inside the semiconductor packaging structure, which is beneficial to reducing parasitic inductance and can quickly respond to current demands, thereby at least partially solving related technical problems.

[0004] In order to achieve the above object, according to a first aspect of the present disclosure, a semiconductor package structure is provided, comprising: A substrate layer, comprising a substrate body having a first cavity and a second cavity; A power regulating component, comprising a MOS device and a magnetic core, wherein the MOS device is installed in the first cavity, and the magnetic core is installed in the second cavity; and The metal layer includes a coil portion wound around the circumference of the magnetic core.

[0005] Optionally, the substrate body further includes a third cavity, and the semiconductor packaging structure further includes a capacitor installed in the third cavity.

[0006] Optionally, the capacitor includes a DTC capacitor and / or a 3D MIM capacitor.

[0007] Optionally, the first cavity and the second cavity are respectively located on two sides of the third cavity.

[0008] Optionally, the substrate body further includes a plurality of through holes, and the metal layer includes a first metal layer located in the through holes.

[0009] Optionally, the substrate layer further includes a plurality of build-up layers formed on at least one side of the substrate body.

[0010] Optionally, the metal layer further includes a second metal layer located in the plurality of the build-up layers.

[0011] Optionally, the semiconductor package structure further comprises an isolation layer formed on a side of the build-up layer away from the substrate body, and the isolation layer is formed with a pad electrically connected to the metal layer.

[0012] Optionally, the substrate body is glass.

[0013] Optionally, the semiconductor package structure further includes a chip component located above the substrate body.

[0014] According to a second aspect of the present disclosure, a chip is provided, comprising the above-mentioned semiconductor package structure.

[0015] According to a third aspect of the present disclosure, a method for preparing a semiconductor package structure is also provided, the method comprising: Providing a substrate body; forming a first cavity and a second cavity in the substrate body; Embedding a MOS device in the first cavity and embedding a magnetic core in the second cavity; A metal layer including a coil portion wound around the circumference of the magnetic core is formed.

[0016] Optionally, the method further comprises: forming a third cavity in the substrate body; A capacitor is embedded in the third cavity.

[0017] Optionally, the method further comprises: forming a through hole in the substrate body; Copper is plated in the through hole or on the sidewall of the through hole to form a first metal layer that penetrates both sides of the substrate body.

[0018] Optionally, the forming includes a metal layer of a coil portion wound around the circumference of the magnetic core, including: After the MOS device, the magnetic core component and the capacitor component are embedded in the substrate body, one or more build-up layers are formed on the side of the substrate body; A metal layer is formed on the build-up layer to connect the MOS device and the capacitor.

[0019] Optionally, the method further comprises: forming an isolation layer on a side of the build-up layer away from the substrate body; A pad is formed on the isolation layer.

[0020] Optionally, the method further comprises: Provide chip parts; The chip component is connected to the pad.

[0021] Through the above technical solution, the semiconductor packaging structure disclosed in the present invention includes a substrate layer, a power regulating component and a metal layer, and the power regulating component is embedded in the substrate body of the semiconductor packaging structure, that is, the MOS device and the magnetic core are respectively installed in the first cavity and the second cavity of the substrate body, and a coil portion located in the circumference of the magnetic core is formed in the metal layer to form an inductor. Through the above arrangement, the semiconductor packaging structure disclosed in the present invention is conducive to reducing parasitic inductance by forming a low-cost, high L / R inductor inside the semiconductor packaging structure, and can quickly respond to current demand.

[0022] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure.

[0024] Figure 1 It is a connection structure diagram of a semiconductor packaging structure and a PCB in the related technology.

[0025] Figure 2 It is a power supply principle diagram of a semiconductor packaging structure in the related art.

[0026] Figure 3 is a structural diagram of a semiconductor packaging structure provided by some embodiments of the present disclosure.

[0027] Figure 4 This is a diagram of the connection structure between the semiconductor packaging structure and the PCB provided in some embodiments of the present disclosure.

[0028] Figures 5 to 16 It is a preparation flow chart of the semiconductor packaging structure provided by some embodiments of the present disclosure.

[0029] Description of Reference Numerals 10-semiconductor packaging structure; 20-inductor; 30-MOS device; 40-PCB board; 41-core power supply line; 42-return ground line; 110-substrate body; 111-first cavity; 112-second cavity; 113-third cavity; 114-through hole; 115-glue; 116-second copper plating layer; 120-build-up layer; 130-metal layer; 130a-first copper plating layer; 131-coil part; 132-first metal layer; 133-second metal layer; 140-isolation layer; 150-pad; 200-magnetic core parts; 300-MOS devices; 400-DTC capacitors; 500-chip parts. DETAILED DESCRIPTION

[0030] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0031] In this disclosure, unless otherwise stated, directional words such as "upper, lower, left, right" generally refer to the upper, lower, left, and right of the corresponding drawings; "inside and outside" refer to the outline of the corresponding parts themselves. The terms "first", "second", etc. used in this disclosure are to distinguish one element from another and do not have order or importance. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0032] like Figure 1 and Figure 2 As shown, it is a connection structure diagram of the semiconductor package structure 10 and the PCB board 40 in the related art, which is used for power supply of the semiconductor package structure. Among them, the power supply of the semiconductor device is usually converted from a higher voltage (12V or 48V) to a lower voltage (0.75-01V) through the regulating component (including the MOS device 30 and the inductor 20) on the PCB board 40 (printed circuit board), and provided to the semiconductor package structure 10 (Vdd) through the core power supply line 41. At the same time, the Vss of the semiconductor package structure 10 is connected to the return ground line 42 of the PCB board 40. When the chip 500 (such as SOC) of the semiconductor package structure 10 is high power, a large current will flow through the PCB board 40 (for example, more than 1000A at 1000W power). The high current on the printed circuit board will generate high Joule heat, which will reduce the power delivered to the SOC (chip). In addition, the printed circuit board and packaging structure have parasitic inductance, which will delay the power supply to the SOC when the high current increases, resulting in a decrease in the voltage at the SOC bump. Therefore, in order to maintain the circuit function at the same frequency, we need to increase the output voltage of the VRM (voltage regulation module), which will increase power consumption.

[0033] In order to achieve the above purpose, Figures 3 to 16As shown, according to the first aspect of the present disclosure, a semiconductor packaging structure is provided, which includes a substrate layer, a power regulating component and a metal layer 130. The substrate layer includes a substrate body 110 having a first cavity 111 and a second cavity 112; the power regulating component includes a MOS device 300 and a magnetic core 200, the MOS device 300 is installed in the first cavity 111, and the magnetic core 200 is installed in the second cavity 112. The metal layer 130 includes a coil portion 131 wound around the magnetic core 200, which can cooperate with the magnetic core 200 to form a low-cost, high L / R inductor.

[0034] Through the above technical solution, that is, the semiconductor packaging structure disclosed in the present invention includes a substrate layer, a power regulating component and a metal layer 130, and the power regulating component is embedded in the substrate body 110 of the semiconductor packaging structure, that is, the MOS device 300 and the magnetic core part 200 are respectively installed in the first cavity 111 and the second cavity 112 of the substrate body 110, and a coil part 131 located in the circumference of the magnetic core part 200 is formed in the metal layer 130 to form an inductor. Through the above arrangement, the semiconductor packaging structure disclosed in the present invention is conducive to reducing parasitic inductance by forming a low-cost, high L / R inductor inside the semiconductor packaging structure, and can quickly respond to current requirements. At the same time, corresponding to the higher-power chip part 500, a high voltage (relative to 0.75-01V) can also be provided on the substrate of the PCB, and at the same time, the initial voltage can be reduced from 12V to 3-4.8V, such as Figure 4 As shown, the circuit between the core power supply line and the return ground line can be 12V, 48V, or can be reduced to 3-5V. For example, the voltage at the connection between the PCB and Vdd can be 3-12V.

[0035] It should be noted that the metal layer 130 also includes a first metal layer 132 and a second metal layer 133, wherein the first metal layer 132 is located in the through hole 114 of the substrate body 110 and passes through the top and bottom of the substrate body 110 to achieve electrical connection on both sides; and the second metal layer 133 is formed between the multiple layers 120, and is used to connect the MOS device 300, the capacitor component and the PCB (printed circuit board) and the SOC (chip component 500), which will be described in detail in the following embodiments.

[0036] In some embodiments, the substrate body 110 includes but is not limited to a glass substrate, and may also be a substrate body 110 made of other materials.

[0037] Optionally, the substrate body 110 further includes a third cavity 113, and the semiconductor package structure further includes a capacitor installed in the third cavity 113. The capacitor includes a DTC capacitor 400 and / or a 3D MIM capacitor. Under the premise that the substrate body 110 is a glass substrate, since the thermal expansion coefficient of the DTC capacitor 400 and / or the 3D MIM capacitor used is close to that of the glass substrate, the stress of the capacitor can be reduced, the risk of cracking can be reduced, and the reliability can be increased.

[0038] It should be noted that the substrate body 110 may also adopt other substrate structures, and the capacitor may also be other forms of capacitors.

[0039] The positions of the first cavity 111, the second cavity 112 and the third cavity 113 can be arranged in any suitable manner. In some embodiments, the first cavity 111 and the second cavity 112 are respectively located on both sides of the third cavity 113. Therefore, the MOS device 300 in the first cavity 111, the magnetic core 200 in the second cavity 112 and the capacitor in the third cavity 113 can be arranged in sequence, so that the current passes through the MOS device 300 and then reaches the capacitor through the inductor formed by the magnetic core 200 and the coil part 131, reducing the length of the metal layer 130 and saving space. Of course, the first cavity 111 and the second cavity 112 can also be arranged in other ways to meet the power supply connection, and the inductor formed by the magnetic core 200 and the coil part 131 can be arranged on the power supply line.

[0040] In some embodiments, the substrate body 110 is further formed with a plurality of through holes 114 penetrating two opposite side surfaces thereof, and a first metal layer 132 is formed in the through holes 114. The first metal layer 132 acts as a part of the metal layer 130 and is used for electrical connection between two sides of the substrate body 110. The first metal layer 132 may be made of copper. For example, the first metal layer 132 may be formed by copper plating, photolithography, and etching.

[0041] like Fig.16 As shown, there are five through holes 114, wherein one through hole 114 is located on the left side of the MOS device 300 for connecting to the Vdd pad 150; one through hole 114 is located between the MOS device 300 and the magnetic core 200, and one through hole 114 is located between the magnetic core 200 and the DTC capacitor 400, forming two ends of the coil portion 131; two through holes 114 are located on the right side of the DTC capacitor 400, one for connecting the DTC capacitor 400 and the Vss pad 150, and the other for signal connection between the PCB and the SOC.

[0042] In some embodiments, the semiconductor package structure includes a plurality of build-up layers 120 disposed on at least one side of a substrate body 110. Typically, a plurality of build-up layers 120 are formed on both sides of the substrate body 110, and a plurality of second metal layers 133 are sequentially connected between the plurality of build-up layers 120 to achieve electrical connection with the pads 150 at the outermost build-up layers 120.

[0043] It is understandable that the build-up layer 120 may adopt a structural layer and an arrangement method known in the related art. For example, the build-up layer 120 may be an ABF layer (Ajinomoto Build-up Film Layer, Ajinomoto build-up film layer).

[0044] In order to achieve connection with the chip component 500, in some embodiments, the metal layer 130 also includes a second metal layer 133 formed between the multiple build-up layers 120, the second metal layer 133 in the multiple build-up layers 120 above the substrate body 110 is used to connect with the chip component 500 (for example, SOC), and the second metal layer 133 in the multiple build-up layers 120 below the substrate body 110 is used to connect with the PCB to achieve power supply, grounding and signal communication.

[0045] Optionally, the semiconductor package structure further includes an isolation layer 140 formed on a side of the buildup layer 120 away from the substrate body 110, and the isolation layer 140 is formed with a pad 150 connected to the second metal layer 133. A pad 150 window can be formed in the isolation by laser drilling, and a pad 150 electrically connected to the second metal layer 133 is formed in the pad 150 window. The buildup layer 120 can be a multi-layer structure, and the second metal layer 133 can be multiple and distributed between multiple buildup layers 120, and the electrical connection of multiple second metal layers 133 is achieved by arranging a through hole 114 in each buildup layer 120 and forming a metal conductive layer in the through hole 114.

[0046] like Figure 3 and Figure 4 As shown, in some embodiments of the present disclosure, the semiconductor package structure further includes a chip component 500 located above the substrate layer. The chip component 500, such as a SOC, can be connected by welding with a pad 150 above the substrate layer.

[0047] It can be understood that the capacitor component is located inside the cavity of the substrate body 110 below the chip component 500, for example, it can be directly below. Such an arrangement enables the chip component 500 to be vertically connected to the capacitor component, and the ESL and ESR from the capacitor component to the pad 150 of the chip component 500 above will be much lower. At the same time, the AC noise will be reduced.

[0048] According to a second aspect of the present disclosure, a chip is provided, which includes the above-mentioned semiconductor packaging structure. Therefore, the chip also has all the advantages of the above-mentioned semiconductor packaging structure, which will not be described one by one here.

[0049] like Figures 5 to 16 According to a third aspect of the present disclosure, a method for preparing a semiconductor packaging structure is also provided, the method comprising the following steps: A substrate body 110 is provided.

[0050] A first cavity 111 and a second cavity 112 are formed in the substrate body 110 .

[0051] The MOS device 300 is embedded in the first cavity 111 , and the magnetic core 200 is embedded in the second cavity 112 .

[0052] The metal layer 130 including the coil portion 131 wound around the circumference of the magnetic core member 200 is formed.

[0053] The preparation method disclosed in the present invention forms a first cavity 111 and a second cavity 112 on a substrate body 110, and embeds a MOS device 300 and a magnetic core piece 200 into the first cavity 111 and the second cavity 112 respectively, and then forms a metal layer 130, wherein the metal layer 130 includes a coil portion 131 wound around the circumference of the magnetic core piece 200, and the coil portion 131 forms an inductor with the magnetic core piece 200 in the second cavity 112. Through the above method, a low-cost inductor with a high L / R can be formed inside the semiconductor packaging structure to reduce parasitic inductance and quickly respond to current demand.

[0054] In order to embed the capacitor into the substrate body 110, Figure 7 As shown, in some embodiments, the method further includes: A third cavity 113 is formed in the substrate body 110 .

[0055] A capacitor is embedded in the third cavity 113 .

[0056] Among them, the first cavity 111 can be formed first, and then the magnetic core 200 is embedded in the first cavity 111, and then the second cavity 112 and the third cavity 113 are formed. In addition, the third cavity 113 and the first cavity 111 and the second cavity 112 can be formed together, and are formed on the glass substrate by laser or etching. The capacitor can be a DTC capacitor 400 and / or a 3D MIM capacitor. Those skilled in the art can allocate the order of forming the first cavity 111, the second cavity 112 and the third cavity 113 in any way, and install the magnetic core 200, the MOS device 300 and the capacitor in any way if it is feasible, and they will not be repeated here.

[0057] In order to realize electrical connection or signal connection on both sides of the substrate body 110, as Figure 7 As shown, in some embodiments, the method may further include: A through hole 114 is formed in the substrate body 110 .

[0058] Copper is plated in the through hole 114 or on the sidewall of the through hole 114 to form a first metal layer 132 that penetrates both sides of the substrate body 110 .

[0059] The through hole 114 can also be formed in one step with the first cavity 111, the second cavity 112, and the third cavity 113, and then the copper plating on the surface of the substrate body 110 is removed by copper plating, photolithography and etching to form the first metal layer 132 inside the through hole 114.

[0060] It should be noted that, in some embodiments, the method further includes, after the steps of embedding the MOS device 300 in the first cavity 111 and embedding the magnetic core 200 in the second cavity 112, forming a build-up layer 120 on the substrate body 110. A metal layer 130 is formed on the substrate body 110 and the build-up layer 120, and the metal layer 130 includes a coil portion 131 wound around the circumference of the magnetic core 200. By means of the above method, a first cavity 111 and a second cavity 112 are formed on the substrate body 110, and the MOS device 300 and the magnetic core piece 200 are respectively embedded in the first cavity 111 and the second cavity 112, and then a build-up layer 120 is formed on the substrate body 110, and a metal layer 130 is formed on the build-up layer 120, wherein the metal layer 130 includes a coil portion 131 wound around the circumference of the magnetic core piece 200, and the coil portion 131 forms an inductor with the magnetic core piece 200 in the second cavity 112. By means of the above method, a low-cost inductor with a high L / R ratio can be formed inside the semiconductor packaging structure to reduce parasitic inductance and quickly respond to current demand.

[0061] In some embodiments, the step of forming a metal layer including a coil portion wound around the circumference of the magnetic core member includes: After the MOS device 300 , the magnetic core 200 and the capacitor are respectively embedded in the first cavity 111 , the second cavity 112 and the third cavity 113 of the substrate body 110 , one or more build-up layers 120 are formed on the side of the substrate body 110 .

[0062] A metal layer 130 is formed on the build-up layer 120 to connect the MOS device 300 and the capacitor.

[0063] The specific steps include: after embedding the MOS device 300, the magnetic core component 200 and the capacitor component, as shown in FIG. Fig.12 and Fig.13As shown, a build-up layer 120 is first formed on both sides of the substrate body 110, and a metal layer 130 is formed on the surface of the build-up layer 120 by drilling and metallization; then, a metal layer 130 structure is formed by photolithography and etching to connect the first metal layer 132 with the MOS device 300, the MOS device 300 with one end of the coil part 131, the other end of the coil part 131 with the first metal layer 132, the first metal layer 132 with the DTC capacitor 400, and the DTC capacitor 400 with the first metal layer 132 on the right side, so as to realize the connection between the MOS device 300 and the DTC capacitor 400. Among them, metal connecting parts are formed above and below the first metal layer 132 at the rightmost through hole 114.

[0064] like Fig.14 As shown, finally, the step of forming the build-up layer 120 is repeated to multiple layers, and a second metal layer 133 is formed between the multiple build-up layers 120 through a metallization process.

[0065] like Fig.15 As shown, in some embodiments, the method further includes: An isolation layer 140 is formed on a side of the build-up layer 120 away from the substrate body 110 .

[0066] A pad 150 is formed on the isolation layer 140 .

[0067] The isolation layer 140 is formed on the build-up layer 120 mainly to isolate the pads 150 formed in the subsequent steps from penetrating into the build-up layer 120, and any suitable material known in the relevant technology can be used. Then, the isolation layer 140 is photolithographically and etched to form a pad 150 window, and the pad 150 is formed at the corresponding pad 150 window by pre-soldering printing and reflow soldering, and the pad 150 is connected to the second metal layer 133.

[0068] like Fig.16 As shown, in some embodiments, the method further includes: A chip component 500 is provided.

[0069] The chip component 500 is connected to the pad 150 .

[0070] The chip component 500 may be a SOC chip, and the chip component 500 is connected to the pad 150 above the substrate to realize chip assembly. It should be noted that the pad 150 on the other side of the substrate body 110 away from the chip component 500 is used to connect to the PCB board, including but not limited to core power supply, grounding and signal connection.

[0071] refer to Figures 5 to 16 As shown, the present disclosure uses a specific embodiment to describe in detail the manufacturing process of a semiconductor packaging structure.

[0072] like Figure 5 As shown, a glass substrate is provided, and a first cavity 111 is formed on the glass substrate.

[0073] like Figure 6 As shown, the magnetic core 200 is embedded in the first cavity 111 .

[0074] like Figure 7 As shown, a second cavity 112, a third cavity 113 and a plurality of through holes 114 are formed on a glass substrate.

[0075] like Figure 8 As shown, on the surface of the glass substrate, the sidewalls of the second cavity 112 , the third cavity 113 and the plurality of through holes 114 are copper plated to form a first copper plated layer 130 a .

[0076] like Fig. 9 As shown, a MOS device 300 is embedded in the second cavity 112 , a DTC capacitor 400 is embedded in the third cavity 113 , and glue 115 is used to fill the gaps between the components and the side walls.

[0077] like Fig.10 As shown, the copper plating on the surface of the glass substrate is removed by patterning or mechanical polishing to form a first metal layer 132 in the through hole 114 .

[0078] like Fig.11 As shown, copper is plated on the surface of the glass substrate to form a second copper plated layer 116, and the second copper plated layer 116 on the surface of the glass substrate is removed by graphic processing or mechanical polishing, leaving the second copper plated layer 116 corresponding to the first metal layer 132 and the connection ends of the MOS device 300 and the DTC capacitor 400.

[0079] like Fig.12 As shown, an ABF layer is formed on the upper surface and the lower surface of the glass substrate body 110 respectively.

[0080] like Fig.13 As shown, openings corresponding to the through hole 114 and the DTC capacitor 400 are formed in the ABF layer by laser drilling, and a copper plating layer is formed in the ABF layer and the opening; then, a metal layer 130 is formed by patterning, or photolithography and etching to connect the MOS device 300 and the DTC capacitor 400, and a coil portion 131 is formed in the circumferential direction of the magnetic core 200.

[0081] like Fig.14 As shown, the ABF layer and the copper circuit (copper plating layer metallization) are repeatedly formed and cycled to multiple layers.

[0082] like Fig.15As shown, an isolation layer 140 (SR Coating) is formed on the surface of the outermost ABF layer; the isolation layer 140 (SR Coating) is photolithographically etched to form a pad 150 window; and the pad 150 is formed at the corresponding pad 150 window by pre-soldering printing and reflow soldering.

[0083] like Fig.16 As shown, the SOC chip is soldered to the pad 150 .

[0084] The semiconductor packaging structure and its preparation method and chip disclosed in the present invention embed the magnetic core 200 into the glass substrate, and use the through hole 114 (TGV, Through Glass Via) and RDL (Redistribution layer) process, such as metal layer 130, to form a high L / R, low-cost inductor in the semiconductor packaging structure; at the same time, the switch MOS device 300 is embedded in the glass substrate. Since the thermal expansion coefficient of the glass substrate is close to that of silicon, thermal stress can be reduced and the risk of cracks in the MOS device 300 can be reduced. At the same time, a capacitor (such as a DTC capacitor 400 or a 3D MIM capacitor) is embedded in the glass substrate. The capacitor has a low ESL (equivalent series inductance) and ESR (equivalent series resistance), which can quickly respond to system requirements and reduce AC noise when the circuit is turned on and off. In addition, when corresponding to a relatively large power-ready SOC, a high voltage (relative to 0.75-1V in the related art) can be provided on the PCB substrate, and the initial voltage can be reduced from 12V to 3-4.8V.

[0085] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings; however, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, a variety of simple modifications can be made to the technical solution of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.

[0086] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.

[0087] In addition, various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.

Claims

1. A semiconductor packaging structure, characterized in that: include: A substrate layer, comprising a substrate body having a first cavity and a second cavity; A power regulating component, comprising a MOS device and a magnetic core, wherein the MOS device is installed in the first cavity, and the magnetic core is installed in the second cavity; as well as The metal layer includes a coil portion wound around the circumference of the magnetic core.

2. The semiconductor package structure according to claim 1, wherein: The substrate body further includes a third cavity, and the semiconductor package structure further includes a capacitor installed in the third cavity.

3. The semiconductor package structure according to claim 2, wherein: The capacitor includes a DTC capacitor and / or a 3D MIM capacitor.

4. The semiconductor package structure according to claim 2, wherein: The first cavity and the second cavity are respectively located on two sides of the third cavity.

5. The semiconductor package structure according to claim 1, wherein: The substrate body further includes a plurality of through holes, and the metal layer includes a first metal layer located in the through holes.

6. The semiconductor package structure according to claim 1, wherein: The substrate layer further includes a plurality of build-up layers formed on at least one side of the substrate body.

7. The semiconductor package structure according to claim 6, characterized in that: The metal layer further includes a second metal layer located within the plurality of build-up layers.

8. The semiconductor package structure according to claim 6, wherein: The semiconductor package structure further includes an isolation layer formed on a side of the build-up layer away from the substrate body, and the isolation layer is formed with a pad electrically connected to the metal layer.

9. The semiconductor package structure according to any one of claims 1 to 8, characterized in that: The substrate body is glass.

10. The semiconductor package structure according to any one of claims 1 to 8, characterized in that: The semiconductor package structure further includes a chip component located above the substrate layer.

11. A chip, characterized in that: A semiconductor packaging structure comprising any one of claims 1-10.

12. A method for preparing a semiconductor packaging structure, characterized in that: The method comprises: Providing a substrate body; forming a first cavity and a second cavity in the substrate body; Embedding a MOS device in the first cavity and embedding a magnetic core in the second cavity; A metal layer including a coil portion wound around the circumference of the magnetic core is formed.

13. The method for preparing a semiconductor packaging structure according to claim 12, characterized in that: The method further comprises: forming a third cavity in the substrate body; A capacitor is embedded in the third cavity.

14. The method for preparing a semiconductor packaging structure according to claim 13, characterized in that: The method further comprises: forming a through hole in the substrate body; Copper is plated in the through hole or on the sidewall of the through hole to form a first metal layer that penetrates both sides of the substrate body.

15. The method for preparing a semiconductor packaging structure according to claim 14, characterized in that: The forming includes a metal layer of a coil portion wound around the circumference of the magnetic core, including: After the MOS device, the magnetic core component and the capacitor component are embedded in the substrate body, one or more build-up layers are formed on the side of the substrate body; A metal layer is formed on the build-up layer to connect the MOS device and the capacitor.

16. The method for preparing a semiconductor packaging structure according to claim 15, characterized in that: The method further comprises: forming an isolation layer on a side of the build-up layer away from the substrate body; A pad is formed on the isolation layer.

17. The method for preparing a semiconductor packaging structure according to claim 16, characterized in that: The method further comprises: Provide chip parts; The chip component is connected to the pad.

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