Semiconductor packaging structure and preparation method thereof

Abstract

The invention relates to a semiconductor packaging structure and a preparation method thereof, the semiconductor packaging structure comprises a substrate and a capacitor, and the substrate comprises a glass substrate body with a cavity; the capacitor is embedded in the cavity. According to the semiconductor packaging structure, the capacitor is mounted in the cavity of the glass substrate body, so that the thickness of the glass substrate body can be reduced without warping, and a large-size packaging structure is met.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor design and preparation, and in particular, to a semiconductor packaging structure and a preparation method thereof. Background Art

[0002] Currently, in order to reduce the equivalent series inductance and resistance, silicon capacitors are embedded in the cavity of the substrate and then packaged. In related technologies, in order to control the warping of the substrate, the thickness of the substrate is usually greater than 1000 microns, while the thickness of a typical silicon capacitor is usually less than 775 microns. The position of the silicon capacitor in the cavity of the substrate may be offset. In addition, since the thermal expansion coefficient of the substrate is usually higher than that of the silicon capacitor, the silicon capacitor generates high stress, which poses a reliability risk during the temperature cycle process. Summary of the invention

[0003] The purpose of the present disclosure is to provide a semiconductor packaging structure and a preparation method thereof, wherein the semiconductor packaging structure installs a capacitor in a cavity of a glass substrate body, and can reduce the thickness of the glass substrate body without warping to meet the needs of a large-sized packaging structure.

[0004] In order to achieve the above object, according to a first aspect of the present disclosure, a semiconductor package structure is provided, comprising: A substrate including a glass substrate body having a cavity; and The capacitor is embedded in the cavity.

[0005] Optionally, the thickness of the glass substrate body corresponds to the thickness of the capacitor.

[0006] Optionally, the glass substrate body has a thickness less than or equal to 770 μm.

[0007] Optionally, the capacitor includes a DTC capacitor and / or a 3D MIM capacitor.

[0008] Optionally, the glass substrate body further includes a through hole, and the semiconductor package structure further includes a first metal layer located in the through hole.

[0009] Optionally, the substrate further comprises at least one build-up layer disposed on each side of the glass substrate body.

[0010] Optionally, the substrate further comprises an isolation layer formed on a side of the stacked layer away from the glass substrate body; The semiconductor package structure further includes a second metal layer formed between the build-up layers, and the isolation layer is formed with a pad connected to the second metal layer.

[0011] Optionally, the semiconductor package structure further includes a chip component located above the substrate.

[0012] According to a second aspect of the present disclosure, a method for preparing a semiconductor packaging structure is also provided, the method comprising: Providing a glass substrate body; forming a cavity on the glass substrate body; A capacitor is installed in the cavity.

[0013] Optionally, the method further comprises: forming a through hole on the glass substrate body; A first metal layer is formed in the through hole.

[0014] Optionally, forming a first metal layer in the through hole includes: forming a first metal layer on the surface of the glass substrate body, the sidewall of the cavity, and the sidewall of the through hole; Disposing a carrier layer at the bottom of the glass substrate body; Installing a capacitor in the cavity; Filling an insulating layer in the through hole and the cavity; The carrier layer and the first metal layer on the surface of the glass substrate body are removed.

[0015] Optionally, the method further comprises: forming one or more build-up layers on the surface of the glass substrate body; At least one second metal layer connected to the capacitor and / or the first metal layer is formed in the build-up layer.

[0016] Optionally, the method further comprises: forming an isolation layer on the side of the outermost layer away from the glass substrate body; A pad connected to the second metal layer is formed on the isolation layer to form a substrate.

[0017] Optionally, the method further comprises: Provide chip parts; The chip component is connected to the pad above the substrate.

[0018] Through the above technical solution, that is, the semiconductor packaging structure disclosed in the present invention includes a substrate and a capacitor. The substrate includes a glass substrate body with a cavity, and the capacitor is installed in the cavity. Since the glass substrate body has a high elastic modulus and good strength, when it uses a smaller thickness size, for example, less than or equal to 1000 microns, it will not produce a large warp. Therefore, this structure can meet the needs of a larger packaging structure.

[0019] Furthermore, the capacitor may be a DTC capacitor and / or a 3D MIM capacitor, which has a thermal expansion coefficient close to that of the glass substrate body, thereby reducing stress of the capacitor and increasing reliability.

[0020] Furthermore, since the capacitor is directly embedded in the cavity of the glass substrate body of the substrate, it has low ESL / ESR characteristics and can also reduce high-frequency power noise.

[0021] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure.

[0023] Figure 1 It is a structural diagram of a semiconductor packaging structure in the related art.

[0024] Figure 2 is a structural diagram of a semiconductor packaging structure provided by some embodiments of the present disclosure.

[0025] Figures 3 to 16 It is a preparation flow chart of the semiconductor packaging structure provided by some embodiments of the present disclosure.

[0026] Description of Reference Numerals 11-substrate body; 12-layer; 20-silicon capacitor; 100-substrate; 110-glass substrate body; 111-cavity; 112-through hole; 120-build-up layer; 130-isolation layer; 131-pad window; 140a-first copper plating layer; 140b-second copper plating layer; 141-first metal layer; 142-second metal layer; 150-pad; 160-insulating layer; 200-capacitors; 300-chip parts; 400-Carrier. DETAILED DESCRIPTION

[0027] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0028] In this disclosure, unless otherwise stated, directional words such as "upper, lower, left, right" generally refer to the upper, lower, left, and right of the corresponding drawings; "inside and outside" refer to the outline of the corresponding parts themselves. The terms "first", "second", etc. used in this disclosure are to distinguish one element from another and do not have order or importance. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0029] like Figure 1 As shown, it is a schematic diagram of a semiconductor packaging structure in the related art. The semiconductor packaging structure includes a substrate and a chip part 300 (such as a SOC chip) connected to the substrate through a pad, wherein the substrate includes a substrate body 11 and a plurality of stacked layers 12 formed on the upper and lower sides of the substrate body 11. Through holes and cavities are formed on the substrate body 11, and the silicon capacitor 20 is bonded to the inside of the cavity of the substrate body 11 by glue. In order to prevent the substrate from warping, the thickness H1 of the substrate body 11 is usually greater than 1000 microns, while the thickness of a typical silicon capacitor 20 is usually less than 775 microns. The position of the silicon capacitor in the cavity may be offset. In addition, since the thermal expansion coefficient of the substrate body 11 is usually higher than that of the silicon capacitor 20, the silicon capacitor 20 generates high stress, and there is a reliability risk during the temperature cycle process.

[0030] Based on this, the purpose of the present disclosure is to provide a semiconductor packaging structure and a preparation method thereof. The substrate body of the semiconductor packaging structure adopts a glass substrate body 110, and the capacitor 200 is installed in the cavity 111 of the glass substrate body 110. When the thickness of the glass substrate body 110 is reduced, warping will not occur, thereby meeting the needs of a larger packaging structure.

[0031] In order to achieve the above purpose, Figures 2 to 12 As shown, according to the first aspect of the present disclosure, a semiconductor package structure is provided, which includes a substrate 100 and a capacitor 200. The substrate 100 includes a glass substrate body 110 having at least one cavity 111, and the capacitor 200 is embedded in the cavity 111.

[0032] The semiconductor packaging structure disclosed in the present invention includes a substrate 100 and a capacitor 200, wherein the substrate 100 includes a glass substrate body 110 having a cavity 111, and the capacitor 200 is installed in the cavity 111. Since the glass substrate body 110 has a higher elastic modulus, its thickness can be arranged to be smaller. For example, when it uses a smaller thickness size, such as less than or equal to 1000 microns, it can also be used for a larger packaging structure without causing a large warp.

[0033] The glass substrate body 110 may be a doped glass fiber substrate 100, on which at least one build-up layer 120 is typically formed, such as an ABF layer (Ajinomoto Build-up Film Layer). In this structure, the glass substrate body 110 is required to have a higher mechanical strength than the ABF layer. For large packaging structures, the thickness of the conventional substrate 100 body is increased to about 1000 μm or more (typically above 1200 μm) to increase the mechanical strength of the substrate 100 body and reduce warping. However, in the actual preparation process, it is difficult to embed the capacitor 200 into a substrate 100 with a thickness of more than 800 μm without offset.

[0034] It should be noted that the capacitor 200 may include a DTC capacitor and / or a 3D MIM capacitor. Since the thermal expansion coefficient of the DTC capacitor and / or the 3D MIM capacitor used is close to that of the glass substrate body 110, the stress of the capacitor 200 can be reduced, the risk of cracking thereof can be reduced, and the reliability can be increased.

[0035] In some embodiments, the capacitor 200 embedded in the cavity 111 may include, for example, a DTC and a 3D MIM capacitor. A DTC capacitor is one of the capacitors 200, which can form a DTC by opening a cavity 111 or a groove in the glass substrate body 110. At the same time, for a portion of the glass substrate body 110 that does not have the conditions for forming a DTC, other forms of capacitors 200 may be used.

[0036] like Figure 2 As shown, in some embodiments, the thickness H2 of the glass substrate body 110 is matched with the thickness of the capacitor 200. For example, the thickness H2 of the glass substrate body 110 can be comparable to the thickness of the capacitor 200. Considering that the thickness of the capacitor 200 to be embedded may be between 50-760 μm, a glass substrate body 110 of comparable thickness can be configured accordingly. For example, the thickness H2 of the glass substrate body 110 is less than 1000 μm or less than 800 μm. In some preferred embodiments, the thickness H2 of the glass substrate body 110 is less than or equal to 770 μm. It can be understood that the thickness H2 of the glass substrate body 110 can be appropriately adjusted according to the need to embed DTC capacitors and / or 3DMIM capacitors of different thickness sizes.

[0037] Therefore, the capacitor 200 and the stacking layer 120 or the capacitor 200 and the stacking layer 120 and the glass substrate body 110 can be adapted by adjusting the thickness H2 of the glass substrate body 110, adjusting the thickness of the applied stacking layer 120, adjusting the thickness of the capacitor 200 to be embedded, or a combination of the above adjustments. This avoids the situation where the capacitor 200 of smaller thickness is not compatible with the substrate 100 body with larger thickness, resulting in the problem that the position of the silicon capacitor is easy to move and affects the reliability. It should be noted that, since the elastic modulus of the glass substrate body 110 is higher, the strength requirement can be met at a smaller thickness. At the same time, since the thickness H2 of the glass substrate body 110 is reduced, the thickness of the substrate 100 of the entire semiconductor packaging structure can also be reduced accordingly, realizing the miniaturization of the packaging structure and reducing space occupancy.

[0038] In order to achieve Vdd, Vss and signal connection with the printed circuit board, in some embodiments, the glass substrate body 110 further includes a plurality of through holes 112, and the through holes 112 can penetrate the two sides of the glass substrate body 110 in the thickness direction, and the semiconductor package structure further includes a first metal layer 141 located in the through holes 112. There are multiple through holes 112, such as Figure 2 As shown, the present disclosure takes three through holes 112 and three first metal layers 141 respectively arranged in the three through holes 112 as an example, wherein one through hole 112 and the first metal layer 141 in the through hole 112 are located on the left side of the capacitor 200, and the upper part is used to connect with the chip part 300 and the capacitor 200, and the lower part is used to connect with the Vdd pad 150; another through hole 112 and the first metal layer 141 in the through hole 112 are located on the right side of the capacitor 200, and the upper part is used to connect with the chip part 300 and the capacitor 200, and the lower part is used to connect with the Vss pad 150; the leftmost through hole 112 and the first metal layer 141 in the through hole 112 are used to connect the chip part 300 and the signal pad 150.

[0039] In some embodiments, the semiconductor package structure further includes at least one build-up layer 120 disposed on each side of the glass substrate body 110. Typically, a plurality of build-up layers 120 are formed on both sides of the glass substrate body 110, and a plurality of second metal layers 142 are sequentially connected between the plurality of build-up layers 120 to achieve electrical connection with the pads 150 at the outermost build-up layers 120.

[0040] It should be noted that one or more cavities 111 can be formed in multiple layers 120, and part of the capacitor 200 can be embedded in the one or more cavities 111. It should be noted that at this time, the thickness of the embedded capacitor 200 needs to be adapted to the thickness of the cavity 111 to be embedded.

[0041] The build-up layer 120 may adopt a structure layer and arrangement method known in the related art. For example, the build-up layer 120 may be an ABF layer (Ajinomoto Build-up Film Layer, Ajinomoto build-up film layer) in order to achieve connection with the chip component 300. Figure 2 As shown, in some embodiments, the substrate 100 further includes an isolation layer 130 formed on the side of the build-up layer 120 away from the glass substrate body 110; the semiconductor package structure further includes a second metal layer 142 formed between the build-up layers 120, and the isolation layer 130 is formed with a pad 150 connected to the second metal layer 142. The build-up layer 120 may be a multi-layer structure, and there may be multiple second metal layers 142, which are distributed between multiple build-up layers 120, and the electrical connection of multiple second metal layers 142 is achieved by arranging a through hole 112 in each build-up layer 120 and forming a metal conductive layer in the through hole 112.

[0042] It is understandable that the isolation layer 130 may also be constructed using a structure known in the related art. The isolation layer 130 is used to isolate the pad 150 and the build-up layer 120 to prevent solder from penetrating into the interior of the semiconductor package structure.

[0043] like Figure 2 As shown, in some embodiments, the semiconductor package structure further includes a chip component 300 located above the substrate 100. The chip component 300 can be connected by welding with the pad 150 above the substrate 100. It can be understood that the capacitor component 200 is below the chip component 300, for example, it can be directly below, such an arrangement enables the chip component 300 to be vertically connected to the capacitor component 200, and the ESL and ESR from the capacitor component 200 to the pad 150 of the upper chip component 300 will be much lower, and at the same time, the high-frequency AC noise will be reduced.

[0044] refer to Figures 3 to 16 In order to prepare the above-mentioned semiconductor package structure, according to the second aspect of the present disclosure, the present disclosure also provides a method for preparing a semiconductor package structure, the method comprising: providing a glass substrate body 110 .

[0045] A cavity 111 is formed on the glass substrate body 110 .

[0046] A capacitor 200 is installed in the cavity 111. The capacitor 200 includes a DTC capacitor and / or a 3D MIM capacitor.

[0047] The preparation method disclosed in the present invention forms a cavity 111 on a glass substrate body 110, and embeds the capacitor 200 into the cavity 111. Since the glass substrate body 110 has a high elastic modulus, it can adapt to the thickness of the capacitor 200, that is, the thickness can be less than or equal to 1000μm. Preferably, the thickness of the glass substrate body 110 is less than or equal to 770μm, wherein the thickness of the glass substrate body 110 can be adaptively adjusted according to the thickness of the capacitor. For example, the thickness of the capacitor 200 may be between 50-760μm, and the corresponding glass substrate body 110 can also be set to the corresponding thickness. When the glass substrate body 110 is used in a smaller size, it will not cause warping, meeting the needs of a large-size packaging structure.

[0048] It should be noted that the capacitor 200 may be a DTC capacitor and / or a 3D MIM capacitor. Since the thermal expansion coefficient of the DTC capacitor and / or the 3D MIM capacitor is close to that of the glass substrate body 110 , the stress of the capacitor 200 can be reduced and the reliability can be increased.

[0049] In order to achieve Vdd, Vss and signal connection between the printed circuit board and the chip component 300 located on the substrate 100 , the method further includes: forming a through hole 112 on the glass substrate body 110 .

[0050] A first metal layer 141 is formed within the through hole 112 .

[0051] like Fig. 9 , Fig.10 and Fig.11 As shown, for example, a through hole 112 can be formed on one side of the cavity 111, and the first metal layer 141 in the through hole 112 is used to connect with the Vdd pad 150 and the chip component 300; two through holes 112 arranged at intervals are formed on the other side, and one through hole 112 and the first metal layer 141 therein are used to connect with the Vss pad 150 and the chip component 300; the other through hole 112 and the first metal layer 141 therein are used to connect with the chip component 300 and the signal pad 150.

[0052] In order to form the first metal layer 141 and the embedded capacitor 200, in some embodiments, the first metal layer 141 is formed in the through hole 112, including: forming the first metal layer 141 on the surface of the glass substrate body 110, the sidewall of the cavity 111, and the sidewall of the through hole 112; wherein the first metal layer 141 includes but is not limited to copper, and can be achieved by copper plating on the glass substrate body 110 forming the cavity 111 and the through hole 112.

[0053] A carrier 400 layer is disposed at the bottom of the glass substrate body 110 , wherein the carrier 400 layer may be a tape, a blue tape or other carriers 400 , which are used to form a support at the bottom of the glass substrate body 110 to prepare for the subsequent installation of the capacitor 200 and the filling of the insulating layer 160 .

[0054] The capacitor 200 is installed in the cavity 111 , wherein the capacitor 200 may be a DTC capacitor and / or a 3D MIM capacitor.

[0055] The insulating layer 160 is filled in the through hole 112 and the cavity 111 . The insulating layer 160 in the cavity 111 is located between the capacitor 200 and the first metal layer 141 , while the insulating layer 160 in the through hole 112 is located inside the first metal layer 141 .

[0056] The first metal layer 141 on the surface of the carrier 400 layer and the glass substrate body 110 is removed. The first metal layer 141 on the surface of the glass substrate body 110 can be removed in any suitable manner, for example, by photolithography and etching, so as to protect the first metal layer 141 in the cavity 111 and the through hole 112.

[0057] In some embodiments, the method further includes: forming one or more build-up layers 120 on the surface of the glass substrate body 110 .

[0058] At least one second metal layer 142 connected to the capacitor 200 and / or the first metal layer 141 is formed on the build-up layer 120 .

[0059] First, a layer of build-up layer 120, such as an ABF layer, can be applied to the upper and lower surfaces of the glass substrate body 110, respectively, and a metal layer can be formed on the build-up layer 120 by laser drilling and copper plating to achieve connection with the first metal layer 141 of the through hole 112 and the capacitor 200. Then, the metal layer is photolithographically and etched to obtain a second metal layer 142. Finally, the steps of forming the build-up layer 120 and the second metal layer 142 are repeated to form multiple layers.

[0060] In some embodiments, the method further includes: forming an isolation layer 130 on the side of the outermost stacking layer 120 away from the glass substrate body 110; wherein the isolation layer 130 is mainly used to isolate the pads 150 formed in the subsequent steps from penetrating into the stacking layer 120, and it can be made of any suitable material known in the relevant technology.

[0061] A pad 150 connected to the second metal layer 142 is formed on the isolation layer 130 to form the substrate 100. Then, the isolation layer 130 is photolithographically etched to form a pad 150 window 131, and a pad 150 is formed at the corresponding pad 150 window 131 by pre-solder printing and reflow soldering.

[0062] In some embodiments, the method further includes: providing a chip component 300, and connecting the chip component 300 to the pad 150 above the substrate 100. The chip component 300 may be a SOC chip, and the chip component 300 is connected to the pad 150 above the substrate 100 to achieve chip assembly.

[0063] It should be noted that the pads 150 on the other side of the glass substrate body 110 away from the chip component 300 are used for connection with the PCB board, including but not limited to core power supply, grounding and signal connection.

[0064] refer to Figures 3 to 16 As shown, the present disclosure uses a specific embodiment to describe in detail the manufacturing process of a semiconductor packaging structure.

[0065] like Figure 3 As shown, a glass substrate body 110 is provided, and a cavity 111 and a through hole 112 are formed on the glass substrate body 110 .

[0066] like Figure 4 As shown, copper is plated on the upper surface and the lower surface of the glass substrate body 110 , and the sidewalls of the cavity 111 and the through hole 112 to form a first copper plating layer 140 a .

[0067] like Figure 5 As shown, the glass substrate body 110 is placed on a carrier 400 formed by a blue tape or other supporting members, and the DTC capacitor is embedded in the cavity 111 .

[0068] like Figure 6 As shown, an insulating layer 160 is formed in the through hole 112 and the cavity 111 .

[0069] like Figure 7 As shown, carrier 400, including the blue tape or support, is removed.

[0070] like Figure 8 As shown, the copper plated on the surface of the glass substrate body 110 is photolithographically and etched to form a copper circuit.

[0071] like Fig. 9 As shown, an ABF layer, namely, a build-up layer 120 , is formed on the upper surface and the lower surface of the glass substrate body 110 , respectively.

[0072] like Fig.10 As shown, an opening corresponding to the through hole 112 and the DTC capacitor is formed in the ABF layer by laser drilling, and a second copper plating layer 140b is formed in the ABF layer and the opening.

[0073] like Fig.11 As shown, the copper plated on the surface of the ABF layer is photolithographically and etched to form a copper circuit, including a second metal layer 142 .

[0074] like Fig.12 As shown, the ABF layer and the copper circuit are repeatedly formed, and the cycle is continued to multiple layers.

[0075] like Fig.13 As shown, a separation layer (SR Coating) 130 is formed on the surface of the outermost ABF layer.

[0076] like Fig.14 As shown, the window 131 of the pad 150 is formed by photolithography and etching the isolation layer (SR Coating) 130 .

[0077] like Fig.15 As shown, the pads 150 are formed at the corresponding pad 150 windows 131 by pre-solder printing and reflow soldering.

[0078] like Fig.16 As shown, the chip component 300 (SOC chip) is soldered to the pad 150 .

[0079] The semiconductor packaging structure and preparation method disclosed herein, by embedding the capacitor 200 in the cavity 111 of the glass substrate body 110, because the glass substrate body 110 has a high elastic modulus, when it uses a smaller thickness size, for example, less than or equal to 1000 microns, it can also be used for a larger packaging structure to avoid large warping. The capacitor 200 can be a DTC capacitor and / or a 3D MIM capacitor with a thermal expansion coefficient close to the glass substrate body 110, thereby reducing the stress of the capacitor 200 and increasing reliability. Since the capacitor 200 is embedded in the glass substrate body 110, the capacitor 200 has low ESL / ESR characteristics, which can reduce high-frequency power noise.

[0080] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings; however, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, a variety of simple modifications can be made to the technical solution of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.

[0081] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.

[0082] In addition, various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.

Claims

1. A semiconductor packaging structure, characterized in that: include: A substrate, comprising a glass substrate body having a cavity; and The capacitor is embedded in the cavity.

2. The semiconductor package structure according to claim 1, wherein: The thickness of the glass substrate body corresponds to the thickness of the capacitor.

3. The semiconductor package structure according to claim 1, wherein: The thickness of the glass substrate body is less than or equal to 770 μm.

4. The semiconductor package structure according to claim 1, wherein: The capacitor includes a DTC capacitor and / or a 3D MIM capacitor.

5. The semiconductor packaging structure according to any one of claims 1 to 4, characterized in that: The glass substrate body further includes a through hole, and the semiconductor package structure further includes a first metal layer located in the through hole.

6. The semiconductor package structure according to any one of claims 1 to 4, characterized in that: The substrate further includes at least one build-up layer disposed on each side of the glass substrate body.

7. The semiconductor package structure according to claim 6, characterized in that: The substrate further comprises an isolation layer formed on a side of the stacked layer away from the glass substrate body; The semiconductor package structure further includes a second metal layer formed between the build-up layers, and the isolation layer is formed with a pad connected to the second metal layer.

8. The semiconductor package structure according to claim 1, wherein: The semiconductor package structure further includes a chip component located above the substrate.

9. A method for preparing a semiconductor packaging structure, characterized in that: The method comprises: Providing a glass substrate body; forming a cavity on the glass substrate body; A capacitor is installed in the cavity.

10. The method for preparing a semiconductor packaging structure according to claim 9, characterized in that: The method further comprises: forming a through hole on the glass substrate body; A first metal layer is formed in the through hole.

11. The method for preparing a semiconductor packaging structure according to claim 10, characterized in that: The forming of a first metal layer in the through hole comprises: forming a first metal layer on the surface of the glass substrate body, the sidewall of the cavity, and the sidewall of the through hole; Disposing a carrier layer at the bottom of the glass substrate body; Installing a capacitor in the cavity; Filling an insulating layer in the through hole and the cavity; The carrier layer and the first metal layer on the surface of the glass substrate body are removed.

12. The method for preparing a semiconductor packaging structure according to claim 10, characterized in that: The method further comprises: forming one or more build-up layers on the surface of the glass substrate body; At least one second metal layer connected to the capacitor and / or the first metal layer is formed in the build-up layer.

13. The method for preparing a semiconductor packaging structure according to claim 12, characterized in that: The method further comprises: forming an isolation layer on the side of the outermost layer away from the glass substrate body; A pad connected to the second metal layer is formed on the isolation layer to form a substrate.

14. The method for preparing a semiconductor packaging structure according to claim 13, characterized in that: The method further comprises: Provide chip parts; The chip component is connected to the pad above the substrate.

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