Wide-input-output-range low-ripple average current mode buck-boost converter

Abstract

The invention relates to a wide-input-output-range low-ripple average current mode buck-boost converter. A main transformation circuit is connected with a voltage source to supply power to a load; the current sampling circuit selectively collects input end current or output end current of the transformation main circuit to form sampling current; the feedback loop module obtains a corresponding error voltage between the sampling current and a difference voltage based on the difference voltage between the voltage at the output end of the transformation main circuit and the reference voltage; the control logic module generates a driving signal and transmits the driving signal to a corresponding NMOS switch tube for control, so that the transformation main circuit is switched to work in a buck mode or a boost mode; the design scheme is simple to control, the voltage transformation main circuit is enabled to smoothly switch and work among different buck-boost modes through an average current mode in combination with two paths of slope compensation signals, output ripples are effectively reduced, a wider input and output voltage range is realized, the switching sequence of a switching tube is optimized, and the overall efficiency of the buck-boost converter is improved.

Description

Technical Field

[0001] The invention relates to a wide input-output range low-ripple average current mode buck-boost converter, belonging to the technical field of voltage transformation control. Background Art

[0002] Four-switch buck-boost switching converters have received more and more attention and applications. Traditional switching converters can only achieve buck or boost operations, while four-switch buck-boost switching converters can achieve seamless switching among voltage regulation modes such as boost, buck, and equal voltage. The wider voltage regulation range makes it one of the indispensable chips in the fields of industry, medical care, and automobiles. In actual applications, the switching converter is usually required to work stably under a wider input and output voltage range and achieve smooth mode switching when the load changes; at the same time, high-precision loads require a precise and stable output voltage, which puts higher requirements on the output ripple of the four-switch buck-boost converter. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a wide input-output range low ripple average current mode buck-boost converter, which works in different buck-boost modes and can achieve smooth switching between them to improve working efficiency.

[0004] In order to solve the above technical problems, the present invention adopts the following technical solutions: The present invention designs a wide input and output range low ripple average current mode buck-boost converter, including a transformer main circuit, a current sampling circuit, a feedback loop module, and a control logic module, wherein the transformer main circuit is connected to a voltage source V at its input terminal. in , and supplies power to the load at the output end through the built-in combination circuit structure of the first NMOS switch tube S1, the second NMOS switch tube S2, the third NMOS switch tube S3, and the fourth NMOS switch tube S4;

[0005] The current sampling circuit is used to receive and select one of the on / off control signals Q2 and Q3 of the second NMOS switch tube S2 and the third NMOS switch tube S3 in the transformer main circuit to collect the current I at the input end of the transformer main circuit. sns1 Or the output current I sns2 The sampling current I SENSE And output;

[0006] The feedback loop module includes a voltage feedback loop module and a current feedback loop module, wherein the voltage feedback loop module is used to connect the output voltage V0 of the transformer main circuit and the reference voltage V REF , and obtain the difference voltage V between the two C1 And output; the current feedback loop module is used to access the sampling current I SENSE The difference voltage VC1 , and obtain the error voltage V corresponding to the two C2 And output;

[0007] The control logic module includes a mode selection module, a switch tube drive circuit, and two main comparators. The negative input terminal of one main comparator and the positive input terminal of the other main comparator are respectively connected to the error voltage V C2 , and the positive input of one of the main comparators is connected to the external slope compensation signal V BUCK The negative input of the other main comparator is connected to the slope compensation signal V BOOST The two main comparators compare the slope compensation signal connected to them with the error voltage V C2 , obtain the comparison results Trip_buck and Trip_boost and output them; the mode selection module is used to externally connect the clock signal clk, and receive the comparison results Trip_buck and Trip_boost output by the two main comparators, process and generate on-off control signals Q1, Q2, Q3, and Q4 corresponding to the first NMOS switch tube S1, the second NMOS switch tube S2, the third NMOS switch tube S3, and the fourth NMOS switch tube S4 in the transformer main circuit, respectively, and the switch tube driving circuit receives the on-off control signals Q1, Q2, Q3, and Q4 output by the mode selection module respectively, converts them into corresponding drive signals HD1, LD1, HD2, and LD2 and transmits them to the corresponding NMOS switch tubes for on-off control, so as to realize the switching of the transformer main circuit to work in the buck mode or the boost mode.

[0008] As a preferred technical solution of the present invention: the transformer main circuit also includes an inductor L m With capacitor C C , where the voltage source V connected to the input end of the transformer main circuit in The positive electrode is connected to the drain of the first NMOS switch tube S1, and the source of the first NMOS switch tube S1 is connected to the drain of the second NMOS switch tube S2, the inductor L m One end of the inductor L m The other end is connected to the drain of the third NMOS switch tube S3 and the drain of the fourth NMOS switch tube S4 respectively. The source of the fourth NMOS switch tube S4 constitutes the positive electrode of the output end of the transformer main circuit and is connected to the positive electrode of the load. The voltage source V in The negative electrode of the output end of the transformer main circuit is connected to the negative electrode of the load, and the capacitor C C The two ends of the connector are connected to the two ends of the load respectively.

[0009] As a preferred technical solution of the present invention: the current sampling circuit includes a current selector, a sampling resistor RSNS1 , sampling resistor R SNS2 , and a first current amplifier and a second current amplifier, wherein the sampling resistor R SNS1 Connected in series to the positive terminal of the transformer main circuit input, the sampling resistor R SNS2 Connected in series to the positive terminal of the transformer main circuit output, through the sampling resistor R SNS1 , sampling resistor R SNS2 Collect the current I of the transformer main circuit input terminal sns1 , output current I sns2 , and the input current I sns1 is sent to the first current amplifier for amplification and updating, and the output current I sns2 The updated input current I sns1 , output current I sns2 The current selector is transmitted to the current selector, and the current selector is connected to the on-off control signals Q2 and Q3 of the second NMOS switch tube S2 and the third NMOS switch tube S3 in the strain main circuit respectively. The current selector selects the received input current I according to the on-off control signals Q2 and Q3. sns1 Or the output current I sns2 The sampling current I SENSE And output.

[0010] As a preferred technical solution of the present invention: when the current selector determines that the on-off control signal Q2 is equal to 1, the current selector selects the received output current I sns2 The sampling current I SENSE If the on / off control signal Q3 is equal to 1, the current selector selects the received input current I sns1 The sampling current I SENSE And output.

[0011] As a preferred technical solution of the present invention: the slope compensation signal V connected to the two main comparators in the control logic module BOOST , slope compensation signal V BUCK , and the clock signal clk connected to the mode selection module, are generated and output by a dual slope voltage generator, the dual slope voltage generator includes a ramp signal generating circuit and a loop control circuit, wherein the ramp signal generating circuit includes V BUCK Generating circuit with V BOOST Generate circuits;

[0012] V BUCK The generating circuit includes a first reference current source I1, a second reference current source I2, a third PMOS transistor M P3 , the third NMOS tube M N3, the first capacitor C1, the output end of the first reference current source I1 is connected to the third PMOS tube M P3 The source of the third PMOS tube M P3 The drain of the third NMOS tube M N3 The drain of the first capacitor C1 and one end of the first capacitor C1 are connected, and the connection position forms V BUCK The output terminal of the generating circuit is used to output the slope compensation signal V BUCK , and constitute the slope compensation signal V output by the dual slope voltage generator BUCK , the third NMOS tube M N3 The source electrode is connected in series with the second reference current source I2 and then connected to the other end of the first capacitor C1 and grounded;

[0013] V BOOST The generating circuit includes a third reference current source I3, a fourth reference current source I4, a fourth PMOS transistor M P4 , the fourth NMOS tube M N4 , the second capacitor C2, the output end of the third reference current source I3 is connected to the fourth PMOS tube M P4 The source of the fourth PMOS tube M P4 The drain of the fourth NMOS tube M N4 The drain of the second capacitor C2 and one end of the second capacitor C2 are connected, and the connection position forms V BOOST The output terminal of the generating circuit is used to output the slope compensation signal V BOOST , and constitute the slope compensation signal V output by the dual slope voltage generator BOOST , the fourth NMOS tube M N4 The source electrode is connected in series with a fourth reference current source I4 and then connected to the other end of the second capacitor C2 and grounded;

[0014] The loop control circuit is used to access V BUCK The generating circuit outputs the slope compensation signal V BUCK , and V BOOST The generating circuit outputs the slope compensation signal V BOOST , processing and outputting various feedback signals including the clock signal clk to V BUCK The third PMOS tube M in the generating circuit P3 The gate of the third NMOS tube M N3 The gate, V BOOST The fourth PMOS tube M in the generating circuit P4 The gate of the fourth NMOS tube M N4 gate, and at the same time constitute the clock signal clk output by the dual slope voltage generator.

[0015] As a preferred technical solution of the present invention: the loop control circuit includes a first comparator A1, a second comparator A2, a third comparator A3, a fourth comparator A4, a first AND gate AND1, a second AND gate AND2, and a first SR trigger SR1; wherein the positive input terminal of the first comparator A1 and the negative input terminal of the second comparator A2 are respectively used to connect to V BOOST The generating circuit outputs the slope compensation signal V BOOST At the same time, the negative input terminal of the first comparator A1 is used to connect to the preset voltage V1, the positive input terminal of the second comparator A2 is used to connect to the preset voltage V3, the positive input terminal of the third comparator A3 and the negative input terminal of the fourth comparator A4 are respectively used to connect to V BUCK The generating circuit outputs the slope compensation signal V BUCK , and the negative input terminal of the third comparator A3 is used to connect to the preset voltage V2, and the positive input terminal of the fourth comparator A4 is used to connect to the preset voltage V4; the output terminal of the first comparator A1 and the output terminal of the fourth comparator A4 are connected to the two input terminals of the first AND gate AND1, and the output terminal of the second comparator A2 and the output terminal of the third comparator A3 are connected to the two input terminals of the second AND gate AND2. At the same time, the reverse signal of the output signal of the output terminal of the second comparator A2 is fed back to V BOOST The fourth NMOS tube M in the generating circuit N4 The output signal of the third comparator A3 output terminal is fed back to V BUCK The third PMOS tube M in the generating circuit P3 The output end of the first AND gate AND1 is connected to the S end of the first SR trigger SR1, the output end of the second AND gate AND2 is connected to the R end of the first SR trigger SR1, and the Qbar end of the first SR trigger SR1 outputs the clock signal clk and feeds it back to V BUCK The third NMOS tube M in the generating circuit N3 The gate of the dual slope voltage generator also forms the clock signal clk output by the dual slope voltage generator. The Q-end output signal of the SR trigger is fed back to V BOOST The fourth PMOS tube M in the generating circuit P4 of the gate.

[0016] As a preferred technical solution of the present invention: the voltage feedback loop module obtains the difference voltage V C1 Perform signal amplification and update before output.

[0017] As a preferred technical solution of the present invention: the mode selection module includes a third AND gate AND3, a fourth AND gate AND4, a second SR trigger SR2, and a third SR trigger SR3, wherein one of the input ends of the third AND gate AND3 and one of the input ends of the fourth AND gate AND4 are respectively connected to the comparison results Trip_buck and Trip_boost, the output end of the third AND gate AND3 is connected to the R end of the second SR trigger SR2, the S end of the second SR trigger SR2 is externally connected to the clock signal clk, the output end of the fourth AND gate AND4 is connected to the S end of the third SR trigger SR3, and the R end of the third SR trigger SR3 is externally connected to the clock signal clk, the Qbar end of the second SR trigger SR2 is used to output the on-off control signal Q1 corresponding to the first NMOS switch tube S1, and the on-off control signal Q1 is fed back to the other input end of the fourth AND gate AND4, the Q end of the second SR trigger SR2 is used to output the on-off control signal Q2 corresponding to the second NMOS switch tube S2, the Qbar end of the third SR trigger SR3 is used to output the on-off control signal Q3 corresponding to the third NMOS switch tube S3, the Q end of the third SR trigger SR3 is used to output the on-off control signal Q4 corresponding to the fourth NMOS switch tube S4, and the on-off control signal Q4 is fed back to the other input end of the third AND gate AND3.

[0018] As a preferred technical solution of the present invention: the mode selection module in each switching cycle is based on the slope compensation signal V BOOST With the slope compensation signal V BUCK are synchronized with the clock signal, and the slope compensation signal V BOOST With the slope compensation signal V BUCK Before the switching cycle clocks intersect at the end, the comparison results output by the two main comparators are analyzed and controlled as follows;

[0019] If the error voltage V C2 First, the slope compensation signal V BUCK intersect, then generate an on-off control signal Q4 for controlling the fourth NMOS switch tube S4 to be turned on, an on-off control signal Q3 for controlling the third NMOS switch tube S3 to be turned off, and generate on-off control signals Q1 and Q2 for keeping the first NMOS switch tube S1 and the second NMOS switch tube S2 alternately turned on, so as to control the main transformer circuit to switch to the buck mode corresponding to the switching cycle;

[0020] If the error voltage V C2 First, the slope compensation signal V BOOSTWhen they intersect, an on-off control signal Q2 is generated to control the conduction of the first NMOS switch tube S1, an on-off control signal Q2 is generated to control the disconnection of the second NMOS switch tube S2, and on-off control signals Q3 and Q4 are generated to keep the third NMOS switch tube S3 and the fourth NMOS switch tube S4 alternately turned on, so as to control the switching of the transformer main circuit to operate in the boost mode corresponding to the switching cycle.

[0021] The wide input-output range low ripple average current mode buck-boost converter of the present invention adopts the above technical solution and has the following technical effects compared with the prior art:

[0022] (1) The present invention designs a wide input-output range low-ripple average current mode buck-boost converter, which is based on connecting the transformer main circuit to a voltage source to power the load; the current sampling circuit selects to collect the input current or the output current of the transformer main circuit to form a sampling current; the feedback loop module obtains the error voltage corresponding to the sampling current and the difference voltage based on the difference voltage between the output voltage of the transformer main circuit and the reference voltage; the control logic module generates a drive signal and transmits it to the corresponding NMOS switch tube for on-off control, so that the transformer main circuit can switch to work in the buck mode or the boost mode; the design scheme is simple to control, through the average current mode, combined with two slope compensation signals, the transformer main circuit can smoothly switch and work between different buck-boost modes, effectively reduce the output ripple, achieve a wider input and output voltage range, and optimize the switching sequence of the switch tube, thereby improving the overall efficiency of the buck-boost converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 The system block diagram of the wide input-output range low ripple average current mode buck-boost converter designed by the present invention.

[0024] Figure 2 It is a circuit diagram of a ramp signal generating circuit in a dual ramp voltage generator in the design of the present invention;

[0025] Figure 3 It is a circuit diagram of a loop control circuit in a dual slope voltage generator in the design of the present invention;

[0026] Figure 4 It is a circuit diagram of a mode selection module in a control logic module in the design of the present invention;

[0027] Figure 5 It is a timing waveform diagram of the design and application embodiment of the present invention. DETAILED DESCRIPTION

[0028] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0029] The present invention designs a wide input-output range low ripple average current mode buck-boost converter. In practical applications, Figure 1 As shown, the design includes a transformer main circuit, a current sampling circuit, a feedback loop module, and a control logic module; wherein the transformer main circuit includes a first NMOS switch tube S1, a second NMOS switch tube S2, a third NMOS switch tube S3, a fourth NMOS switch tube S4, an inductor L m , capacitor C C , where the voltage source V connected to the input end of the transformer main circuit in The positive electrode is connected to the drain of the first NMOS switch tube S1, and the source of the first NMOS switch tube S1 is connected to the drain of the second NMOS switch tube S2, the inductor L m One end of the inductor L m The other end is connected to the drain of the third NMOS switch tube S3 and the drain of the fourth NMOS switch tube S4 respectively. The source of the fourth NMOS switch tube S4 constitutes the positive electrode of the output end of the transformer main circuit and is connected to the positive electrode of the load. The voltage source V in The negative electrode of the output end of the transformer main circuit is connected to the negative electrode of the load, and the capacitor C C The two ends of the transformer are connected to the two ends of the load respectively. In the application, the transformer main circuit is connected to the voltage source V at its input end. in , and the load at the output end is powered through the built-in combined circuit structure of the first NMOS switch tube S1, the second NMOS switch tube S2, the third NMOS switch tube S3, and the fourth NMOS switch tube S4.

[0030] like Figure 1 As shown, the current sampling circuit is used to receive and select one of the on-off control signals Q2 and Q3 of the second NMOS switch tube S2 and the third NMOS switch tube S3 in the transformer main circuit to collect the current I at the input end of the transformer main circuit. sns1 Or the output current I sns2 The sampling current I SENSE And output; in specific design, such as Figure 1 As shown, the current sampling circuit includes a current selector, a sampling resistor R SNS1 , sampling resistor R SNS2 , and a first current amplifier and a second current amplifier, wherein the sampling resistor R SNS1 Connected in series to the positive terminal of the transformer main circuit input, the sampling resistor R SNS2 Connected in series to the positive terminal of the transformer main circuit output, through the sampling resistor R SNS1 , sampling resistor R SNS2 Collect the current I of the transformer main circuit input terminal sns1, output current I sns2 , and the input current I sns1 is sent to the first current amplifier for amplification and updating, and the output current I sns2 The updated input current I sns1 , output current I sns2 The current selector is transmitted to the current selector, and the current selector is connected to the on-off control signals Q2 and Q3 of the second NMOS switch tube S2 and the third NMOS switch tube S3 in the strain main circuit respectively. The current selector selects the received input current I according to the on-off control signals Q2 and Q3. sns1 Or the output current I sns2 The sampling current I SENSE And output.

[0031] In the actual application of the current sampling circuit, the current selector determines that if the on-off control signal Q2 is equal to 1, the current selector selects the received output current I sns2 The sampling current I SENSE If the on / off control signal Q3 is equal to 1, the current selector selects the received input current I sns1 The sampling current I SENSE And output.

[0032] The feedback loop module includes a voltage feedback loop module and a current feedback loop module, such as Figure 1 As shown, the voltage feedback loop module is used to connect the output voltage V0 of the transformer main circuit and the reference voltage V REF , and obtain the difference voltage V between the two C1 The signal is amplified and updated before output; the current feedback loop module is used to access the sampling current I SENSE and the difference voltage V C1 , and obtain the error voltage V corresponding to the two C2 And output.

[0033] like Figure 1 As shown, the control logic module includes a mode selection module, a switch tube driving circuit, and two main comparators, wherein the negative input terminal of one main comparator and the positive input terminal of the other main comparator are respectively connected to the error voltage V C2 , and the positive input of one of the main comparators is connected to the external slope compensation signal V BUCK The negative input of the other main comparator is connected to the slope compensation signal V BOOST The two main comparators compare the slope compensation signal connected to them with the error voltage V C2, obtain the comparison results Trip_buck and Trip_boost and output them; the mode selection module is used for externally connecting the clock signal clk, and receiving the comparison results Trip_buck and Trip_boost output by the two main comparators, processing and generating the on-off control signals Q1, Q2, Q3, and Q4 corresponding to the first NMOS switch tube S1, the second NMOS switch tube S2, the third NMOS switch tube S3, and the fourth NMOS switch tube S4 in the transformer main circuit respectively, and the switch tube driving circuit receives the on-off control signals Q1, Q2, Q3, and Q4 output by the mode selection module respectively, converts them into corresponding driving signals HD1, LD1, HD2, and LD2 and transmits them to the corresponding NMOS switch tubes for on-off control, so as to realize the switching of the transformer main circuit to work in the buck mode or the boost mode, and sets the dead time to ensure that the power tube can work efficiently and orderly.

[0034] In actual application, the slope compensation signal V connected to the two main comparators in the control logic module BOOST , slope compensation signal V BUCK , and the clock signal clk connected to the mode selection module, are generated and output by a dual slope voltage generator, the dual slope voltage generator includes a ramp signal generating circuit and a loop control circuit, wherein the ramp signal generating circuit includes V BUCK Generating circuit with V BOOST Generate the circuit.

[0035] like Figure 2 As shown, V BUCK The generating circuit includes a first reference current source I1, a second reference current source I2, a third PMOS transistor M P3 , the third NMOS tube M N3 , the first capacitor C1, the output end of the first reference current source I1 is connected to the third PMOS tube M P3 The source of the third PMOS tube M P3 The drain of the third NMOS tube M N3 The drain of the first capacitor C1 and one end of the first capacitor C1 are connected, and the connection position forms V BUCK The output terminal of the generating circuit is used to output the slope compensation signal V BUCK , and constitute the slope compensation signal V output by the dual slope voltage generator BUCK , the third NMOS tube M N3 The source of the capacitor is connected in series with the second reference current source I2 and then connected to the other end of the first capacitor C1 and grounded.

[0036] like Figure 2 As shown, V BOOST The generating circuit includes a third reference current source I3, a fourth reference current source I4, a fourth PMOS transistor M P4, the fourth NMOS tube M N4 , the second capacitor C2, the output end of the third reference current source I3 is connected to the fourth PMOS tube M P4 The source of the fourth PMOS tube M P4 The drain of the fourth NMOS tube M N4 The drain of the second capacitor C2 and one end of the second capacitor C2 are connected, and the connection position forms V BOOST The output terminal of the generating circuit is used to output the slope compensation signal V BOOST , and constitute the slope compensation signal V output by the dual slope voltage generator BOOST , the fourth NMOS tube M N4 The source of the capacitor is connected in series with the fourth reference current source I4, and then connected to the other end of the second capacitor C2 and grounded.

[0037] like Figure 3 As shown, the loop control circuit is used to access V BUCK The generating circuit outputs the slope compensation signal V BUCK , and V BOOST The generating circuit outputs the slope compensation signal V BOOST , processing and outputting various feedback signals including the clock signal clk to V BUCK The third PMOS tube M in the generating circuit P3 The gate of the third NMOS tube M N3 The gate, V BOOST The fourth PMOS tube M in the generating circuit P4 The gate of the fourth NMOS tube M N4 The gate of the dual slope voltage generator also forms the clock signal clk output by the dual slope voltage generator. In practical applications, Figure 3 As shown, the loop control circuit includes a first comparator A1, a second comparator A2, a third comparator A3, a fourth comparator A4, a first AND gate AND1, a second AND gate AND2, and a first SR trigger SR1; wherein the positive input terminal of the first comparator A1 and the negative input terminal of the second comparator A2 are respectively used to connect to V BOOST The generating circuit outputs the slope compensation signal V BOOST At the same time, the negative input terminal of the first comparator A1 is used to connect to the preset voltage V1, the positive input terminal of the second comparator A2 is used to connect to the preset voltage V3, the positive input terminal of the third comparator A3 and the negative input terminal of the fourth comparator A4 are respectively used to connect to V BUCK The generating circuit outputs the slope compensation signal V BUCK, and the negative input terminal of the third comparator A3 is used to connect to the preset voltage V2, and the positive input terminal of the fourth comparator A4 is used to connect to the preset voltage V4; the output terminal of the first comparator A1 and the output terminal of the fourth comparator A4 are connected to the two input terminals of the first AND gate AND1, and the output terminal of the second comparator A2 and the output terminal of the third comparator A3 are connected to the two input terminals of the second AND gate AND2. At the same time, the reverse signal of the output signal of the output terminal of the second comparator A2 is fed back to V BOOST The fourth NMOS tube M in the generating circuit N4 The output signal of the third comparator A3 output terminal is fed back to V BUCK The third PMOS tube M in the generating circuit P3 The output end of the first AND gate AND1 is connected to the S end of the first SR trigger SR1, the output end of the second AND gate AND2 is connected to the R end of the first SR trigger SR1, and the Qbar end of the first SR trigger SR1 outputs the clock signal clk and feeds it back to V BUCK The third NMOS tube M in the generating circuit N3 The gate of the dual slope voltage generator also forms the clock signal clk output by the dual slope voltage generator. The Q-end output signal of the SR trigger is fed back to V BOOST The fourth PMOS tube M in the generating circuit P4 of the gate.

[0038] And regarding the above-mentioned mode selection module, in actual application, such as Figure 4 As shown, the specific design includes a third AND gate AND3, a fourth AND gate AND4, a second SR trigger SR2, and a third SR trigger SR3, wherein one of the input ends of the third AND gate AND3 and one of the input ends of the fourth AND gate AND4 are respectively connected to the comparison results Trip_buck and Trip_boost, the output end of the third AND gate AND3 is connected to the R end of the second SR trigger SR2, the S end of the second SR trigger SR2 is externally connected to the clock signal clk, the output end of the fourth AND gate AND4 is connected to the S end of the third SR trigger SR3, the R end of the third SR trigger SR3 is externally connected to the clock signal clk, and the second SR The Qbar end of the trigger SR2 is used to output the on-off control signal Q1 corresponding to the first NMOS switch tube S1, and the on-off control signal Q1 is fed back to the other input end of the fourth AND gate AND4. The Q end of the second SR trigger SR2 is used to output the on-off control signal Q2 corresponding to the second NMOS switch tube S2. The Qbar end of the third SR trigger SR3 is used to output the on-off control signal Q3 corresponding to the third NMOS switch tube S3. The Q end of the third SR trigger SR3 is used to output the on-off control signal Q4 corresponding to the fourth NMOS switch tube S4, and the on-off control signal Q4 is fed back to the other input end of the third AND gate AND3.

[0039] In actual implementation, the mode selection module selects the slope compensation signal V in each switching cycle. BOOST With the slope compensation signal V BUCK are synchronized with the clock signal, and the slope compensation signal V BOOST With the slope compensation signal V BUCK Intersect before the end of the switching cycle clock, such as Figure 5 As shown, the comparison results output by the two main comparators are analyzed and controlled as follows;

[0040] If the error voltage V C2 First, the slope compensation signal V BUCK intersect, then generate an on-off control signal Q4 for controlling the fourth NMOS switch tube S4 to be turned on, an on-off control signal Q3 for controlling the third NMOS switch tube S3 to be turned off, and generate on-off control signals Q1 and Q2 for keeping the first NMOS switch tube S1 and the second NMOS switch tube S2 alternately turned on, so as to control the main transformer circuit to switch to the buck mode corresponding to the switching cycle;

[0041] If the error voltage V C2 First, the slope compensation signal V BOOST When they intersect, an on-off control signal Q2 is generated to control the conduction of the first NMOS switch tube S1, an on-off control signal Q2 is generated to control the disconnection of the second NMOS switch tube S2, and on-off control signals Q3 and Q4 are generated to keep the third NMOS switch tube S3 and the fourth NMOS switch tube S4 alternately turned on, so as to control the switching of the transformer main circuit to operate in the boost mode corresponding to the switching cycle.

[0042] The present invention designs a wide input-output range low ripple average current mode buck-boost converter, which is simple to control. Through the average current mode and combined with two slope compensation signals, the transformer main circuit can smoothly switch and operate between different buck-boost modes, effectively reducing output ripple, achieving a wider input and output voltage range, and optimizing the switching sequence of the switch tube, thereby improving the overall efficiency of the buck-boost converter.

[0043] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A wide input-output range low ripple average current mode buck-boost converter, characterized in that: It includes a transformer main circuit, a current sampling circuit, a feedback loop module, and a control logic module. The transformer main circuit is connected to a voltage source V at its input terminal. in , and supplies power to the load at the output end through the built-in combination circuit structure of the first NMOS switch tube S1, the second NMOS switch tube S2, the third NMOS switch tube S3, and the fourth NMOS switch tube S4; The current sampling circuit is used to receive and select one of the on / off control signals Q2 and Q3 of the second NMOS switch tube S2 and the third NMOS switch tube S3 in the transformer main circuit to collect the current I at the input end of the transformer main circuit. sns1 Or the output current I sns2 The sampling current I SENSE And output; The feedback loop module includes a voltage feedback loop module and a current feedback loop module, wherein the voltage feedback loop module is used to connect the output voltage V0 of the transformer main circuit and the reference voltage V REF , and obtain the difference voltage V between the two C1 And output; the current feedback loop module is used to access the sampling current I SENSE and the difference voltage V C1 , and obtain the error voltage V corresponding to the two C2 And output; The control logic module includes a mode selection module, a switch tube drive circuit, and two main comparators. The negative input terminal of one main comparator and the positive input terminal of the other main comparator are respectively connected to the error voltage V C2 , and the positive input of one of the main comparators is connected to the external slope compensation signal V BUCK The negative input of the other main comparator is connected to the slope compensation signal V BOOST The two main comparators compare the slope compensation signal connected to them with the error voltage V C2 , obtain the comparison results Trip_buck and Trip_boost and output them; the mode selection module is used to externally connect the clock signal clk, and receive the comparison results Trip_buck and Trip_boost output by the two main comparators, process and generate on-off control signals Q1, Q2, Q3, and Q4 corresponding to the first NMOS switch tube S1, the second NMOS switch tube S2, the third NMOS switch tube S3, and the fourth NMOS switch tube S4 in the transformer main circuit, respectively, and the switch tube driving circuit receives the on-off control signals Q1, Q2, Q3, and Q4 output by the mode selection module respectively, converts them into corresponding drive signals HD1, LD1, HD2, and LD2 and transmits them to the corresponding NMOS switch tubes for on-off control, so as to realize the switching of the transformer main circuit to work in the buck mode or the boost mode.

2. A wide input-output range low ripple average current mode buck-boost converter according to claim 1, characterized in that: The transformer main circuit also includes an inductor L m With capacitor C C , where the voltage source V connected to the input end of the transformer main circuit in The positive electrode is connected to the drain of the first NMOS switch tube S1, and the source of the first NMOS switch tube S1 is connected to the drain of the second NMOS switch tube S2, the inductor L m One end of the inductor L m The other end is connected to the drain of the third NMOS switch tube S3 and the drain of the fourth NMOS switch tube S4 respectively. The source of the fourth NMOS switch tube S4 constitutes the positive electrode of the output end of the transformer main circuit and is connected to the positive electrode of the load. The voltage source V in The negative electrode of the output end of the transformer main circuit is connected to the negative electrode of the load, and the capacitor C C The two ends of the are connected to the two ends of the load respectively.

3. The wide input-output range low ripple average current mode buck-boost converter according to claim 1, characterized in that: The current sampling circuit includes a current selector, a sampling resistor R SNS1 , sampling resistor R SNS2 , and a first current amplifier and a second current amplifier, wherein the sampling resistor R SNS1 Connected in series to the positive terminal of the transformer main circuit input, the sampling resistor R SNS2 Connected in series to the positive terminal of the transformer main circuit output, through the sampling resistor R SNS1 , sampling resistor R SNS2 Collect the current I of the transformer main circuit input terminal sns1 , output current I sns2 , and the input current I sns1 is sent to the first current amplifier for amplification and updating, and the output current I sns2 The updated input current I sns1 , output current I sns2 The current selector is transmitted to the current selector, and the current selector is connected to the on-off control signals Q2 and Q3 of the second NMOS switch tube S2 and the third NMOS switch tube S3 in the strain main circuit respectively. The current selector selects the received input current I according to the on-off control signals Q2 and Q3. sns1 Or the output current I sns2 The sampling current I SENSE And output.

4. A wide input-output range low ripple average current mode buck-boost converter according to claim 1 or 3, characterized in that: If the on / off control signal Q2 is equal to 1, the current selector selects the received output current I sns2 The sampling current I SENSE And output; If the on / off control signal Q3 is equal to 1, the current selector selects the received input current I sns1 The sampling current I SENSE And output.

5. The wide input-output range low ripple average current mode buck-boost converter according to claim 1, characterized in that: The slope compensation signal V connected to the two main comparators in the control logic module BOOST , slope compensation signal V BUCK , and the clock signal clk connected to the mode selection module, are generated and output by a dual slope voltage generator, the dual slope voltage generator includes a ramp signal generating circuit and a loop control circuit, wherein the ramp signal generating circuit includes V BUCK Generating circuit with V BOOST Generate circuits; V BUCK The generating circuit includes a first reference current source I1, a second reference current source I2, a third PMOS transistor M P3 , the third NMOS tube M N3 , the first capacitor C1, the output end of the first reference current source I1 is connected to the third PMOS tube M P3 The source of the third PMOS tube M P3 The drain of the third NMOS tube M N3 The drain of the first capacitor C1 and one end of the first capacitor C1 are connected, and the connection position forms V BUCK The output terminal of the generating circuit is used to output the slope compensation signal V BUCK , and constitute the slope compensation signal V output by the dual slope voltage generator BUCK , the third NMOS tube M N3 The source electrode is connected in series with the second reference current source I2 and then connected to the other end of the first capacitor C1 and grounded; V BOOST The generating circuit includes a third reference current source I3, a fourth reference current source I4, a fourth PMOS transistor M P4 , the fourth NMOS tube M N4 , the second capacitor C2, the output end of the third reference current source I3 is connected to the fourth PMOS tube M P4 The source of the fourth PMOS tube M P4 The drain of the fourth NMOS tube M N4 The drain of the second capacitor C2 and one end of the second capacitor C2 are connected, and the connection position forms V BOOST The output terminal of the generating circuit is used to output the slope compensation signal V BOOST , and constitute the slope compensation signal V output by the dual slope voltage generator BOOST , the fourth NMOS tube M N4 The source electrode is connected in series with a fourth reference current source I4 and then connected to the other end of the second capacitor C2 and grounded; The loop control circuit is used to access V BUCK The generating circuit outputs the slope compensation signal V BUCK , and V BOOST The generating circuit outputs the slope compensation signal V BOOST , processing and outputting various feedback signals including the clock signal clk to V BUCK The third PMOS tube M in the generating circuit P3 The gate of the third NMOS tube M N3 The gate, V BOOST The fourth PMOS tube M in the generating circuit P4 The gate of the fourth NMOS tube M N4 gate, and at the same time constitute the clock signal clk output by the dual slope voltage generator.

6. A wide input-output range low ripple average current mode buck-boost converter according to claim 5, characterized in that: The loop control circuit includes a first comparator A1, a second comparator A2, a third comparator A3, a fourth comparator A4, a first AND gate AND1, a second AND gate AND2, and a first SR trigger SR1; wherein the positive input terminal of the first comparator A1 and the negative input terminal of the second comparator A2 are respectively used to connect to V BOOST The generating circuit outputs the slope compensation signal V BOOST At the same time, the negative input terminal of the first comparator A1 is used to connect to the preset voltage V1, the positive input terminal of the second comparator A2 is used to connect to the preset voltage V3, the positive input terminal of the third comparator A3 and the negative input terminal of the fourth comparator A4 are respectively used to connect to V BUCK The generating circuit outputs the slope compensation signal V BUCK , and the negative input terminal of the third comparator A3 is used to connect to the preset voltage V2, and the positive input terminal of the fourth comparator A4 is used to connect to the preset voltage V4; the output terminal of the first comparator A1 and the output terminal of the fourth comparator A4 are connected to the two input terminals of the first AND gate AND1, and the output terminal of the second comparator A2 and the output terminal of the third comparator A3 are connected to the two input terminals of the second AND gate AND2. At the same time, the reverse signal of the output signal of the output terminal of the second comparator A2 is fed back to V BOOST The fourth NMOS tube M in the generating circuit N4 The output signal of the third comparator A3 output terminal is fed back to V BUCK The third PMOS tube M in the generating circuit P3 The output end of the first AND gate AND1 is connected to the S end of the first SR trigger SR1, the output end of the second AND gate AND2 is connected to the R end of the first SR trigger SR1, and the Qbar end of the first SR trigger SR1 outputs the clock signal clk and feeds it back to V BUCK The third NMOS tube M in the generating circuit N3 The gate of the dual slope voltage generator also forms the clock signal clk output by the dual slope voltage generator. The Q-end output signal of the SR trigger is fed back to V BOOST The fourth PMOS tube M in the generating circuit P4 of the gate.

7. The wide input-output range low ripple average current mode buck-boost converter according to claim 1, characterized in that: The voltage feedback loop module obtains the difference voltage V C1 Perform signal amplification and update before output.

8. The wide input-output range low ripple average current mode buck-boost converter according to claim 1, characterized in that: The mode selection module includes a third AND gate AND3, a fourth AND gate AND4, a second SR trigger SR2, and a third SR trigger SR3, wherein one of the input ends of the third AND gate AND3 and one of the input ends of the fourth AND gate AND4 are respectively connected to the comparison results Trip_buck and Trip_boost, the output end of the third AND gate AND3 is connected to the R end of the second SR trigger SR2, the S end of the second SR trigger SR2 is externally connected to the clock signal clk, the output end of the fourth AND gate AND4 is connected to the S end of the third SR trigger SR3, the R end of the third SR trigger SR3 is externally connected to the clock signal clk, and the second S The Qbar end of the R trigger SR2 is used to output the on-off control signal Q1 corresponding to the first NMOS switch tube S1, and the on-off control signal Q1 is fed back to the other input end of the fourth AND gate AND4. The Q end of the second SR trigger SR2 is used to output the on-off control signal Q2 corresponding to the second NMOS switch tube S2. The Qbar end of the third SR trigger SR3 is used to output the on-off control signal Q3 corresponding to the third NMOS switch tube S3. The Q end of the third SR trigger SR3 is used to output the on-off control signal Q4 corresponding to the fourth NMOS switch tube S4, and the on-off control signal Q4 is fed back to the other input end of the third AND gate AND3.

9. The wide input-output range low ripple average current mode buck-boost converter according to claim 1, characterized in that: The mode selection module selects the slope compensation signal V in each switching cycle. BOOST With the slope compensation signal V BUCK are synchronized with the clock signal, and the slope compensation signal V BOOST With the slope compensation signal V BUCK Before the switching cycle clocks intersect at the end, the comparison results output by the two main comparators are analyzed and controlled as follows; If the error voltage V C2 First, the slope compensation signal V BUCK intersect, then generate an on-off control signal Q4 for controlling the fourth NMOS switch tube S4 to be turned on, an on-off control signal Q3 for controlling the third NMOS switch tube S3 to be turned off, and generate on-off control signals Q1 and Q2 for keeping the first NMOS switch tube S1 and the second NMOS switch tube S2 alternately turned on, so as to control the main transformer circuit to switch to the buck mode corresponding to the switching cycle; If the error voltage V C2 First, the slope compensation signal V BOOST When they intersect, an on-off control signal Q2 is generated to control the conduction of the first NMOS switch tube S1, an on-off control signal Q2 is generated to control the disconnection of the second NMOS switch tube S2, and on-off control signals Q3 and Q4 are generated to keep the third NMOS switch tube S3 and the fourth NMOS switch tube S4 alternately turned on, so as to control the switching of the transformer main circuit to operate in the boost mode corresponding to the switching cycle.

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