Common-ground five-level photovoltaic inverter with capacitor voltage self-balancing function

Abstract

The invention discloses a common ground type five-level photovoltaic inverter with a capacitor voltage self-balancing function. The inverter topology comprises a photovoltaic cell, a five-level inverter circuit with a capacitor voltage self-balancing function, a single-phase output LC filter circuit and a single-phase load. Wherein the five-level inverter circuit is composed of a direct-current input filter capacitor Cdc, switched capacitors C1 and C2 and ten switching tubes S1 to S10, S1 is an IGBT (Insulated Gate Bipolar Translator) without a fly-wheel diode, and S2 to S10 are IGBTs with fly-wheel diodes. According to the control method of the inverter, a sine wave reference signal is compared with two paths of in-phase triangular carrier waves and two paths of phase-shifting triangular carrier waves to generate four paths of preprocessing signals, and then logic operation is carried out according to the switching tube conduction relation in six working modes to obtain a control signal. According to the inverter, self-balancing of the switched capacitor voltage can be achieved through mode switching, and the quality of the output voltage is remarkably improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic DC-AC conversion, and is applicable to application scenarios where the load is an AC load and the power supply is a DC power supply, and has good application value in photovoltaic off-grid or grid-connected inverters, and specifically relates to a common ground type five-level photovoltaic inverter with a capacitor voltage self-balancing function. Background Art

[0002] With the increasing consumption of fossil energy and the continuous deterioration of the ecological environment, the development and utilization of new energy has become an urgent need. Solar energy, as a clean, harmless and resource-rich renewable energy, has received widespread attention. Among them, photovoltaic power generation, as a major form of utilizing solar energy, has been studied in detail. The 2023 China Renewable Energy Development Report shows that China's renewable energy development will reach 2.95 trillion kWh in 2023, of which solar power generation will be 583.3 billion kWh, a year-on-year increase of 36.4%. According to the International Energy Agency (IEA), by 2028, renewable energy will account for more than 42% of global power generation, of which solar and wind power generation will account for 25%. However, with the rapid development of photovoltaic power generation, traditional photovoltaic inverters face many problems such as large system size, high cost and low efficiency due to the inclusion of isolation transformers. Therefore, non-isolated photovoltaic inverters have gradually become an effective solution with the advantages of small size, low cost and high conversion efficiency, and have been widely used in solar power generation systems.

[0003] Non-isolated photovoltaic inverters significantly improve system efficiency by directly connecting the photovoltaic input side to the grid or load by removing the isolation transformer. However, due to the lack of electrical isolation provided by traditional isolation devices, this structure also brings new technical challenges. In particular, the power switch tube in the photovoltaic inverter will generate a common-mode voltage when operating at high frequency. This voltage will act on the parasitic capacitance between the photovoltaic panel and the ground, the output side filter and the loop formed by the grid impedance, thereby causing common-mode leakage current (commonly referred to as leakage current). The generation of leakage current may cause electromagnetic interference and radiation, and cause harmonic distortion of the grid-connected current, reduce conversion efficiency, and even pose a threat to equipment and personnel safety. In order to suppress the leakage current in non-isolated photovoltaic inverters, the inverter topology and switch tube control strategy are often optimized to reduce the pulsation range of the common-mode voltage or keep it constant. However, due to the influence of parasitic parameters and dead time, it is still challenging to completely eliminate common-mode voltage fluctuations and leakage current.

[0004] To address this problem, the existing technology has proposed a common-ground photovoltaic inverter, which effectively eliminates leakage current by directly connecting the negative end of the photovoltaic panel to the neutral line of the power grid. However, the existing capacitor-type common-ground photovoltaic inverter has shortcomings, such as the lack of voltage doubling function. The continuous discharge of the switching capacitor will cause the voltage ripple to increase, causing output voltage distortion, affecting system efficiency and performance.

[0005] In view of this, it is necessary to design a new common-ground five-level photovoltaic inverter with capacitor voltage self-balancing function to solve the above problems. Summary of the invention

[0006] The main purpose of the present invention is to propose a common-ground type five-level photovoltaic inverter with capacitor voltage self-balancing function, so as to effectively solve the problem of continuous discharge of switching capacitors in the common-ground type inverter, reduce the capacitance of the required capacitor, and significantly improve the quality of the output voltage waveform.

[0007] The present invention provides a common ground type five-level photovoltaic inverter with capacitor voltage self-balancing function, including a photovoltaic cell PV, a five-level inverter circuit with capacitor voltage self-balancing function, a single-phase output LC filter circuit and a single-phase load. The five-level inverter circuit includes a DC input filter capacitor Cdc, two switch capacitors C1 and C2, and ten switch tubes S1 to S10, wherein the switch tube S1 is an IGBT without a freewheeling diode, and the switch tubes S2 to S9 are all IGBTs with freewheeling diodes. The single-phase output LC filter circuit and the single-phase load include a filter inductor Lf, a filter capacitor Cf and a single-phase load Ro.

[0008] A further improvement of the present invention is that the positive electrode of the photovoltaic cell PV is connected to the positive electrode of the DC input filter capacitor Cdc and the collector of the switch tube S1; the emitter of the switch tube S1 is connected to the collector of the switch tube S2, the collector of the switch tube S3, the collector of the switch tube S4 and the switch capacitor C 1 The positive electrode of switch S2 is connected to the collector of switch tube S9 and one end of filter inductor Lf; the emitter of switch tube S4 is connected to the collector of switch tube S5 and the positive electrode of switch capacitor C2; the negative electrode of switch capacitor C1 is connected to the emitter of switch tube S5, the collector of switch tube S6 and the collector of switch tube S8; the emitter of switch tube S6 is connected to the emitter of switch tube S7; the negative electrode of switch capacitor C2 is connected to the emitter of switch tube S8, the emitter of switch tube S9 and the emitter of switch tube S10; the other end of filter inductor Lf is connected to the positive electrode of filter capacitor Cf and one end of load Ro; the negative electrode of photovoltaic cell PV is connected to the negative electrode of DC input filter capacitor Cdc, the emitter of switch tube S3, the emitter of switch tube S7, the collector of switch tube S10, the negative electrode of filter capacitor Cf and the other end of load Ro.

[0009] A further improvement of the present invention lies in that the switching transistors S6 and S7 in the common-ground five-level photovoltaic inverter circuit with the function of self-balancing capacitor voltage are connected in reverse series, so as to realize the bidirectional flow of current in this branch.

[0010] A further improvement of the present invention lies in that six working modes [M1, M2, M3, M4, M5, M6] of the inverter are defined; wherein the working mode M1 means that the SPWM voltage output by the inverter is 2U PV ; the working mode M2 means that the SPWM voltage output by the inverter is U PV ; the working mode M3 means that the SPWM voltage output by the inverter is 0; the working mode M4 means that the SPWM voltage output by the inverter is -U PV , at this time, the switching capacitor C1 is in the charging state, and the switching capacitor C2 provides energy to the load; the working mode M5 means that the SPWM voltage output by the inverter is -U PV , at this time, the switching capacitor C1 charges the capacitor C2, and then the two are connected in parallel to supply power to the load together; the working mode M6 means that the SPWM voltage output by the inverter is -2U PV .

[0011] The present invention also provides a control method for a common-ground five-level photovoltaic inverter with the function of self-balancing capacitor voltage, which is used to control the above-mentioned common-ground five-level photovoltaic inverter circuit, and specifically includes the following steps:

[0012] The first step: The sine wave reference signal uref is respectively intercepted and compared with the two in-phase stacked triangular carriers uc1 and uc2 on the positive half-axis and the two phase-shifted triangular carriers uc3 and uc4 on the negative half-axis. When uref>uc1, a high level is output. When uref<uc1, a low level is output to generate a preprocessing signal A, and its inverse is taken to obtain a preprocessing signal a; similarly, when uref>uc2, a high level is output, and when uref<uc2, a low level is output to generate a preprocessing signal B, and its inverse is taken to obtain a preprocessing signal b; when uref>uc3, a high level is output, and when uref<uc3, a low level is output to generate a preprocessing signal C, and its inverse is taken to obtain a preprocessing signal c; when uref>uc4, a high level is output, and when uref<uc4, a low level is output to generate a preprocessing signal D, and its inverse is taken to obtain a preprocessing signal d;

[0013] Step 2: According to the preprocessing signal generated in the first step, combined with the signal status under different working modes, determine the logic control signal of each switch tube. Specifically, perform an AND operation on the inverted signal a of preprocessing signal A and preprocessing signal B, perform an AND operation on the inverted signal b of preprocessing signal B and preprocessing signal C and preprocessing signal D, perform an AND operation on preprocessing signal C and inverted signal d of preprocessing signal D, and then perform an OR operation on the AND operation results of the three to obtain the drive signal ug1 of switch tube S1; perform an AND operation on the inverted signal a of preprocessing signal A and preprocessing signal B, and then perform an OR operation on the AND operation result and preprocessing signal A to obtain the drive signal ug2 of switch tube S2; perform an AND operation on the inverted signal c of preprocessing signal C and preprocessing signal D, and perform an AND operation on the inverted signal c of preprocessing signal C and preprocessing signal D. An AND operation is performed on the inverted signal d of signal D, and then an OR operation is performed on the AND operation results of the two to obtain the drive signal ug3 of the switch tube S3; an AND operation is performed on the inverted signal a of the preprocessed signal A and the preprocessed signal B, an AND operation is performed on the inverted signal b of the preprocessed signal B and the preprocessed signal C and the preprocessed signal D, an AND operation is performed on the inverted signal c of the preprocessed signal C and the preprocessed signal D, and then an OR operation is performed on the AND operation results of the three to obtain the drive signals ug4 and ug6 of the switch tubes S4 and S6; an AND operation is performed on the preprocessed signal C and the inverted signal d of the preprocessed signal D, and an AND operation is performed on the inverted signal c of the preprocessed signal C and the inverted signal d of the preprocessed signal D , and then perform an OR operation on the AND operation results of the two and the preprocessing signal A to obtain the drive signal ug5 of the switch S5; perform an AND operation on the preprocessing signal C and the negated signal of the preprocessing signal D to obtain the drive signals ug6 and ug7 of the switch tubes S6 and S7; perform an AND operation on the negated signal a of the preprocessing signal A and the preprocessing signal B, perform an AND operation on the negated signal b of the preprocessing signal B and the preprocessing signal C and the preprocessing signal D, and perform an AND operation on the negated signal c of the preprocessing signal C and the preprocessing signal D, and then perform an OR operation on the AND operation results of the three to obtain the drive signal ug8 of the switch tube S8; perform an AND operation on the negated signal b of the preprocessing signal B and the preprocessing signal C And the preprocessing signal D are ANDed, the preprocessing signal C and the inverted signal d of the preprocessing signal D are ANDed, the inverted signal c of the preprocessing signal C and the preprocessing signal D are ANDed, the inverted signal c of the preprocessing signal C and the inverted signal d of the preprocessing signal D are ANDed, and then the AND operation results of the four are performed OR operation to obtain the driving signal ug9 of the switch tube S9; the inverted signal a of the preprocessing signal A and the preprocessing signal B are performed AND operation, the inverted signal b of the preprocessing signal B and the preprocessing signal C and the preprocessing signal D are performed AND operation, and then the AND operation results of the two and the preprocessing signal A are performed OR operation to obtain the driving signal ug10 of the switch tube S10.

[0014] A further improvement of the present invention is that a switching state configuration of the inverter under each working mode is defined, specifically: the switching state under working mode M1 is [0,1,0,0,1,0,0,0,0,1], the switching state under working mode M2 ​​is [1,1,0,1,0,0,0,1,0,1], the switching state under working mode M3 is [1,0,0,1,0,0,0,1,1,1], the switching state under working mode M4 is [1,0,0,0,1,1,1,0,1,0], the switching state under working mode M5 is [0,0,1,1,0,0,0,1,1,0], and the switching state under working mode M6 is [0,0,1,0,1,0,0,0,1,0], where 0 indicates that the IGBT switch tube is turned off and 1 indicates that the IGBT switch tube is turned on.

[0015] The beneficial effects of the present invention are as follows: the present invention provides a common ground type five-level photovoltaic inverter with capacitor voltage self-balancing function, wherein the photovoltaic panel on the DC side and the AC side load are connected in a common ground manner, short-circuiting the parasitic capacitance of the photovoltaic panel to the ground, thereby effectively eliminating the influence of leakage current. The inverter outputs a doubled voltage five-level voltage in the entire working cycle through the control signal of the switch capacitor and the switch tube, and the output voltage range is 0, ±U PV 、±2U PV The five-level design increases the output voltage amplitude and improves the utilization rate of DC voltage, while suppressing harmonic generation and reducing the size of the filter. PV The working mode of the inverter is realized, thereby achieving self-balancing of the charge and discharge of the switching capacitor voltage. This design effectively avoids the continuous discharge of capacitor C2 during the negative half cycle of the inverter output, significantly reduces the capacitor voltage ripple, and further improves the quality of the inverter output voltage waveform. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is the main circuit structure diagram of the present invention.

[0017] Figure 2 It is the logic control principle diagram of the present invention.

[0018] Figure 3 It is a timing diagram of the driving signal of the present invention.

[0019] Figure 4 It is a schematic diagram of mode 1 in the present invention.

[0020] Figure 5 It is a schematic diagram of mode 2 in the present invention.

[0021] Figure 6 It is a schematic diagram of mode three in the present invention.

[0022] Figure 7 It is a schematic diagram of mode four in the present invention.

[0023] Figure 8 It is a schematic diagram of mode five in the present invention.

[0024] Fig. 9 It is a schematic diagram of mode six in the present invention.

[0025] Fig.10 This is the SPWM voltage waveform diagram output by the present invention.

[0026] Fig.11 This is a leakage current waveform diagram of the present invention.

[0027] Fig.12 This is a waveform diagram of the switched capacitor of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] It should be emphasized that in the process of describing the present invention, various formulas and constraints are distinguished by consistent labels, but the use of different labels to mark the same formula and / or constraints is not excluded. The purpose of this setting is to more clearly illustrate the characteristics of the present invention.

[0030] In order to improve the DC voltage utilization rate of the inverter, improve the output voltage quality and achieve zero leakage current. The present invention provides a common ground type five-level photovoltaic inverter with capacitor voltage self-balancing function, such as Figure 1 As shown, it includes a photovoltaic cell PV, a five-level inverter circuit with a capacitor voltage self-balancing function, a single-phase output LC filter circuit and a single-phase load. The five-level inverter circuit includes a DC input filter capacitor Cdc, two switch capacitors C1 and C2, and ten switch tubes S1 to S10, wherein the switch tube S1 is an IGBT without a freewheeling diode, and the switch tubes S2 to S9 are all IGBTs with freewheeling diodes. The single-phase output LC filter circuit and the single-phase load include a filter inductor Lf, a filter capacitor Cf and a single-phase load Ro.

[0031] The positive electrode of the photovoltaic cell PV is connected to the positive electrode of the DC input filter capacitor Cdc and the collector of the switch tube S1; the emitter of the switch tube S1 is connected to the collector of the switch tube S2, the collector of the switch tube S3, the collector of the switch tube S4 and the switch capacitor C 1is connected to the positive electrode; the emitter of switch S2 is connected to the collector of switch tube S9 and one end of filter inductor Lf; the emitter of switch tube S4 is connected to the collector of switch tube S5 and the positive electrode of switch capacitor C2; the negative electrode of switch capacitor C1 is connected to the emitter of switch tube S5, the collector of switch tube S6, and the collector of switch tube S8; the emitter of switch tube S6 is connected to the emitter of switch tube S7; the negative electrode of switch capacitor C2 is connected to the emitter of switch tube S8, the emitter of switch tube S9, and the emitter of switch tube S10; the other end of filter inductor Lf is connected to the positive electrode of filter capacitor Cf and one end of load Ro; the negative electrode of photovoltaic cell PV is connected to the negative electrode of DC input filter capacitor Cdc, the emitter of switch tube S3, the emitter of switch tube S7, the collector of switch tube S10, the negative electrode of filter capacitor Cf, and the other end of load Ro.

[0032] Switch tube S7 is added to the common-ground five-level photovoltaic inverter circuit with capacitor voltage self-balancing function. Among them, switch tube S6 and switch tube S7 form a pair of reversely connected switch combinations in series, so as to realize the bidirectional flow of current in this branch. At the same time, this switch combination also provides a charging path for switch capacitor C1, a discharging path for switch capacitor C2, and an energy feedback path.

[0033] This embodiment also provides a control method for a common-ground five-level photovoltaic inverter with capacitor voltage self-balancing function, as Figure 2 and Figure 3 shown, which specifically includes the following steps:

[0034] The first step: The sine wave reference signal uref is respectively intercepted and compared with two in-phase stacked triangular carriers uc1 and uc2 on the positive half-axis and two phase-shifted triangular carriers uc3 and uc4 on the negative half-axis. When uref>uc1, a high level is output; when uref<uc1, a low level is output to generate a preprocessing signal A, and its inverse is taken to obtain a preprocessing signal a; similarly, when uref>uc2, a high level is output; when uref<uc2, a low level is output to generate a preprocessing signal B, and its inverse is taken to obtain a preprocessing signal b; when uref>uc3, a high level is output; when uref<uc3, a low level is output to generate a preprocessing signal C, and its inverse is taken to obtain a preprocessing signal c. Similarly, when uref>uc4, a high level is output; when uref<uc4, a low level is output to generate a preprocessing signal D, and its inverse is taken.

[0035] Step 2: According to the preprocessing signal generated in the first step, combined with the signal status under different working modes, determine the logic control signal of each switch tube. Specifically, perform an AND operation on the inverted signal a of preprocessing signal A and preprocessing signal B, perform an AND operation on the inverted signal b of preprocessing signal B and preprocessing signal C and preprocessing signal D, perform an AND operation on preprocessing signal C and inverted signal d of preprocessing signal D, and then perform an OR operation on the AND operation results of the three to obtain the drive signal ug1 of switch tube S1; perform an AND operation on the inverted signal a of preprocessing signal A and preprocessing signal B, and then perform an OR operation on the AND operation result and preprocessing signal A to obtain the drive signal ug2 of switch tube S2; perform an AND operation on the inverted signal c of preprocessing signal C and preprocessing signal D, and perform an AND operation on the inverted signal c of preprocessing signal C and preprocessing signal D. An AND operation is performed on the inverted signal d of signal D, and then an OR operation is performed on the AND operation results of the two to obtain the drive signal ug3 of the switch tube S3; an AND operation is performed on the inverted signal a of the preprocessed signal A and the preprocessed signal B, an AND operation is performed on the inverted signal b of the preprocessed signal B and the preprocessed signal C and the preprocessed signal D, an AND operation is performed on the inverted signal c of the preprocessed signal C and the preprocessed signal D, and then an OR operation is performed on the AND operation results of the three to obtain the drive signals ug4 and ug6 of the switch tubes S4 and S6; an AND operation is performed on the preprocessed signal C and the inverted signal d of the preprocessed signal D, and an AND operation is performed on the inverted signal c of the preprocessed signal C and the inverted signal d of the preprocessed signal D , and then perform an OR operation on the AND operation results of the two and the preprocessing signal A to obtain the drive signal ug5 of the switch S5; perform an AND operation on the preprocessing signal C and the negated signal of the preprocessing signal D to obtain the drive signals ug6 and ug7 of the switch tubes S6 and S7; perform an AND operation on the negated signal a of the preprocessing signal A and the preprocessing signal B, perform an AND operation on the negated signal b of the preprocessing signal B and the preprocessing signal C and the preprocessing signal D, and perform an AND operation on the negated signal c of the preprocessing signal C and the preprocessing signal D, and then perform an OR operation on the AND operation results of the three to obtain the drive signal ug8 of the switch tube S8; perform an AND operation on the negated signal b of the preprocessing signal B and the preprocessing signal C And the preprocessing signal D are ANDed, the preprocessing signal C and the inverted signal d of the preprocessing signal D are ANDed, the inverted signal c of the preprocessing signal C and the preprocessing signal D are ANDed, the inverted signal c of the preprocessing signal C and the inverted signal d of the preprocessing signal D are ANDed, and then the AND operation results of the four are performed OR operation to obtain the driving signal ug9 of the switch tube S9; the inverted signal a of the preprocessing signal A and the preprocessing signal B are performed AND operation, the inverted signal b of the preprocessing signal B and the preprocessing signal C and the preprocessing signal D are performed AND operation, and then the AND operation results of the two and the preprocessing signal A are performed OR operation to obtain the driving signal ug10 of the switch tube S10.

[0036] Therefore, through the above control method, the inverter can switch between six working modes [M1, M2, M3, M4, M5, M6], each working mode corresponds to a different output SPWM voltage and a corresponding switching state; the working mode M1 indicates that the inverter output SPWM voltage is 2U PV , the corresponding switch state is [0,1,0,0,1,0,0,0,0,1]; the working mode M2 ​​means that the inverter output SPWM voltage is U PV , the corresponding switch state is [1,1,0,1,0,0,0,1,0,1]; working mode M3 means that the inverter output SPWM voltage is 0, and the corresponding switch state is [1,0,0,1,0,0,0,1,1,1]; working mode M4 means that the inverter output SPWM voltage is -U PV At this time, the switch capacitor C1 is in a charging state, and the switch capacitor C2 provides energy to the load. The corresponding switch state is [1,0,0,0,1,1,1,0,1,0]; the working mode M5 indicates that the inverter output SPWM voltage is -U PV At this time, the switch capacitor C1 charges the capacitor C2, and then the two are connected in parallel to supply power to the load. The corresponding switch state is [0,0,1,1,0,0,0,1,1,0]; the working mode M6 indicates that the inverter output SPWM voltage is -2U PV , the corresponding switch state is [0,0,1,0,1,0,0,0,1,0].

[0037] The above working modes are as follows Figures 4 to 9 As shown, the working principle of the inverter in each working mode is analyzed in detail below:

[0038] Mode 1: If Figure 4 As shown in the figure, in this mode, the switching state of the inverter is [0,1,0,0,1,0,0,0,0,1], the switch tubes S2, S5 and S10 are in the on state, and the switch tubes S1, S3, S4, S6, S7, S8 and S9 are in the off state. The current flows out from the positive electrode of the switch capacitor C1, flows through S4-S2-Lf-Ro-S10, and then returns to the negative electrode of the switch capacitor C2. The switch tube S5 connects the two switch capacitors C1 and C2 in series. At this time, both switch capacitors are in the forward discharge state, and the inverter output SPWM voltage is 2U PV .

[0039] Mode 2: If Figure 5As shown, in this mode, the switching state of the inverter is [1,1,0,1,0,0,0,1,0,1], the switch tubes S1, S2, S4, S8 and S10 are in the on state, and the switch tubes S3, S5, S6, S7 and S9 are in the off state. The current flows out from the positive pole of the photovoltaic cell PV, flows through S1-C1-S8-S10, S1-S4-C2-S10, S1-S2-Lf-Ro, and finally flows back to the negative pole of the photovoltaic cell PV. At this time, the switch capacitors C1 and C2 are both in the charging state, the photovoltaic cell PV on the DC side directly supplies power to the load, and the inverter output SPWM voltage is U PV .

[0040] Mode 3: If Figure 6 As shown in the figure, in this mode, the switching state of the inverter is [1,0,0,1,0,0,0,1,1,1], the switch tubes S1, S4, S8, S9 and S10 are in the on state, and the switch tubes S2, S3, S5, S6 and S7 are in the off state. The current flows out from the positive pole of the photovoltaic cell PV, flows through S1-C1-S8-S10, S1-S4-C2-S10 respectively, and then flows back to the negative pole of the photovoltaic cell PV. At the same time, the current on the filter and the load continues to flow in the loop formed by S9 and S10. At this time, the switch capacitors C1 and C2 are both kept in the charged state, and the inverter output SPWM voltage is 0.

[0041] Mode 4: If Figure 7 As shown, in this mode, the switching state of the inverter is [1,0,0,0,1,1,1,0,1,0], the switch tubes S1, S5, S6, S7 and S9 are in the on state, and the switch tubes S2, S3, S4, S8 and S10 are in the off state. The current flows out from the positive pole of the photovoltaic cell PV, flows through S1-C1-S6-S7, and then flows back to the negative pole of the photovoltaic cell PV. At the same time, the current on the switch capacitor C2 flows out from the positive pole, through S5-S6-S7-Ro-Lf-S9, and returns to the negative pole of the switch capacitor C2. At this time, the DC side photovoltaic cell PV charges the switch capacitor C1 through the loop, and the switch capacitor C2 discharges to the load. The inverter output SPWM voltage is -U PV .

[0042] Mode 5: If Figure 8 As shown in the figure, in this mode, the switching state of the inverter is [0,0,1,1,0,0,0,1,1,0], the switch tubes S3, S4, S8 and S9 are in the on state, and the switch tubes S1, S2, S5, S6, S7 and S10 are in the off state. Since the voltage of the switch capacitor C1 is higher, the current flows out from its positive electrode, flows through S4-C2-S8 in sequence, and flows back to the negative electrode of the switch capacitor C1. When the voltages of the two switch capacitors C1 and C2 both reach U PVAfter that, the current flows through S3-Ro-Lf-S9. At this time, the switch capacitor C1 charges the switch capacitor C2, and then the two are discharged in parallel. The inverter output SPWM voltage is -U PV .

[0043] Mode 6: If Fig. 9 As shown in the figure, in this mode, the switching state of the inverter is [0,0,1,0,1,0,0,0,1,0], the switch tubes S3, S5 and S9 are in the on state, and the switch tubes S1, S2, S4, S6, S7, S8 and S10 are in the off state. The current flows out from the positive electrode of the switch capacitor C2, flows through C2-S5-C1-S3-Ro-Lf-S9, and finally flows back to the negative electrode of the switch capacitor C2. At this time, the switch capacitors C1 and C2 are both in the reverse discharge state, and the inverter output SPWM voltage is -2U PV .

[0044] Table 1 shows the switch state, switch capacitor state and output SPWM voltage of the common ground type five-level photovoltaic inverter with capacitor voltage self-balancing function in different working modes.

[0045] Table 1 Switch tube state, switch capacitor state and output SPWM voltage in each working mode of the inverter

[0046]

[0047]

[0048] According to the above specific implementation scheme, the common ground type five-level photovoltaic inverter with capacitor voltage self-balancing function of the present invention is simulated by MATLAB / Simulink, and its output SPWM voltage waveform and leakage current waveform are obtained, respectively as shown in Fig.10 and Fig.11 The SPWM voltage peak value of the inverter output reaches 2U PV , and form five voltage levels: 0, ±U PV and ±2U PV Compared with the traditional three-level inverter, this design significantly reduces the output harmonic content, reduces the filter volume, and improves the output voltage amplitude and DC voltage utilization. In addition, this topology effectively eliminates leakage current through common ground configuration, and simulation results show that zero leakage current is achieved.

[0049] As shown in the table above, the inverter is constructed by two output voltages -U PV The working mode realizes the self-balance of the charge and discharge of the switch capacitor voltage, effectively avoids the continuous discharge of capacitor C2 in the negative half cycle, significantly reduces the capacitor voltage ripple, and improves the quality of the output voltage waveform. The simulation waveforms of the switch capacitors C1 and C2 are as follows: Fig.12shown.

[0050] In summary, the present invention provides a common-ground five-level photovoltaic inverter with capacitor voltage self-balancing function, which has the following significant advantages: this topology eliminates system leakage current and improves safety by connecting the DC side and the AC side to the common ground; it adopts voltage-doubling five-level output technology to improve the DC voltage utilization rate and effectively reduce voltage harmonics; by increasing the inverter working mode, it realizes self-balancing of the switching capacitor voltage, reduces the capacitor voltage ripple, and thus improves the quality of the output voltage waveform.

[0051] The above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A common ground type five-level photovoltaic inverter with capacitor voltage self-balancing function, characterized in that: It includes a photovoltaic cell PV, a five-level inverter circuit with a capacitor voltage self-balancing function, a single-phase output LC filter circuit, and a single-phase load; the five-level inverter circuit includes a DC input filter capacitor Cdc, two switching capacitors C1, C2, and ten switching tubes S1 to S10, where the switching tube S1 is an IGBT without a freewheeling diode, and the switching tubes S2 to S10 are all IGBTs with freewheeling diodes; the single-phase output LC filter circuit and the single-phase load include a filter inductor Lf, a filter capacitor Cf, and a single-phase load Ro.

2. The common ground type five-level photovoltaic inverter with capacitor voltage self-balancing function according to claim 1, characterized in that: The positive electrode of the photovoltaic cell PV is connected to the positive electrode of the DC input filter capacitor Cdc and the collector of the switching tube S1; the emitter of the switching tube S1 is connected to the collectors of the switching tubes S2, S3, S4, and the positive electrode of the switching capacitor C1; the emitter of the switch S2 is connected to the collector of the switching tube S9 and one end of the filter inductor Lf; the emitter of the switching tube S4 is connected to the collector of the switching tube S5 and the positive electrode of the switching capacitor C2; the negative electrode of the switching capacitor C1 is connected to the emitters of the switching tubes S5, S6, S8; the emitter of the switching tube S6 is connected to the emitter of the switching tube S7; the negative electrode of the switching capacitor C2 is connected to the emitters of the switching tubes S8, S9, and S10; the other end of the filter inductor Lf is connected to the positive electrode of the filter capacitor Cf and one end of the load Ro; the negative electrode of the photovoltaic cell PV is connected to the negative electrode of the DC input filter capacitor Cdc, the emitters of the switching tubes S3, S7, S10, the negative electrode of the filter capacitor Cf, and the other end of the load Ro.

3. The common ground type five-level photovoltaic inverter with capacitor voltage self-balancing function according to claim 1, characterized in that: The switching tubes S6 and S7 are connected in reverse series to enable bidirectional current flow in this branch.

4. The common ground type five-level photovoltaic inverter with capacitor voltage self-balancing function according to claim 1, characterized in that: Define six working modes of the inverter [M1, M2, M3, M4, M5, M6]; working mode M1 means that the inverter output SPWM voltage is 2U PV ; Working mode M2 ​​means the inverter output SPWM voltage is U PV ; Working mode M3 means that the inverter output SPWM voltage is 0; working mode M4 means that the inverter output SPWM voltage is -U PV At this time, the switch capacitor C1 is in a charging state, and the switch capacitor C2 provides energy to the load; the working mode M5 indicates that the inverter output SPWM voltage is -U PV At this time, the switch capacitor C1 charges the capacitor C2, and then the two are connected in parallel to supply power to the load; the working mode M6 indicates that the inverter output SPWM voltage is -2U PV .

5. The common ground type five-level photovoltaic inverter with capacitor voltage self-balancing function according to claim 1, characterized in that: The control method of the common-ground photovoltaic inverter specifically includes the following steps: The first step: The sinusoidal reference signal uref is respectively compared with two in-phase stacked triangular carriers uc1, uc2 on the positive half-axis and two phase-shifted triangular carriers uc3, uc4 on the negative half-axis. When uref > uc1, a high level is output; when uref < uc1, a low level is output to generate a preprocessing signal A, and its inverse is taken to obtain a preprocessing signal a; similarly, when uref > uc2, a high level is output; when uref < uc2, a low level is output to generate a preprocessing signal B, and its inverse is taken to obtain a preprocessing signal b; when uref > uc3, a high level is output; when uref < uc3, a low level is output to generate a preprocessing signal C, and its inverse is taken to obtain a preprocessing signal c; when uref > uc4, a high level is output; when uref < uc4, a low level is output to generate a preprocessing signal D, and its inverse is taken to obtain a preprocessing signal d; Step 2: According to the preprocessing signal generated in the first step, combined with the signal states in different working modes, determine the logic control signal of each switch tube; specifically, perform an AND operation on the inverted signal a of the preprocessing signal A and the preprocessing signal B, perform an AND operation on the inverted signal b of the preprocessing signal B and the preprocessing signal C and the preprocessing signal D, perform an AND operation on the preprocessing signal C and the inverted signal d of the preprocessing signal D, and then perform an OR operation on the AND operation results of the three to obtain the drive signal ug1 of the switch tube S1; perform an AND operation on the inverted signal a of the preprocessing signal A and the preprocessing signal B, and then perform an OR operation on the AND operation result and the preprocessing signal A to obtain the drive signal ug2 of the switch tube S2; perform an AND operation on the preprocessing signal An AND operation is performed on the inverted signal c of preprocessing signal C and the inverted signal d of preprocessing signal D, and then an OR operation is performed on the AND operation results of the two to obtain the driving signal ug3 of the switch tube S3; an AND operation is performed on the inverted signal a of preprocessing signal A and the preprocessing signal B, an AND operation is performed on the inverted signal b of preprocessing signal B and the preprocessing signal C and the preprocessing signal D, an AND operation is performed on the inverted signal c of preprocessing signal C and the preprocessing signal D, and then an OR operation is performed on the AND operation results of the three to obtain the driving signals ug4 and ug6 of the switch tubes S4 and S6; an AND operation is performed on the inverted signal d of the preprocessing signal C and the preprocessing signal D, and the preprocessing signal An AND operation is performed on the inverted signal c of the preprocessed signal C and the inverted signal d of the preprocessed signal D, and then an OR operation is performed on the AND operation results of the two and the preprocessed signal A to obtain the drive signal ug5 of the switch S5; an AND operation is performed on the preprocessed signal C and the inverted signal of the preprocessed signal D to obtain the drive signals ug6 and ug7 of the switch tubes S6 and S7; an AND operation is performed on the inverted signal a of the preprocessed signal A and the preprocessed signal B, an AND operation is performed on the inverted signal b of the preprocessed signal B and the preprocessed signal C and the preprocessed signal D, an AND operation is performed on the inverted signal c of the preprocessed signal C and the preprocessed signal D, and then an OR operation is performed on the AND operation results of the three to obtain the drive signal ug8 of the switch tube S8; an AND operation is performed on the inverted signal a of the preprocessed signal B and the preprocessed signal C, and the inverted signal b of the preprocessed signal B and the preprocessed signal C and the preprocessed signal D, and then an OR operation is performed on the AND operation results of the three to obtain the drive signal ug8 of the switch tube S8; The inverted signal b is ANDed with the preprocessed signal C and the preprocessed signal D, the preprocessed signal C is ANDed with the inverted signal d of the preprocessed signal D, the inverted signal c of the preprocessed signal C is ANDed with the preprocessed signal D, the inverted signal c of the preprocessed signal C is ANDed with the inverted signal d of the preprocessed signal D, and then an OR operation is performed on the AND operation results of the four to obtain the drive signal ug9 of the switch tube S9; the inverted signal a of the preprocessed signal A is ANDed with the preprocessed signal B, the inverted signal b of the preprocessed signal B is ANDed with the preprocessed signal C and the preprocessed signal D, and then an OR operation is performed on the AND operation results of the two and the preprocessed signal A to obtain the drive signal ug10 of the switch tube S10.

6. The common ground type five-level photovoltaic inverter with capacitor voltage self-balancing function according to claim 5, characterized in that: Define the switch state configuration of the inverter under each working mode, specifically: the switch state under working mode M1 is [0,1,0,0,1,0,0,0,0,1], the switch state under working mode M2 ​​is [1,1,0,1,0,0,0,1,0,1], the switch state under working mode M3 is [1,0,0,1,0,0,0,1,1,1], the switch state under working mode M4 is [1,0,0,0,1,1,1,0,1,0], the switch state under working mode M5 is [0,0,1,1,0,0,0,1,1,0], and the switch state under working mode M6 is [0,0,1,0,1,0,0,0,1,0], where 0 indicates that the IGBT switch tube is turned off and 1 indicates that the IGBT switch tube is turned on.

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