Oscillation circuit capable of generating fixed frequency and adjustable duty ratio
By designing an oscillation circuit including charging and discharging, RDAC and high-speed comparison parts, the problem of insufficient frequency stability and duty cycle adjustment in the prior art is solved, and the effect of simple structure, stable frequency and adjustable duty cycle is achieved.
Patent Information
- Application Number
- CN202411627339.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-14
- Publication Date
- 2025-03-07
AI Technical Summary
Existing oscillation circuits have shortcomings in frequency stability and duty cycle adjustment, making them difficult to apply to chip designs that require frequency stability and duty cycle adjustment.
An oscillation circuit including a charge and discharge part, an RDAC part and a high-speed comparison part is designed. The resistance size and charge and discharge current size are controlled by the RDAC part, and the high-speed comparison part controls the comparison between the charge and discharge voltage and the reference voltage, so as to achieve fixed frequency and adjustable duty cycle.
It realizes an oscillating circuit with a simple structure, stable frequency and adjustable duty cycle, which improves tolerance for power supply and process mismatch, and is suitable for applications requiring adjustable duty cycles.
Smart Images
Figure CN119582761A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip technology, and more particularly to an oscillating circuit that generates a fixed frequency and has an adjustable duty cycle. Background Art
[0002] In chip design, multiple clock signals are often required. For chips with low clock requirements, RC oscillators are generally used. This type of oscillation is greatly affected by process, voltage, and temperature, while the cost of crystal oscillators is relatively high. In addition, this type of oscillator cannot adjust the duty cycle of the oscillation period, so it is difficult to apply it to modulation circuits where the duty cycle carries information and energy.
[0003] In existing oscillator circuits with adjustable duty cycle, multiple comparators are usually required to complete duty cycle adjustment, which has a complex design and occupies a large area. In addition, since the charging and discharging time is controlled by different circuits and implemented by different resistors and capacitors, the process tolerance is low. Summary of the invention
[0004] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a method of realizing an adjustable duty cycle circuit with a simple structure and using the same string of resistors and capacitors for charging and discharging with different duty cycles. The method not only has a very stable frequency and an adjustable duty cycle, but also has a simple structure and a high tolerance to voltage and process mismatch.
[0005] To achieve the above object, the present invention provides the following technical solutions: An oscillator circuit generating a fixed frequency and adjustable duty cycle includes a charge and discharge part, an RDAC part and a high-speed comparison part; wherein, The charging and discharging part is used for charging and discharging, and includes a PMOS tube and an NMOS tube; The RDAC part is used to control the size of the resistance and the size of the charge and discharge current, and includes a number of XNOR gates, a number of switches and a number of resistors; The high-speed comparison part includes a capacitor, a comparator, a buffer and an inverter. This part is used to control the comparison between the charge and discharge voltage and different reference voltages to complete the flipping, and feedback control the switch of the RDAC circuit.
[0006] Furthermore, a number of resistors are connected in series in sequence, a number of switches are connected in series in sequence, a number of control switches correspond to a number of resistors one by one and control the short circuit and open circuit of the resistors; one input end of a number of XENOR gates is connected to the output end of the high-speed comparison part, and the other input ends of a number of XENOR gates are respectively connected to different pins of the ADC in the chip.
[0007] Furthermore, the source of the PMOS tube is connected to the power supply terminal, the drain of the PMOS tube is connected to the drain of the NOMOS tube, the source of the NMOS tube is grounded, and the gate of the PMOS tube is connected to the gate of the NMOS tube.
[0008] Furthermore, the input of the comparator is connected to the input of the buffer, the output of the buffer is connected to the input of the inverter, the output of the inverter is connected to the positive input of the comparator, one end of the capacitor is grounded, and the other end of the capacitor is connected to the RDAC part and the negative input of the comparator.
[0009] Furthermore, the comparator has two different reference voltages VL and VH, and VL is smaller than VH.
[0010] Furthermore, the gate of the PMOS tube and the gate of the NMOS tube are both connected to the output end of the inverter.
[0011] By adopting the above technical solution, the beneficial effects of the present invention are: 1. The circuit structure is very simple and only requires a string of resistors, a comparator, and several logic gates and other electronic components.
[0012] 2. The total resistance experienced by the circuit of the present invention during charging and discharging is fixed for different duty cycles, so it can be ensured that the frequency is very stable while adjusting the duty cycle, and is less affected by power supply and process mismatch.
[0013] 3. The duty cycle adjustment method of the circuit of the present invention is suitable for isolating switch drive modulation energy usage. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 Schematic diagram of the circuit structure of an embodiment of the present invention.
[0015] Figure 2 FIG. 4 is a working timing diagram of an embodiment of the present invention. DETAILED DESCRIPTION
[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0017] In the description of the present invention, it is necessary to understand that the terms "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
[0018] The present invention relates to an oscillation circuit that can generate an oscillation with a fixed frequency and adjustable duty cycle. As shown in Figure 1 the circuit block diagram, it includes a charge-discharge part, an RDAC part, and a high-speed comparison part. The RDAC part is used to control the size of the resistor, thereby controlling the size of the charge-discharge current. The high-speed comparison part controls the comparison between the charge-discharge voltage and different reference voltages to complete the flip, and feeds back to control the switch of the RDAC circuit, thereby generating an oscillation circuit with a fixed frequency and adjustable duty cycle.
[0019] The shown charge-discharge part is composed of P0 and N0. P0 is a PMOS and N0 is an NMOS, and their driving current capabilities are set to be close.
[0020] The shown RDAC part includes four XNOR gates X0, X1, X2, and X3, four output control switches S3, S2, S1, and S0, and four resistors 36R1, 18R1, 9R1, and R0. Among them, X0, X1, X2, and X2 have a common input StN, and different inputs D3, D2, D1, and D0. These 4 different inputs can come from an ADC. 36R1, 18R1, and 9R1 are binary weighted resistors, and R0 is a reference resistor. The output control switches S3, S2, and S1 control the short-circuit and open-circuit of 36R1, 18R1, and 9R1 to complete the binary weighted control of the resistor. When D3, D2, D1, and D0 are fixed values, the jump of StN will be reflected on S3, S2, S1, and S0, thereby changing the resistor connected in the charging path.
[0021] The shown high-speed comparison part, the capacitor C0 is part of the charge-discharge RC time constant, A0 is a high-speed comparator, VL and VH are different reference voltages, where VL < VH, and St and StN are the results after comparison fed back to select different voltages. B0 is a buffer, which shapes the output of the comparator, and the shaped waveform is a square wave. I0 is an inverter, and the outputs St and StN are used as feedback control.
[0022] The working timing of the present invention is as shown in Figure 2 the timing diagram.
[0023] The state before T0 shown is the reset time period. At this time, the charge-discharge part is in a high-impedance state, and VCHR is reset to VL.
[0024] The time period from t0 to t1 shown is the charging stage. Assuming D3, D2, D1, and D0 are 0001, when St = 1, the output of the XNOR gate is 0001, that is, S3, S2, and S1 are in the off state, and S0 is in the on state. At this time, R0 is short-circuited, and 36R1, 18R1, and 9R1 are open-circuited. The charging resistor obtained is: Rc = 63R1 At this time, StN is 0, P0 is controlled to be open, N0 is closed, and it is in the charging state. Assuming that the equivalent resistance of P0 is Rp, the total resistance is: Rtotal=Rp+Rc Since the initial state of VCHR is VL, when charging, the voltage difference of its reversal is: Vd=VH-VL So the charging current is: Ic=Vd / Rtotal So the charging time is: Tc=Rtotal C0 When VCHR is charged to VH, the comparator flips, St flips to 0, and the circuit enters the discharge stage.
[0025] As shown in the time period T1~T2, it is the discharge stage. Since St=0, the output of the XOR gate is 1110, so S3, S2, S1 are all closed, and S0 is open. At this time, Rdc=R0; At this time, StN=1, N0 is open, P0 is closed, and it is in the discharge state. Assuming that the equivalent resistance of N0 is Rn, the total resistance is: Rdtotal=Rn+Rdc Because the discharge is from VH to VL, the discharge voltage difference remains unchanged, which is Vd, and the discharge time is: Tc=RdTotal C0 When VCHR discharges to VL, the comparator flips again, St flips to 1, and the circuit enters the recharging stage, and the cycle repeats to form a fixed oscillation cycle, and its cycle time is: Ttotal = (Rp+63R1+R0+Rn) C0 It can be seen that in the total cycle, all Rs participate in charging and discharging. Therefore, when D3, D2, D1 and D0 change, although the charging time and discharging time change, T is always fixed, which also means that the frequency is fixed. When the overshoot and undershoot responses of different sizes are generated when the current switching is ignored, the total cycle time is completely fixed in an ideal state. Therefore, this structure can produce an oscillating circuit with a fixed frequency but an adjustable duty cycle, which is very useful for some applications that require an adjustable duty cycle.
[0026] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Common changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included in the protection scope of the present invention.
Claims
1. An oscillator circuit generating a fixed frequency and an adjustable duty cycle, characterized in that: include The charging and discharging part is used for charging and discharging, including PMOS tube and NMOS tube; The RDAC part is used to control the size of the resistance and the size of the charge and discharge current, including a number of XNOR gates, a number of switches and a number of resistors; The high-speed comparison part includes a capacitor, a comparator, a buffer and an inverter. This part is used to control the comparison between the charge and discharge voltage and different reference voltages to complete the flipping, and feedback control the switch of the RDAC circuit.
2. The oscillator circuit for generating a fixed frequency and an adjustable duty cycle according to claim 1, characterized in that: The plurality of resistors are connected in series in sequence, the plurality of switches are connected in series in sequence, the plurality of control switches correspond to the plurality of resistors one by one and control the short circuit and open circuit of the resistors; one input end of the plurality of XENOR gates is connected to the output end of the high-speed comparison part, and the other input ends of the plurality of XENOR gates are respectively connected to different pins of the ADC in the chip.
3. An oscillator circuit for generating a fixed frequency and having an adjustable duty cycle according to claim 1 or 2, characterized in that: The source of the PMOS tube is connected to the power supply terminal, the drain of the PMOS tube is connected to the drain of the NOMOS tube, the source of the NMOS tube is grounded, and the gate of the PMOS tube is connected to the gate of the NMOS tube.
4. The oscillator circuit for generating a fixed frequency and having an adjustable duty cycle according to claim 3, characterized in that: The input end of the comparator is connected to the input end of the buffer, the output end of the buffer is connected to the input end of the inverter, the output end of the inverter is connected to the positive input end of the comparator, one end of the capacitor is grounded, and the other end of the capacitor is connected to the RDAC part and the negative input end of the comparator.
5. The oscillator circuit for generating a fixed frequency and having an adjustable duty cycle according to claim 4, characterized in that: The comparator has two different reference voltages VL and VH, and VL is smaller than VH.
6. The oscillator circuit for generating a fixed frequency and having an adjustable duty cycle according to claim 5, characterized in that: The gate of the PMOS tube and the gate of the NMOS tube are both connected to the output end of the inverter.