A low-overhead four-point flip-flop hardened latch

Abstract

The application relates to the technical field of latches, and discloses a low-overhead four-point flip-flop reinforced latch, which comprises a transmission gate assembly and an inverter assembly connected with the transmission gate assembly, and a node assembly is formed between the transmission gate assembly and the inverter assembly; the transmission gate assembly comprises transmission gates TG1-TG12; the inverter assembly comprises inverters DI1-DI24; and the node assembly comprises nodes N1-N24 located on the inverter assembly. The application has higher reliability, lower power consumption and greatly reduced delay, and can be widely applied to the fields of aerospace and medical treatment and the like which have high latch reliability requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of latch, in particular to a low-overhead four-point-flip hardened latch. BACKGROUND

[0002] With the continuous development of nanometer process, the performance and integration of integrated circuits have been greatly improved, but at the same time, the sensitivity of integrated circuits to soft errors has been significantly improved. Soft error is caused by high-energy particles such as alpha particles, heavy ions, neutrons, and protons hitting the sensitive area of CMOS devices. Soft error will change the logic state of the node, but will not damage the devices in the circuit.

[0003] In the field of integrated circuit radiation-hardened, researchers focus on the hardened design of memory cells, latches, and flip-flops. Due to the significant reduction in transistor size, the charge sharing effect is more and more obvious, a single high-energy particle can affect multiple nodes at the same time, causing multi-node flip, including double-node flip, three-node flip, and even four-node flip. These soft errors can seriously affect the reliability of the system. Therefore, we need to take measures to reduce the problems caused by soft errors to the reliability of the system.

[0004] In recent years, researchers have proposed a series of radiation-hardened latch designs. However, most of the traditional radiation-hardened latches can only achieve single-point flip or double-point flip, and are no longer suitable for more severe radiation environments. The existing three-point flip or four-point flip hardened latch has high power consumption, delay, and area overhead, so a low-overhead four-point flip hardened latch is proposed. SUMMARY

[0005] To solve the technical problems existing in the prior art, the present application provides a low-overhead four-point flip hardened latch.

[0006] The present application adopts the following technical scheme: a low-overhead four-point flip hardened latch, comprising a transmission gate component and an inverter component connected with the transmission gate component, a node component is formed between the transmission gate component and the inverter component;

[0007] The transmission gate component comprises transmission gates TG1-TG12;

[0008] The inverter component comprises inverters DI1-DI24;

[0009] The node component comprises nodes N1-N24 on the inverter component;

[0010] In the transparent period, the transmission gate component is turned on, the input signal D is transmitted to the node N2, the node N4, the node N6, the node N8, the node N12, the node N14, the node N16, the node N18, the node N20, the node N22 and the node N24 simultaneously, and the node N18 is taken as the output terminal Q;

[0011] In the holding period, the transmission gate component is turned off, the feedback loop 1 composed of inverters, the open loop 1 and the open loop 2 are turned off, and the data is latched in the feedback loop 1, the open loop 1 and the open loop 2.

[0012] As a further improvement of the above-mentioned scheme, the node N1 is connected with the inverter DI1 and the inverter DI20;

[0013] The node N2 is connected with the inverter DI2, the inverter DI19, the inverter DI3 and the transmission gate TG1;

[0014] The node N3 is connected with the inverter DI3 and the inverter DI10;

[0015] The node N4 is connected with the inverter DI4, the inverter DI9, the inverter DI15 and the transmission gate TG2;

[0016] The node N5 is connected with the inverter DI5, the inverter DI12 and the inverter DI22;

[0017] The node N6 is connected with the inverter DI6, the inverter DI13, the inverter DI15 and the transmission gate TG3.

[0018] As a further improvement of the above-mentioned scheme, the node N7 is connected with the inverter DI7, the inverter DI16, the inverter DI10 and the inverter DI20;

[0019] The node N8 is connected with the inverter DI8, the inverter DI1, the inverter DI11, the inverter DI23 and the transmission gate TG4;

[0020] The node N9 is connected with the inverter DI9, the inverter DI16 and the inverter DI6;

[0021] The node N10 is connected with the inverter DI10, the inverter DI17, the inverter DI21, the inverter DI11 and the transmission gate TG5;

[0022] The node N11 is connected with the inverter DI11, the inverter DI18 and the inverter DI4;

[0023] The node N12 is connected with the inverter DI12, the inverter DI7, the inverter DI1, the inverter DI21 and the transmission gate TG6.

[0024] As a further improvement of the above solution, the node N13 is connected with the inverter DI13, the inverter DI2, the inverter DI18 and the inverter DI22;

[0025] The node N14 is connected with the inverter DI14, the inverter DI7 and the transmission gate TG7;

[0026] The node N15 is connected with the inverter DI15, the inverter DI2, the inverter DI12 and the inverter DI14;

[0027] The node N16 is connected with the inverter DI16, the inverter DI5, the inverter DI17 and the transmission gate TG8;

[0028] The node N17 is connected with the inverter DI17, the inverter DI24 and the inverter DI4;

[0029] The node N18 is connected with the inverter DI18, the inverter DI5 and the transmission gate TG9.

[0030] As a further improvement of the above solution, the node N19 is connected with the inverter DI19 and the inverter DI8;

[0031] The node N20 is connected with the inverter DI20, the inverter DI13 and the transmission gate TG10

[0032] The node N21 is connected with the inverter DI21, the inverter DI6 and the inverter DI8;

[0033] The node N22 is connected with the inverter DI22, the inverter DI9, the inverter DI23 and the transmission gate TG11;

[0034] The node N23 is connected with the inverter DI23, the inverter DI14 and the inverter DI24;

[0035] The node N24 is connected with the inverter DI24, the inverter DI19, the inverter DI3 and the transmission gate TG12.

[0036] As a further improvement of the above solution, the feedback loop 1 comprises the inverter DI4, the inverter DI6, the inverter DI7, the inverter DI9, the inverter DI14, the inverter DI15, the inverter DI16 and the inverter DI17;

[0037] The open loop 1 comprises the inverter DI1, the inverter DI2, the inverter DI8 and the inverter DI19;

[0038] The open loop 2 includes inverters DI3, DI5, DI10, DI11, DI12, DI13, DI18, DI20, DI21, DI22, DI23 and DI24.

[0039] As a further improvement of the above-mentioned scheme, the transmission gates TG1-TG12 each include a PMOS transistor-1 and an NMOS transistor-1, the sources of which are connected together as the input of the transmission gate; the drains of which are connected together as the output of the transmission gate; the gate of the PMOS transistor-1 is connected to the complementary clock signal CLKB, and the gate of the NMOS transistor-1 is connected to the clock signal CLK.

[0040] As a further improvement of the above-mentioned scheme, the inverters DI1-DI24 each use a double-input inverter, and each include a PMOS transistor-2 and an NMOS transistor-2, the drains of which are connected together as the output of the double-input inverter.

[0041] Compared with the prior art, the present application has the following advantages:

[0042] 1. The present application is composed of 12 transmission gates and 24 double-input inverters, has high reliability, 95.76% self-recovery rate and 96.92% blocking rate for four-point flip of internal nodes.

[0043] 2. The present application has low power consumption due to the use of fewer transistors, and in the transparent mode, there is only one transmission gate between the input and the output, which greatly reduces the delay.

[0044] 3. The present application provides a low-overhead four-point flip hardened latch, which can be widely used in fields such as aerospace and medical care that require high reliability of latches. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 Fig. 1 is a structural schematic diagram of a low-overhead four-point flip hardened latch according to the present application;

[0046] Figure 2 Fig. 2 is a structural schematic diagram of a transmission gate and an inverter according to the present application;

[0047] Figure 3 Fig. 3 is a four-point flip fault injection waveform diagram according to the present application. DETAILED DESCRIPTION

[0048] The application will be further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the following described embodiments or technical features can be combined with each other to form new embodiments without conflict.

[0049] Embodiment 1

[0050] Please refer to Figures 1-2 The low-overhead four-point flip-flop latch of the embodiment includes a transmission gate component and an inverter component connected with the transmission gate component, and a node component is formed between the transmission gate component and the inverter component.

[0051] The transmission gate component includes transmission gates TG1-TG12.

[0052] The inverter component includes inverters DI1-DI24.

[0053] The node component includes nodes N1-N24 on the inverter component.

[0054] During the transparent period, the transmission gate component is turned on, and the input signal D is simultaneously propagated to nodes N2, N4, N6, N8, N12, N14, N16, N18, N20, N22 and N24, and node N18 is taken as the output end Q.

[0055] During the holding period, the transmission gate component is turned off, and the inverters form a feedback loop 1, an open loop 1 and an open loop 2, and the data is latched in the feedback loop 1, the open loop 1 and the open loop 2.

[0056] Node N1 is connected with inverter DI1 and inverter DI20.

[0057] Node N2 is connected with inverter DI2, inverter DI19, inverter DI3 and transmission gate TG1.

[0058] Node N3 is connected with inverter DI3 and inverter DI10.

[0059] Node N4 is connected with inverter DI4, inverter DI9, inverter DI15 and transmission gate TG2.

[0060] Node N5 is connected with inverter DI5, inverter DI12 and inverter DI22.

[0061] Node N6 is connected with inverter DI6, inverter DI13, inverter DI15 and transmission gate TG3.

[0062] Node N7 is connected with inverter DI7, inverter DI16, inverter DI10 and inverter DI20.

[0063] Node N8 is connected to inverter DI8, inverter DI1, inverter DI11, inverter DI23 and transmission gate TG4;

[0064] Node N9 is connected to inverter DI9, inverter DI16 and inverter DI6;

[0065] Node N10 is connected to inverter DI10, inverter DI17, inverter DI21, inverter DI11 and transmission gate TG5;

[0066] Node N11 is connected to inverter DI11, inverter DI18 and inverter DI4;

[0067] Node N12 is connected to inverter DI12, inverter DI7, inverter DI1, inverter DI21 and transmission gate TG6;

[0068] Node N13 is connected to inverter DI13, inverter DI2, inverter DI18 and inverter DI22;

[0069] Node N14 is connected to inverter DI14, inverter DI7 and transmission gate TG7;

[0070] Node N15 is connected to inverter DI15, inverter DI2, inverter DI12 and inverter DI14;

[0071] Node N16 is connected to inverter DI16, inverter DI5, inverter DI17 and transmission gate TG8;

[0072] Node N17 is connected to inverter DI17, inverter DI24 and inverter DI4;

[0073] Node N18 is connected to inverter DI18, inverter DI5 and transmission gate TG9;

[0074] Node N19 is connected to inverter DI19 and inverter DI8;

[0075] Node N20 is connected to inverter DI20, inverter DI13 and transmission gate TG10;

[0076] Node N21 is connected to inverter DI21, inverter DI6 and inverter DI8;

[0077] Node N22 is connected to inverter DI22, inverter DI9, inverter DI23 and transmission gate TG11;

[0078] Node N23 is connected to inverter DI23, inverter DI14 and inverter DI24;

[0079] Node N24 is connected with inverter DI24, inverter DI19, inverter DI3 and transmission gate TG12.

[0080] Embodiment 2:

[0081] Feedback loop 1 includes inverter DI4, inverter DI6, inverter DI7, inverter DI9, inverter DI14, inverter DI15, inverter DI16 and inverter DI17;

[0082] Open loop 1 includes inverter DI1, inverter DI2, inverter DI8 and inverter DI19;

[0083] Open loop 2 includes inverter DI3, inverter DI5, inverter DI10, inverter DI11, inverter DI12, inverter DI13, inverter DI18, inverter DI20, inverter DI21, inverter DI22, inverter DI23 and inverter DI24.

[0084] Transmission gate TG1-TG12 each includes a PMOS transistor-1 and an NMOS transistor-1, the sources of the PMOS transistor-1 and the NMOS transistor-1 are connected, as the input of the transmission gate; the drains of the PMOS transistor-1 and the NMOS transistor-1 are connected, as the output of the transmission gate; the gate of the PMOS transistor-1 is connected with a complementary clock signal CLKB, and the gate of the NMOS transistor-1 is connected with a clock signal CLK.

[0085] Inverters DI1-DI24 each are a double-input inverter, and each include a PMOS transistor-2 and an NMOS transistor-2, the drains of the PMOS transistor-2 and the NMOS transistor-2 are connected, as the output end of the double-input inverter.

[0086] Embodiment 3:

[0087] The low-overhead four-point-flip hardened latch includes 12 transmission gates and 24 double-input inverters, the double-input inverters form three ring structures, including feedback loop 1, open loop 1 and open loop 2; the feedback loop is a ring structure with internal feedback, and the open loop is a ring structure without internal feedback.

[0088] Feedback loop 1 is composed of fourth double-input inverter DI4, sixth double-input inverter DI6, seventh double-input inverter DI7, ninth double-input inverter DI9, fourteenth double-input inverter DI14, fifteenth double-input inverter DI15, sixteenth double-input inverter DI16 and seventeenth double-input inverter DI17;

[0089] The open loop 1 is composed of a first double input inverter DI1, a second double input inverter DI2, an eighth double input inverter DI8, and a nineteenth double input inverter DI19;

[0090] The open loop 2 is composed of a third double input inverter DI3, a fifth double input inverter DI5, a tenth double input inverter DI10, an eleventh double input inverter DI11, a twelfth double input inverter DI12, a thirteenth double input inverter DI13, an eighteenth double input inverter DI18, a twentieth double input inverter DI20, a twenty-first double input inverter DI21, a twenty-second double input inverter DI22, a twenty-third double input inverter DI23, and a twenty-fourth double input inverter DI24.

[0091] The 12 transmission gates are a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, a fifth transmission gate TG5, a sixth transmission gate TG6, a seventh transmission gate TG7, an eighth transmission gate TG8, a ninth transmission gate TG9, a tenth transmission gate TG10, an eleventh transmission gate TG11, and a twelfth transmission gate TG12; the 12 transmission gates are completely identical and have the same clock control signal.

[0092] The 24 double input inverters are a first double input inverter DI1, a second double input inverter DI2, a third double input inverter DI3, a fourth double input inverter DI4, a fifth double input inverter DI5, a sixth double input inverter DI6, a seventh double input inverter DI7, an eighth double input inverter DI8, a ninth double input inverter DI9, a tenth double input inverter DI10, an eleventh double input inverter DI11, a twelfth double input inverter DI12, a thirteenth double input inverter DI13, a fourteenth double input inverter DI14, a fifteenth double input inverter DI15, a sixteenth double input inverter DI16, a seventeenth double input inverter DI17, an eighteenth double input inverter DI18, a nineteenth double input inverter DI19, a twentieth double input inverter DI20, a twenty-first double input inverter DI21, a twenty-second double input inverter DI22, a twenty-third double input inverter DI23, and a twenty-fourth double input inverter DI24; the 24 double input inverters are completely identical in structure.

[0093] Reference Figure 2It is a transistor circuit of double-input inverter and transmission gate and corresponding gate circuit; all double-input inverters are composed of one PMOS transistor and one NMOS transistor. The drain of the PMOS transistor is connected with the drain of the NMOS transistor, as the output end OUT of the double-input inverter; the source of the PMOS transistor is connected with the power supply signal VDD, and the gate is connected with the first signal input end I1; the source of the NMOS transistor is connected with the ground signal GND, and the gate is connected with the second signal input end I2.

[0094] The fault-tolerant principle of the latch proposed in the application is described below; before analyzing the principle, three properties of the double-input inverter are introduced first:

[0095] Property 1: If the logic values of the input ends I1 and I2 are the same, the logic value of the output end OUT is opposite to I1 and I2.

[0096] Property 2: When the input ends I1 and I2 are high level, if I2 becomes low level, at this time, the PMOS and NMOS transistors are in OFF state at the same time, due to the existence of the parasitic capacitance, OUT is in high resistance state, temporarily keeping low level. If I1 becomes low level, at this time, the PMOS and NMOS transistors are in ON state at the same time, due to the driving ability of the NMOS transistor being greater than that of the PMOS transistor, OUT still keeps low level.

[0097] Property 3: When the input ends I1 and I2 are low level, if I1 becomes high level, at this time, the PMOS and NMOS transistors are in OFF state at the same time. Due to the existence of the parasitic capacitance, OUT is in high resistance state, temporarily keeping high level. If I2 becomes high level, at this time, the PMOS and NMOS transistors are in ON state at the same time, due to the driving ability of the NMOS transistor being greater than that of the PMOS transistor, OUT is pulled down to low level.

[0098] In order to more clearly explain the fault-tolerant principle of the application, all four-node flipping cases are classified, and the classification is shown in Table 1: (in the table, “☆” represents the place where node flipping occurs)

[0099]

[0100] Case 1: The four flipped nodes all occur in a feedback loop or an open loop, and there are 566 cases; the fault injection waveform diagram of this case is shown as Figure 3 (1), and the specific fault injection combination is <N4, N6, N14, N16>, <N1, N2, N8, N19>, <N3, N13, N23, N24>; taking the fault injection combination <N2, N4, N6, N16> as an example, the fault-tolerant principle of the latch is analyzed;

[0101] When N18(Q) = 0, according to the property 3 of the double-input inverter, at this time, nodes N7, N9, N15, N17 are pulled down to low level, the error in the feedback loop 1 forms interlocking and cannot be self-recovered; but at this time, the error on the feedback loop 1 is isolated by the second double-input inverter DI2 and the twentieth double-input inverter DI20, the open loop 1 and the open loop 2 both maintain correct logic values, and the error is blocked;

[0102] When N18(Q) = 1, according to the property 2 of the double-input inverter, nodes N7, N9, N17 maintain correct values, and since N4, N6 both occur flip, N15 also occurs flip; at this time, the error does not form interlocking, and the error on the feedback loop 1 is quickly recovered;

[0103] When the open loop 1 and the open loop 2 occur four-point flip, since they do not form feedback interlocking inside, the error is quickly recovered;

[0104] Case 2: three of the four flipped nodes are in the same feedback loop or open loop, and the other node is in the other feedback loop or open loop, and there are 3616 cases; the fault injection waveform diagram of this case is shown in Figure 3 (2), and the specific fault injection combination is <N2, N4, N6, N16>, <N1, N8, N19, N20>, <N3, N13, N14, N23>; taking the fault injection combination <N2, N4, N6, N16> as an example, the fault tolerance principle of the latch is analyzed;

[0105] When N18(Q) = 0, according to the property 3 of the double-input inverter, the flip of nodes N2, N4, N6, N16 will cause the flip of nodes N19, N17, N9, N15 to low level, at this time, nodes N14, N7 in the feedback loop 1 maintain correct values, and the error on the open loop 1 is blocked by DI8; since nodes N7, N9 maintain correct values, node N16 is recovered, and the correct value is propagated on the feedback loop 1, so all the errors on the feedback loop 1 are recovered; similarly, the error on the open loop 1 is also recovered;

[0106] When N18(Q) = 1, according to the property 2 of the double-input inverter, nodes N9, N17, N19 maintain correct values, and since nodes N4, N6 both occur flip, node N15 also occurs flip; since at this time, the error does not form interlocking, the error on the feedback loop 1 is quickly recovered, and similarly, node N2 is quickly recovered by nodes N13, N15.

[0107] Case 3: two of the four flipped nodes are in two different feedback loops or open loops, and there are 2414 cases. The fault injection waveform diagram of this case is shown in Figure 3(3) as shown, the specific fault injection combination is <N2, N4, N6, N8>, <N1, N13, N19, N23>; taking the fault injection combination <N1, N13, N19, N23> as an example, the fault tolerance principle of the latch is analyzed;

[0108] When N18(Q) = 0, according to the property 2 of the double-input inverter, the errors are respectively blocked by the twentieth double-input inverter DI20, the twenty-second double-input inverter DI22, the eighth double-input inverter DI8 and the twenty-fourth double-input inverter DI24, and then the errors are quickly recovered;

[0109] When N18(Q) = 1, according to the property 3 of the double-input inverter, the error on N1 is blocked by the twentieth double-input inverter DI20, the nodes N8, N22 and N24 are flipped, and the error is blocked by the double-input inverter of the next stage; since the error nodes do not form a mutual lock, they are quickly recovered.

[0110] Case 4: The flipped four nodes have two in the same feedback loop or open loop, and the other two nodes are in two other feedback loops or open loops, and there are 4032 cases; the fault injection waveform diagram of this case is as shown in Figure 3 (4) as shown, the specific fault injection combination is <N2, N6, N14, N19>, <N2, N8, N15, N22>; taking the fault injection combination <N2, N6, N14, N20> as an example, the fault tolerance principle of the latch is analyzed;

[0111] When N18(Q) = 0, according to the property 3 of the double-input inverter, the nodes N7, N15 and N19 are flipped, and the node N13 is flipped since the nodes N6 and N20 are both flipped; at this time, the errors on N7, N13, N15 and N19 are blocked by the double-input inverter of the next stage; since the error nodes do not form a mutual lock, they are quickly recovered;

[0112] When N18(Q) = 1, according to the property 2 of the double-input inverter, the nineteenth double-input inverter DI19, the fifteenth double-input inverter DI15, the seventh double-input inverter DI7 and the thirteenth double-input inverter DI13 respectively block the errors on the nodes N2, N6, N14 and N20; since the error nodes do not form a mutual lock, they are quickly recovered.

[0113] In conclusion, the application is composed of 12 transmission tubes and 24 double-input inverters, has higher reliability, 95.76% self-recovery rate and 96.92% blocking rate for four-point flips of internal nodes. Since the storage module uses fewer transistors, the application has lower power consumption. In addition, in the transparent mode, there is only one transmission gate at the input and output, which greatly reduces the delay. Therefore, the application is a low-overhead four-point flip hardened latch and can be widely applied in the fields of aerospace and medical treatment and other fields with high latch reliability requirements.

[0114] The above embodiments are only preferred embodiments of the application, and cannot be used to limit the protection scope of the application. Any non-essential changes and replacements made by those skilled in the art on the basis of the application shall fall within the protection scope of the application.

Claims

1. A low-overhead four-point flip-flop hardened latch, characterized in that, It includes a transmission gate assembly and an inverter assembly connected to the transmission gate assembly, wherein a node assembly is formed between the transmission gate assembly and the inverter assembly; The transmission gate assembly includes transmission gates TG1-TG12; The inverter assembly includes inverters DI1 to DI24; The node assembly includes nodes N1-N24 located on the inverter assembly; During the transparent period, the transmission gate component is turned on, and the input signal D is simultaneously propagated to nodes N2, N4, N6, N8, N12, N14, N16, N18, N20, N22 and N24, with node N18 serving as the output terminal Q; During the hold period, the transmission gate assembly is turned off, and the inverters form feedback loop 1, open loop 1, and open loop 2, and the data is latched within feedback loop 1, open loop 1, and open loop 2. Node N1 is connected to inverters DI1 and DI20; The node N2 is connected to inverters DI2, DI19, DI3 and transmission gate TG1; Node N3 is connected to inverters DI3 and DI10; Node N4 is connected to inverters DI4, DI9, DI15 and transmission gate TG2; Node N5 is connected to inverters DI5, DI12 and DI22; Node N6 is connected to inverters DI6, DI13, DI15 and transmission gate TG3; Node N7 is connected to inverters DI7, DI16, DI10 and DI20; The node N8 is connected to inverters DI8, DI1, DI11, DI23 and transmission gate TG4; Node N9 is connected to inverters DI9, DI16, and DI6; The node N10 is connected to inverters DI10, DI17, DI21, DI11 and transmission gate TG5; Node N11 is connected to inverters DI11, DI18 and DI4; The node N12 is connected to inverters DI12, DI7, DI1, DI21 and transmission gate TG6; Node N13 is connected to inverters DI13, DI2, DI18, and DI22; Node N14 is connected to inverter DI14, inverter DI7 and transmission gate TG7; Node N15 is connected to inverters DI15, DI2, DI12 and DI14; Node N16 is connected to inverters DI16, DI5, DI17 and transmission gate TG8; Node N17 is connected to inverters DI17, DI24, and DI4. Node N18 is connected to inverter DI18, inverter DI5 and transmission gate TG9; Node N19 is connected to inverters DI19 and DI8; The node N20 is connected to inverter DI20, inverter DI13 and transmission gate TG10; Node N21 is connected to inverters DI21, DI6 and DI8; Node N22 is connected to inverters DI22, DI9, DI23 and transmission gate TG11; Node N23 is connected to inverters DI23, DI14, and DI24; The node N24 is connected to inverters DI24, DI19, DI3 and transmission gate TG12; The feedback loop 1 includes inverters DI4, DI6, DI7, DI9, DI14, DI15, DI16 and DI17; The open-loop 1 includes inverters DI1, DI2, DI8, and DI19; The open loop 2 includes inverters DI3, DI5, DI10, DI11, DI12, DI13, DI18, DI20, DI21, DI22, DI23, and DI24.

2. The low-overhead four-point flip-flop hardened latch as described in claim 1, characterized in that, The transmission gates TG1-TG12 each include a PMOS transistor-1 and an NMOS transistor-1. The sources of the PMOS transistor-1 and the NMOS transistor-1 are connected to serve as the input of the transmission gate; the drains of the PMOS transistor-1 and the NMOS transistor-1 are connected to serve as the output of the transmission gate. The gate of PMOS transistor-1 is connected to the complementary clock signal CLKB, and the gate of NMOS transistor-1 is connected to the clock signal CLK.

3. The low-overhead four-point flip-flop hardened latch as described in claim 1, characterized in that, The inverters DI1-DI24 are all dual-input inverters, each including a PMOS transistor-2 and an NMOS transistor-2. The drains of the PMOS transistor-2 and the NMOS transistor-2 are connected, serving as the output terminals of the dual-input inverters.

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