Slope Control Circuit, Chip and Electronic Device

Abstract

This application belongs to the field of electronic circuit technology, and provides a slope control circuit, a chip and an electronic device. The circuit includes a coupling module, a first switching module, a second switching module, a Miller compensation module and a logic module. The logic module is respectively connected to the coupling module, the second switching module, the Miller compensation module, the controller and the gate of the first field-effect transistor. The first switching module is respectively connected to the second switching module, the Miller compensation module and the drain of the first field-effect transistor. The logic module outputs a first voltage signal, a second voltage signal and a third voltage signal according to the first level signal output by the controller. The coupling module outputs a coupling signal according to the first voltage signal, so that the first field-effect transistor enters the saturation region. The Miller compensation module reduces the rising speed of the gate voltage of the first field-effect transistor after the first field-effect transistor enters the saturation region. The first switching module conducts according to the second level signal, so that the second switching module conducts according to the second voltage signal and the third voltage signal.

Description

Technical Field

[0001] This application belongs to the technical field of electronic circuits, and particularly relates to a slope control circuit, a chip, and an electronic device. Background Art

[0002] In the application of integrated circuits, chips or MCUs (Microcontroller Units) and slave chips that cooperate at all levels need to transmit data through I / O (Input / Output) ports. Taking the most widely used I 2 C (Inter-Integrated Circuit) communication as an example, data transmission between devices connected to the bus is achieved through a serial data line (SDA) and a serial clock line (SCL). The output stage of the devices connected to the bus adopts an open-drain structure.

[0003] When the open-drain of the I / O port is cut off, the power supply charges the parasitic capacitance through the pull-up resistor, pulling the bus high. Usually, the RC time constant is large, the rising edge is relatively gentle, and the rising slope is small; when the open-drain of the I / O port is turned on, the bus is pulled low through the pull-down transistor. To ensure the accuracy of data, the low-level voltage of the I / O port should be less than 0.4V, which makes the on-resistance of the I / O port very small, so the RC time constant is small, the falling edge is relatively steep, and the falling slope is large, resulting in a large difference in the slopes of the rising edge and the falling edge, serious waveform asymmetry, and signal duty cycle deviation. At the same time, due to the parasitic inductance and capacitance between the MCU and the slave chip, when the falling speed of the SDA is too fast, the voltage on the bus will have an undershoot and oscillation, which may cause damage to the MCU. Also, since the I 2 C protocol stipulates that the output stages of the fast mode and the high-speed mode both require a slope control circuit. Therefore, how to propose a slope control circuit is an urgent problem to be solved at present. Summary of the Invention

[0004] Embodiments of this application provide a slope control circuit, a chip, and an electronic device, which can solve the problems of undershoot and oscillation of the bus voltage caused by too fast falling speed of the SDA and large difference in the slopes of the rising edge and the falling edge.

[0005] In a first aspect, embodiments of this application provide a slope control circuit, including a coupling module, a first switch module, a second switch module, a Miller compensation module, and a logic module. The logic module is respectively connected to the coupling module, the second switch module, the Miller compensation module, a controller, and the gate of the first field-effect transistor in the I / O port. The first switch module is respectively connected to the second switch module, the Miller compensation module, and the drain of the first field-effect transistor;

[0006] The logic module is configured to output a first voltage signal, a second voltage signal, and a third voltage signal according to the first level signal output by the controller; the coupling module is configured to output a coupling signal according to the first voltage signal to make the first field effect transistor enter the saturation region; the Miller compensation module is configured to reduce the rising speed of the gate voltage of the first field effect transistor after the first field effect transistor enters the saturation region; the first switch module is configured to conduct according to a second level signal, so that the second switch module conducts according to the second voltage signal and the third voltage signal.

[0007] In a possible implementation manner of the first aspect, the coupling module includes a first capacitor and a second capacitor. The first end of the first capacitor is connected to the logic module, and the second end of the first capacitor is respectively connected to the first end of the second capacitor, the Miller compensation module, the second switch module, the logic module, and the gate of the first field effect transistor. The second end of the second capacitor is grounded.

[0008] In a possible implementation manner of the first aspect, the first switch module includes a second field effect transistor and a first resistor. The first end of the first resistor is respectively connected to the Miller compensation module and the drain of the first field effect transistor. The second end of the first resistor is connected to the gate of the second field effect transistor. The drain of the second field effect transistor is connected to the second switch module, and the source of the second field effect transistor is grounded.

[0009] In a possible implementation manner of the first aspect, the second switch module includes a third field effect transistor. The gate of the third field effect transistor is respectively connected to the logic module, the coupling module, the Miller compensation module, and the gate of the first field effect transistor. The source of the third field effect transistor is connected to the logic module, and the drain of the third field effect transistor is connected to the first switch module.

[0010] In a possible implementation manner of the first aspect, the Miller compensation module includes a third capacitor and a second resistor. The first end of the third capacitor is connected to the drain of the first field effect transistor. The second end of the third capacitor is connected to the first end of the second resistor. The second end of the second resistor is respectively connected to the coupling module, the second switch module, the logic module, and the gate of the first field effect transistor.

[0011] In a possible implementation manner of the first aspect, the logic module includes a first logic unit and a second logic unit. The first logic unit is respectively connected to the second logic unit and the controller. The second logic unit is respectively connected to the coupling module, the second switch module, the Miller compensation module, and the gate of the first field effect transistor;

[0012] The first logic unit is configured to output a first logic signal according to the first level signal output by the controller; the second logic unit is configured to output a first voltage signal, a second voltage signal, and a third voltage signal according to the first logic signal.

[0013] In a possible implementation manner of the first aspect, the first logic unit includes a NAND gate and a NOR gate. The first input terminal and the second input terminal of the NAND gate are both configured to be connected to the controller. The output terminal of the NAND gate is connected to the input terminal of the NOR gate, and the output terminal of the NOR gate is connected to the second logic unit.

[0014] In a possible implementation manner of the first aspect, the second logic unit includes a fourth field effect transistor, a fifth field effect transistor, a third resistor, and a fourth resistor. The gate of the fourth field effect transistor is respectively connected to the gate of the fifth field effect transistor and the first logic unit. The source of the fourth field effect transistor is connected to a power supply. The drain of the fourth field effect transistor is respectively connected to the coupling module and the first end of the third resistor. The second end of the third resistor is respectively connected to the second switching module and the first end of the fourth resistor. The second end of the fourth resistor is respectively connected to the drain of the fifth field effect transistor, the second switching module, the coupling module, the Miller compensation module, and the gate of the first field effect transistor. The source of the fifth field effect transistor is grounded.

[0015] In a second aspect, an embodiment of the present application provides a chip, including the slope control circuit according to any one of the first aspect.

[0016] In a third aspect, an embodiment of the present application provides an electronic device, including the chip according to any one of the second aspect.

[0017] The beneficial effects of the embodiments of the present application compared with the prior art are as follows:

[0018] An embodiment of the present application provides a slope control circuit, including a coupling module, a first switching module, a second switching module, a Miller compensation module, and a logic module. The logic module is respectively connected to the coupling module, the second switching module, the Miller compensation module, the controller, and the gate of the first field effect transistor in the I / O port. The first switching module is respectively connected to the second switching module, the Miller compensation module, and the drain of the first field effect transistor.

[0019] When the controller wants to transmit data through the bus, the logic module is used to output a first voltage signal, a second voltage signal, and a third voltage signal according to the first level signal output by the controller. The coupling module is used to output a coupling signal according to the first voltage signal, so that the first field effect transistor enters the saturation region. The Miller compensation module is used to reduce the rising speed of the gate voltage of the first field effect transistor after the first field effect transistor enters the saturation region, so as to extend the time that the first field effect transistor is in the saturation region, thereby reducing the falling speed of SDA and making the falling slope smaller. At the same time, the first switch module is used to conduct according to the second level signal (the second level signal is the level signal on SDA), so that the second switch module conducts according to the second voltage signal and the third voltage signal. After the second switch module conducts, the current flowing into the coupling module will be shunted, so that the current flowing into the coupling module decreases, resulting in a decrease in the charging current of the gate of the first field effect transistor, and further extending the time that the first field effect transistor is in the saturation region, thereby reducing the falling speed of SDA and making the falling slope smaller.

[0020] As can be seen from the above, the present application realizes the control of the falling slope of SDA by extending the time that the first field effect transistor is in the saturation region, avoiding the problems of undershoot and oscillation of the bus voltage caused by too fast falling speed of SDA, and at the same time avoiding the problem of a large difference in the slopes of the rising edge and the falling edge.

[0021] It can be understood that the beneficial effects of the above second aspect to the third aspect can be referred to the relevant descriptions in the above first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0023] Figure 1 is a schematic diagram of a device connected to the I 2 C bus;

[0024] Figure 2 is a schematic diagram of the process of changing the bus signal to a high level;

[0025] Figure 3 is a schematic diagram of the process of pulling down the bus signal;

[0026] Figure 4 is a schematic diagram of the SDA flip model;

[0027] Figure 5 is a waveform diagram of SDA;

[0028] Figure 6 It is a schematic circuit block diagram of the SDA port;

[0029] Figure 7 It is a principle block diagram of the slope control circuit provided by an embodiment of the present application;

[0030] Figure 8 It is a principle block diagram of the slope control circuit provided by another embodiment of the present application;

[0031] Figure 9 It is a schematic diagram of the circuit connection of the slope control circuit provided by an embodiment of the present application;

[0032] Figure 10 It is a schematic diagram of the relationship between the on-state of the first field-effect transistor and the falling slope of the SDA in the present application.

[0033] In the figure: 1. Slope control circuit; 10. Coupling module; 20. First switch module; 30. Second switch module; 40. Miller compensation module; 50. Logic module; 51. First logic unit; 52. Second logic unit; 2. Controller; 3. I / O port. Detailed implementation manners

[0034] In the following description, specific details such as specific system structures and technologies are proposed for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application.

[0035] It should be understood that when used in the specification and appended claims of the present application, the term "comprising" indicates the presence of the described features, wholes, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0036] It should also be understood that the term "and / or" used in the specification and appended claims of the present application refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0037] As used in the specification of this application and the appended claims, the term "if" may be construed contextually as "when" or "once" or "in response to determining" or "in response to detecting". Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be construed contextually to mean "once determined" or "in response to determining" or "once [described condition or event] is detected" or "in response to detecting [described condition or event]".

[0038] In addition, in the description of the specification of this application and the appended claims, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be construed as indicating or implying relative importance.

[0039] Reference to "one embodiment" or "some embodiments" or the like described in the specification of this application means that a specific feature, structure, or characteristic described in connection with that embodiment is included in one or more embodiments of this application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "comprising", "including", "having", and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0040] In the application of integrated circuits, chips or MCUs and slave chips that cooperate at all levels need to transmit data through I / O ports. As Figure 1 shown, taking the most widely used I 2 C communication as an example, data transmission between devices connected to the bus is achieved through the serial data line (SDA) and the serial clock line (SCL). The output stage of the device connected to the bus adopts an open-drain structure. When data is transmitted, the bus is pulled low, as Figure 3 shown; when the bus is idle, SDA and SCL pull the bus up to VDD through the pull-up resistor R PU as Figure 2 shown.

[0041] When the open-drain of the I / O port is cut off, VDD charges the parasitic capacitance C PU through the pull-up resistor R bDuring charging, the bus is pulled high. Usually, the RC time constant is large, the rising edge is relatively gentle, and the rising slope is small. When the open-drain of the I / O port conducts, the bus is pulled low through the pull-down transistor. To ensure the accuracy of data, the low-level voltage of the I / O port should be less than 0.4V, which makes the on-resistance of the I / O port very small, so the RC time constant is small, the falling edge is relatively steep, and the falling slope is large. As a result, the slopes of the rising edge and the falling edge differ greatly, the waveform shows serious asymmetry, and the signal duty cycle shifts. At the same time, due to the parasitic inductance and capacitance between the MCU and the slave chip, when the falling speed of SDA is too fast, the voltage on the bus will have undershoot and oscillation, which may cause damage to the MCU. Usually, a resistor Rs is connected in series in the open-drain structure to reduce the impact of the voltage change on the bus on the I / O port, but this will increase the cost. Also, because 2 The I2C protocol stipulates that the output stages of the fast mode and the high-speed mode both require a slope control circuit. Therefore, how to propose a slope control circuit is an urgent problem to be solved currently.

[0042] Based on this, this application proposes a slope control circuit for adjusting the falling slope of the I / O port, so that the falling time of the I / O port is only slightly affected by the pull-up resistor R PU and the parasitic capacitance C b , avoiding the problems of undershoot and oscillation of the bus voltage caused by too fast falling speed of SDA, and the problem of large difference in slopes between the rising edge and the falling edge.

[0043] The SDA flip model can be simplified as Figure 4 shown, where C b is the parasitic capacitance of the bus. When the first field-effect transistor M1 is turned off, VDD charges the parasitic capacitance C PU through the pull-up resistor R b . The formula for calculating the rising edge time of SDA is:

[0044] ;

[0045] ;

[0046] ;

[0047] where is 0.3 times of VDD, is 0.7 times of VDD, t1 is the time when SDA rises to 0.3 times of VDD, t2 is the time when SDA rises to 0.7 times of VDD, t r is the rising edge time of SDA, 0.3 and 0.7 are the thresholds stipulated by the I 2 2C protocol, and e is the base of the natural logarithm.

[0048] As can be seen from the above, the time of the rising edge is mainly affected by the pull-up resistor R PU and the parasitic capacitance C b . When the first field-effect transistor M1 is turned on, the falling speed of SDA is determined by the pulling-down ability of the first field-effect transistor M1. The I 2 C protocol stipulates that in fast mode, the maximum value of the low-level voltage VOL is 0.4V, the pulling-down current at this time is 3mA, and the maximum on-resistance of the first field-effect transistor M1 is 133Ω. Taking the fast mode as an example, =200pF, =300ns, VDD = 5V, calculate the range of the pull-up resistor R PU :

[0049] kΩ;

[0050] kΩ;

[0051] According to the common resistance values of surface mount resistors, finally select the pull-up resistor R PU to be 1.6kΩ, the parasitic capacitance C b to be 50pF, and the time of the rising edge is about 67.76ns.

[0052] The circuit diagram of the SDA port (i.e., the I / O port) is as shown in Figure 6 . When the MCU accesses the slave chip, the external signal enters the internal circuit of the slave chip through the PAD_SDA pin, and after filtering, the SDA_DEG signal is output and sent to the digital circuit of the slave chip; when the slave chip sends data to the MCU, the controller of the slave chip outputs the SDA_OUT signal, and the SDA_OUT signal controls the first field-effect transistor M1 to conduct through logic control processing, realizing the pulling-down of the bus. The falling slope of SDA is as shown in Figure 5 . It can be seen from Figure 5 that the falling slope of SDA is quite different from the rising slope of SDA, and the waveform of SDA shows serious asymmetry. The slope control circuit proposed in this application controls the gate voltage of the first field-effect transistor M1 to realize the adjustment of the falling slope of the I / O port. The adjusted falling slope of SDA is as shown by the dotted line part in Figure 5 .

[0053] The slope control circuit proposed in this application is as shown in Figure 7As shown in the figure, the slope control circuit 1 includes a coupling module 10, a first switch module 20, a second switch module 30, a Miller compensation module 40, and a logic module 50. The logic module 50 is respectively connected to the coupling module 10, the second switch module 30, the Miller compensation module 40, the controller 2, and the gate of the first field-effect transistor M1 in the I / O port 3. The first switch module 20 is respectively connected to the second switch module 30, the Miller compensation module 40, and the drain of the first field-effect transistor M1.

[0054] Specifically, when the controller 2 wants to transmit data through the bus, the controller 2 outputs a first level signal to the logic module 50, where the first level signal is a low level. The logic module 50 is used to output a first voltage signal, a second voltage signal, and a third voltage signal according to the first level signal, where the first voltage signal is greater than the second voltage signal, and the second voltage signal is greater than the third voltage signal. The coupling module 10 is used to output a coupling signal according to the first voltage signal to make the first field-effect transistor M1 enter the saturation region. The Miller compensation module 40 is used to reduce the rising speed of the gate voltage of the first field-effect transistor M1 after the first field-effect transistor M1 enters the saturation region, so as to extend the time that the first field-effect transistor M1 is in the saturation region, thereby reducing the falling speed of SDA and making the falling slope smaller. At the same time, the first switch module 20 is used to conduct according to the second level signal (the second level signal is the level signal on SDA, and at this time the level signal on SDA is a high level), so that the second switch module 30 conducts according to the second voltage signal and the third voltage signal. After the second switch module 30 conducts, it will shunt the current flowing into the coupling module 10, reduce the current flowing into the coupling module 10, resulting in a reduction in the charging current of the gate of the first field-effect transistor M1, and further extend the time that the first field-effect transistor M1 is in the saturation region, thereby reducing the falling speed of SDA and making the falling slope smaller.

[0055] As can be seen from the above, the present application realizes the control of the falling slope of SDA by extending the time that the first field-effect transistor M1 is in the saturation region, avoiding the problems of undershoot and oscillation of the bus voltage caused by the too fast falling speed of SDA, and also avoiding the problem of a large difference in slope between the rising edge and the falling edge.

[0056] It should be noted that the I / O port 3 is the I / O port of the chip, the controller 2 is arranged inside the chip, and the chip can be a slave chip or an MCU.

[0057] As the gate voltage of the first field-effect transistor M1 increases, the drain voltage (i.e., the SDA voltage) decreases. Eventually, the first field-effect transistor M1 will enter the linear region. After the first field-effect transistor M1 enters the linear region, the second switching module 30 disconnects, and the function of the Miller compensation module 40 disappears. The charging current of the gate of the first field-effect transistor M1 increases (i.e., the gate voltage of the first field-effect transistor M1 increases), so the falling slope of SDA increases. Since the gate voltage of the first field-effect transistor M1 increases, the charging current flowing from the logic module 50 to the gate of the first field-effect transistor M1 decreases, so the rising speed of the gate voltage of the first field-effect transistor M1 slows down, and the falling slope of SDA decreases.

[0058] When the first field-effect transistor M1 is in the saturation region, the SDA voltage starts to drop. This application mainly controls the falling slope of SDA by extending the time when the first field-effect transistor M1 is in the saturation region.

[0059] In some embodiments, as Figure 8 shown, the logic module 50 includes a first logic unit 51 and a second logic unit 52. The first logic unit 51 is respectively connected to the second logic unit 52 and the controller 2. The second logic unit 52 is respectively connected to the coupling module 10, the second switching module 30, the Miller compensation module 40, and the gate of the first field-effect transistor M1.

[0060] Specifically, when the controller 2 wants to transmit data through the bus, the controller 2 outputs a first level signal to the logic module 50, where the first level signal is a low level. The first logic unit 51 is used to output a first logic signal according to the first level signal, where the first logic signal is a low level. The second logic unit 52 is used to output a first voltage signal, a second voltage signal, and a third voltage signal according to the first logic signal.

[0061] In some embodiments, as Figure 9 shown, the first logic unit 51 includes a NAND gate and a NOR gate. The first input terminal and the second input terminal of the NAND gate are both used to be connected to the controller 2. The output terminal of the NAND gate is connected to the input terminal of the NOR gate. The output terminal of the NOR gate is connected to the second logic unit 52.

[0062] In some embodiments, as Figure 9As shown, the second logic unit 52 includes a fourth field-effect transistor M4, a fifth field-effect transistor M5, a third resistor R3, and a fourth resistor R4. The gate of the fourth field-effect transistor M4 is connected to the gate of the fifth field-effect transistor M5 and the output terminal of the NOR gate in the first logic unit 51 respectively. The source of the fourth field-effect transistor M4 is connected to the power supply. The drain of the fourth field-effect transistor M4 is connected to the coupling module 10 and the first end of the third resistor R3 respectively. The second end of the third resistor R3 is connected to the second switch module 30 and the first end of the fourth resistor R4 respectively. The second end of the fourth resistor R4 is connected to the drain of the fifth field-effect transistor M5, the second switch module 30, the coupling module 10, the Miller compensation module 40, and the gate of the first field-effect transistor M1 respectively. The source of the fifth field-effect transistor M5 is grounded.

[0063] In some embodiments, the coupling module 10 includes a first capacitor C1 and a second capacitor C2. The first end of the first capacitor C1 is connected to the drain of the fourth field-effect transistor M4 in the logic module 50. The second end of the first capacitor C1 is connected to the first end of the second capacitor C2, the Miller compensation module 40, the second switch module 30, the second end of the fourth resistor R4 in the logic module 50, and the gate of the first field-effect transistor M1 respectively. The second end of the second capacitor C2 is grounded.

[0064] In some embodiments, the first switch module 20 includes a second field-effect transistor M2 and a first resistor R1. The first end of the first resistor R1 is connected to the Miller compensation module 40 and the drain of the first field-effect transistor M1 respectively. The second end of the first resistor R1 is connected to the gate of the second field-effect transistor M2. The drain of the second field-effect transistor M2 is connected to the second switch module 30. The source of the second field-effect transistor M2 is grounded. Among them, the first resistor R1 is an ESD (Electrostatic Discharge) resistor, which is used to protect the circuit from electrostatic discharge damage.

[0065] In some embodiments, the second switch module 30 includes a third field-effect transistor M3. The gate of the third field-effect transistor M3 is connected to the second end of the fourth resistor R4 in the logic module 50, the second end of the first capacitor C1 in the coupling module 10, the Miller compensation module 40, and the gate of the first field-effect transistor M1 respectively. The source of the third field-effect transistor M3 is connected to the second end of the third resistor R3 in the logic module 50. The drain of the third field-effect transistor M3 is connected to the drain of the second field-effect transistor M2 in the first switch module 20.

[0066] In some embodiments, the Miller compensation module 40 includes a third capacitor C3 and a second resistor R2. The first end of the third capacitor C3 is connected to the drain of the first field effect transistor M3. The second end of the third capacitor C3 is connected to the first end of the second resistor R2. The second end of the second resistor R2 is respectively connected to the second end of the first capacitor C1 in the coupling module 10, the gate of the third field effect transistor M3 in the second switch module 30, the second end of the fourth resistor R4 in the logic module 50, and the gate of the first field effect transistor M1. Among them, the third capacitor C3 is a Miller capacitor, and the second resistor R2 is a zero-adjusting resistor.

[0067] The working principle of the present application will be described again in conjunction with Figure 9 and Figure 10 the following.

[0068] The SDA_OUT signal is the signal output by the controller 2. The SDA_OUT signal includes a first-level signal and a third-level signal. Among them, the first-level signal is a low level, and the third-level signal is a high level. When the SDA_OUT signal is at a high level, the voltages at points A and B are both low, and the voltage difference across the first capacitor C1 and the second capacitor C2 is 0. Since the signal on SDA is at a high level (i.e., the second-level signal), the second field-effect transistor M2 is in a conducting state. When the SDA_OUT signal is at a low level, it means that the controller 2 wants to perform data transmission. The voltage at point A rises to approximately equal to the power supply voltage VDD. The voltage at point B (i.e., the second voltage signal) is equal to the voltage at point A (i.e., the first voltage signal) minus the voltage drop across the third resistor R3. The voltage at point C (i.e., the third voltage signal) is equal to the voltage at point B minus the voltage drop across the fourth resistor R4. Then, the third field-effect transistor M3 conducts. Since the voltage across a capacitor cannot change suddenly, the gate voltage of the first field-effect transistor M1 will be coupled to a certain voltage by the capacitor. To enable the first field-effect transistor M1 to conduct quickly, by designing the capacitance value ratio of the first capacitor C1 and the second capacitor C2, the gate voltage of the first field-effect transistor M1 is coupled to near the conduction threshold voltage Vth, and the first field-effect transistor M1 enters the saturation region, and the SDA voltage starts to drop. For the first field-effect transistor M1 in the saturation region, the Miller effect will equivalently amplify the third capacitor C3 at the gate by the intrinsic gain multiple. Then, the equivalent capacitance of the gate of the first field-effect transistor M1 increases, resulting in a slower rising speed of the gate voltage of the first field-effect transistor M1. At the same time, when the third field-effect transistor M3 conducts, it will draw the current on the third resistor R3, resulting in a decrease in the charging current of the gate of the first field-effect transistor M1. The time for the first field-effect transistor M1 to be in the saturation region increases, and the slope of the SDA voltage drop decreases. As the gate voltage of the first field-effect transistor M1 increases, the drain voltage decreases. The first field-effect transistor M1 finally enters the linear region, the Miller effect disappears, the equivalent capacitance of the gate of the first field-effect transistor M1 decreases (i.e., the rising speed of the gate voltage of the first field-effect transistor M1 increases), the third field-effect transistor M3 turns off, and it will no longer draw the current on the third resistor R3. Then, the charging current of the gate of the first field-effect transistor M1 increases, and the slope of the SDA drop increases. The voltage at point A increases, the drain current of the fourth field-effect transistor M4 decreases, the rising rate of the gate voltage of the first field-effect transistor M1 slows down, and the slope of the SDA drop decreases. When the first field-effect transistor M1 is in the saturation region, the SDA voltage starts to drop. This application mainly controls the slope of the SDA drop by extending the time for the first field-effect transistor M1 to be in the saturation region.

[0069] In summary, the slope control circuit provided by the embodiment of this application realizes the adjustment of the falling-edge slope of the I / O port by segmentally controlling the gate voltage of the first field-effect transistor M1, avoiding the problems of the bus voltage undershoot caused by too fast a falling speed and the large difference in slopes between the rising edge and the falling edge, and ensuring that the duty cycle of the received-end signal does not shift.

[0070] The embodiment of the present application further provides a chip, including the slope control circuit described above. Since the chip provided by the embodiment of the present application adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be elaborated here one by one.

[0071] Exemplarily, the chip includes a slave chip or an MCU.

[0072] The embodiment of the present application further provides an electronic device, including the chip described above. Since the electronic device provided by the embodiment of the present application adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be elaborated here one by one.

[0073] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For parts not detailed or recorded in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0074] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A slope control circuit, characterized in that: It includes a coupling module, a first switch module, a second switch module, a Miller compensation module and a logic module, wherein the logic module is respectively connected to the coupling module, the second switch module, the Miller compensation module, a chip controller and a gate of a first field effect transistor in an I / O port of the chip, and the first switch module is respectively connected to the second switch module, the Miller compensation module and a drain of the first field effect transistor; the first switch module and the logic module are respectively connected to different ends of the second switch module, and the first switch module and the logic module are respectively connected to different ends of the Miller compensation module; The logic module is used to output a first voltage signal, a second voltage signal and a third voltage signal according to a first level signal output by the controller; the coupling module is used to output a coupling signal according to the first voltage signal, so that the first field effect transistor enters a saturation region; the Miller compensation module is used to reduce a rising speed of a gate voltage of the first field effect transistor after the first field effect transistor enters a saturation region; the first switch module is used to be turned on according to a second level signal on the I / O port, so that the second switch module is turned on according to the second voltage signal and the third voltage signal.

2. The slope control circuit according to claim 1, characterized in that: The coupling module includes a first capacitor and a second capacitor, the first end of the first capacitor is connected to the logic module, the second end of the first capacitor is respectively connected to the first end of the second capacitor, the Miller compensation module, the second switch module, the logic module and the gate of the first field effect transistor, and the second end of the second capacitor is grounded.

3. The slope control circuit according to claim 1, characterized in that: The first switch module includes a second field effect transistor and a first resistor, the first end of the first resistor is respectively connected to the Miller compensation module and the drain of the first field effect transistor, the second end of the first resistor is connected to the gate of the second field effect transistor, the drain of the second field effect transistor is connected to the second switch module, and the source of the second field effect transistor is grounded.

4. The slope control circuit according to claim 1, characterized in that: The second switch module includes a third field effect transistor, the gate of the third field effect transistor is respectively connected to the logic module, the coupling module, the Miller compensation module and the gate of the first field effect transistor, the source of the third field effect transistor is connected to the logic module, and the drain of the third field effect transistor is connected to the first switch module.

5. The slope control circuit according to claim 1, characterized in that: The Miller compensation module includes a third capacitor and a second resistor, the first end of the third capacitor is connected to the drain of the first field effect transistor, the second end of the third capacitor is connected to the first end of the second resistor, and the second end of the second resistor is respectively connected to the coupling module, the second switch module, the logic module and the gate of the first field effect transistor.

6. The slope control circuit according to claim 1, characterized in that: The logic module includes a first logic unit and a second logic unit, the first logic unit is connected to the second logic unit and the controller respectively, and the second logic unit is connected to the coupling module, the second switch module, the Miller compensation module and the gate of the first field effect transistor respectively; The first logic unit is used to output a first logic signal according to the first level signal output by the controller; The second logic unit is used to output a first voltage signal, a second voltage signal and a third voltage signal according to the first logic signal.

7. The slope control circuit according to claim 6, characterized in that: The first logic unit includes a NAND gate and a NOR gate, the first input and the second input of the NAND gate are both used to connect to the controller, the output of the NAND gate is connected to the input of the NOR gate, and the output of the NOR gate is connected to the second logic unit.

8. The slope control circuit according to claim 6, characterized in that: The second logic unit includes a fourth field effect transistor, a fifth field effect transistor, a third resistor and a fourth resistor. The gate of the fourth field effect transistor is respectively connected to the gate of the fifth field effect transistor and the first logic unit, the source of the fourth field effect transistor is connected to a power supply, the drain of the fourth field effect transistor is respectively connected to the coupling module and the first end of the third resistor, the second end of the third resistor is respectively connected to the second switch module and the first end of the fourth resistor, the second end of the fourth resistor is respectively connected to the drain of the fifth field effect transistor, the second switch module, the coupling module, the Miller compensation module and the gate of the first field effect transistor, and the source of the fifth field effect transistor is grounded.

9. A chip, characterized in that: The invention comprises the slope control circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.

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