Field programmable gate array (FPGA) embedded radio frequency unit testing method based on universal interconnection bus

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) embedded radio frequency unit test method based on a universal interconnection bus, which comprises the following steps of: configuring an FPGA embedded radio frequency unit by using an FPGA embedded processor; based on an FPGA internal programmable logic resource, the embedded radio frequency unit generates a first radio frequency signal; establishing a first radio frequency channel for the FPGA embedded radio frequency unit to receive the first radio frequency signal; detecting the received first radio frequency signal to obtain first detection data, transmitting the first detection data to the FPGA embedded processor, and comparing the first detection data with a standard value to obtain a test result of the first radio frequency channel; and transmitting the configuration parameters, the first radio frequency signal and the first detection data through a universal interconnection bus, and caching by using a memory on an FPGA (Field Programmable Gate Array) chip. Automatic testing of the FPGA embedded radio frequency unit can be achieved, the testing processing speed is increased, external testing equipment is not needed, and the testing cost is saved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a method for testing a radio frequency unit embedded in an FPGA based on a universal interconnection bus. Background Art

[0002] FPGA (Field Programmable Gate Array) has been widely used in product design and prototype verification. FPGA integrates programmable radio frequency, digital signal processor, high-performance memory, high-speed serial interface, PCIE (Peripheral Component Interconnect Express), Ethernet and other unit modules and IP cores, so that one chip can support a system application, with the characteristics of miniaturization, low cost, high performance, and flexible design.

[0003] The problems faced in testing RF units embedded in FPGAs are complex external test platforms and high test costs. In addition, to establish a connection between the RF unit and the FPGA, the conventional method is to manually modify the configuration parameters, which is not suitable for automated production testing. Summary of the invention

[0004] In order to overcome the shortcomings of the prior art, the present invention provides a method for testing an FPGA embedded radio frequency unit based on a universal interconnect bus, including: using an FPGA embedded processor to configure the FPGA embedded radio frequency unit; based on the internal programmable logic resources of the FPGA, generating a first radio frequency signal in the embedded radio frequency unit; establishing a first radio frequency channel for the FPGA embedded radio frequency unit to receive the first radio frequency signal; detecting the received first radio frequency signal to obtain first detection data, transmitting the first detection data to the FPGA embedded processor, and comparing it with the standard value to obtain the test result of the first radio frequency channel; transmitting the configuration parameters, the first radio frequency signal and the first detection data through the universal interconnect bus, and using the FPGA on-chip memory for caching. It can realize the automated testing of the FPGA embedded radio frequency unit, speed up the test processing speed, do not need external test equipment, and save the test cost.

[0005] The technical solution adopted by the present invention to solve the technical problem is as follows:

[0006] Step 1: Use the FPGA embedded processor to configure the FPGA embedded radio unit according to the configuration parameters and transmit / receive duplex mode;

[0007] Step 2: Based on the internal programmable logic resources of the FPGA, the RF unit embedded in the FPGA generates a first RF signal corresponding to the configuration parameters;

[0008] Step 3: Establish a first RF channel for the FPGA embedded RF unit to receive the first RF signal;

[0009] Step 4: Detect the first radio frequency signal received by the first radio frequency channel to obtain first detection data, and transmit the first detection data to the FPGA embedded processor;

[0010] Step 5: Transmit the configuration parameters, the first RF signal and the first detection data through the universal interconnection bus, and use the FPGA on-chip memory for caching; use the FPGA embedded processor to compare the first detection data with the specification value to obtain the test result of the first RF channel.

[0011] Preferably, the step 1 is specifically:

[0012] Step 1-1: Use the FPGA embedded processor to write the initial value of the FPGA embedded radio unit configuration register according to the configuration parameters;

[0013] Step 1-2: Configure the FPGA embedded radio unit to transmit and receive duplex mode and determine the operating parameters;

[0014] Step 1-3: Use the FPGA embedded processor to call the hardware abstraction layer function and initialize multiple working parameter states at the FPGA application layer.

[0015] Preferably, the step 2 is specifically:

[0016] Step 2-1: Generate a first single tone signal by direct digital frequency synthesis using the internal programmable logic resources of the FPGA;

[0017] Step 2-2: Based on the first single-tone signal, configure the phase word and frequency word corresponding to the configuration parameters in the FPGA embedded radio frequency unit, and output the first radio frequency signal corresponding to the configuration parameters.

[0018] Preferably, the step 3 is specifically:

[0019] A radio frequency transmitting pin of the radio frequency unit embedded in the FPGA is connected to multiple radio frequency receiving pins of the radio frequency unit embedded in the FPGA through a power divider to obtain multiple first radio frequency channels for the radio frequency unit embedded in the FPGA to receive the first radio frequency signal.

[0020] Preferably, the step 4 is specifically:

[0021] Step 4-1: Use the FPGA on-chip memory to cache the first RF signal received by the first RF channel across clock domains;

[0022] Step 4-2: performing parallel-to-serial conversion on the cached first RF signal according to the corresponding RF channel to obtain a parallel-to-serial converted signal;

[0023] Step 4-3: Perform fast Fourier transform on the parallel-to-serial converted signal to obtain a transformed signal;

[0024] Step 4-4: Determine the signal strength and signal-to-noise ratio of the received first radio frequency signal according to the transformed signal;

[0025] Step 4-5: determining first detection data according to the transmission power of the first radio frequency signal and the signal strength and signal-to-noise ratio of the received first radio frequency signal;

[0026] Step 4-6: Transmit the first detection data to the FPGA embedded processor.

[0027] Preferably, the step 5 is specifically:

[0028] Step 5-1: Using the FPGA embedded processor, compare the signal strength, signal-to-noise ratio, and transmit signal power of the first RF signal received by the first RF channel with the corresponding specification values ​​in the electrical parameter table;

[0029] Step 5-2: When the signal strength, signal-to-noise ratio, and transmitted signal power all differ from the corresponding standard values ​​by no more than a preset value, it is determined that the first RF channel is operating normally; when the signal strength or signal-to-noise ratio or transmitted signal power differs from the corresponding standard values ​​by more than a preset value, it is determined that the first RF channel is operating abnormally.

[0030] Preferably, the FPGA embedded radio frequency unit testing method further includes:

[0031] Using an automatic test machine, generating a second radio frequency signal according to configuration parameters;

[0032] Establishing a second radio frequency channel for the FPGA embedded radio frequency unit to receive a second radio frequency signal;

[0033] Detecting a second radio frequency signal received by the second radio frequency channel to obtain second detection data, and transmitting the second detection data to the FPGA embedded processor;

[0034] Using the FPGA embedded processor, the second detection data is compared with the standard value to obtain the test result of the second radio frequency channel;

[0035] When the test results of the first RF channel and the test results of the second RF channel are both normal, the test of the FPGA embedded RF unit based on the universal interconnection bus passes.

[0036] Preferably, the step of using an automatic test machine to generate a second radio frequency signal according to configuration parameters includes:

[0037] Using an automatic test machine to generate a second single tone signal;

[0038] Use an automatic test machine to configure the FPGA embedded radio frequency unit according to the configuration parameters;

[0039] Based on the second single tone signal, the FPGA embedded radio frequency unit outputs a second radio frequency signal corresponding to the configuration parameter.

[0040] Preferably, the establishment of a second RF channel for the FPGA embedded RF unit to receive the second RF signal includes: connecting the signal generator and the spectrum analyzer to the automatic test machine through the GPIB interface, connecting an RF receiving pin of the FPGA embedded RF unit to the signal generator, and connecting an RF transmitting pin of the FPGA embedded RF unit to the spectrum analyzer, so as to obtain the second RF channel for the FPGA embedded RF unit to receive the second RF signal.

[0041] Preferably, the detecting of the second RF signal received by the second RF channel to obtain the second detection data includes: the automatic test machine obtains the received second RF signal through the GPIB interface, and calculates the signal strength and signal-to-noise ratio of the received second RF signal; the automatic test machine reads the spectrum analyzer through the GPIB interface to obtain the transmission power of the second RF signal; and determines the second detection data according to the transmission power of the second RF signal and the signal strength and signal-to-noise ratio of the received second RF signal.

[0042] The beneficial effects of the present invention are as follows:

[0043] The present invention adopts an FPGA chip in-chip testing method, completes signal processing inside the chip, realizes an automatic test of an FPGA embedded radio frequency unit based on a universal interconnection bus, does not require external testing equipment, and saves testing costs; has strong versatility, and can test multiple frequency points, bandwidths and other parameters by loading different configuration files; based on FPGA internal programmable logic resources such as an FPGA embedded radio frequency unit and an FPGA embedded processor, a universal interconnection bus is used to interact with FPGA internal data, and pipeline processing of transmission, reception and judgment of test signals can be realized, thereby accelerating the test processing speed, reducing the test cache amount, and does not require additional hardware design. Only the FPGA on-chip memory is used for caching, so that the FPGA built-in test can be realized, and no external memory such as DDR is required.

[0044] In the present invention, the test results of the automatic test machine and the test results of the FPGA embedded radio frequency unit based on the universal interconnect bus of the present invention are compared for consistency, which can enhance the reliability of the final test results. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a flow chart of the method of the present invention;

[0046] Figure 2 It is a flow chart of software module design of the method of the present invention;

[0047] Figure 3 It is a hardware circuit principle block diagram of the FPGA initialization radio frequency unit of the present invention;

[0048] Figure 4 It is a flow chart of the FPGA embedded radio frequency unit testing method of the present invention. DETAILED DESCRIPTION

[0049] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0050] The present invention provides a method for testing a radio frequency unit embedded in an FPGA based on a universal interconnect bus, which can realize automatic testing of the radio frequency unit embedded in the FPGA, does not require external testing equipment, and saves testing costs.

[0051] The present invention provides a method for testing an FPGA embedded radio frequency unit based on a universal interconnect bus, comprising: using an FPGA embedded processor to configure the FPGA embedded radio frequency unit according to configuration parameters and a transmitting and receiving duplex mode; based on programmable logic resources inside the FPGA, generating a first radio frequency signal corresponding to the configuration parameters in the FPGA embedded radio frequency unit; establishing a first radio frequency channel for the FPGA embedded radio frequency unit to receive the first radio frequency signal; detecting the first radio frequency signal received by the first radio frequency channel to obtain first detection data, and transmitting the first detection data to the FPGA embedded processor; transmitting the configuration parameters, the first radio frequency signal and the first detection data through the universal interconnect bus, and using an FPGA on-chip memory for caching; using the FPGA embedded processor to compare the first detection data with a standard value to obtain a test result of the first radio frequency channel.

[0052] Specifically, the FPGA embedded processor is used to configure the FPGA embedded radio frequency unit according to the configuration parameters and the transmit / receive duplex mode, including: according to the configuration parameters, using the FPGA embedded processor, writing the initial value of the FPGA embedded radio frequency unit configuration register; configuring the FPGA embedded radio frequency unit to the transmit / receive duplex mode, and determining the working parameters; using the FPGA embedded processor, calling the hardware abstraction layer function, and initializing multiple working parameter states at the FPGA application layer.

[0053] Specifically, based on the internal programmable logic resources of the FPGA, a first RF signal corresponding to the configuration parameters is generated in the FPGA embedded RF unit, including: using the internal programmable logic resources of the FPGA to generate a first single-tone signal through direct digital frequency synthesis; based on the first single-tone signal, configuring the phase word and frequency word corresponding to the configuration parameters in the FPGA embedded RF unit, and outputting the first RF signal corresponding to the configuration parameters.

[0054] Specifically, a first RF channel for the FPGA embedded RF unit to receive the first RF signal is established, including: connecting an RF transmit pin of the FPGA embedded RF unit to multiple RF receive pins of the FPGA embedded RF unit through a power divider, so as to obtain multiple first RF channels for the FPGA embedded RF unit to receive the first RF signal.

[0055] Specifically, the first RF signal received by the first RF channel is detected to obtain first detection data, and the first detection data is transmitted to the FPGA embedded processor, including: using the FPGA on-chip memory to perform cross-clock domain caching on the first RF signal received by the first RF channel; performing parallel-to-serial conversion on the cached first RF signal according to the corresponding RF channel to obtain a parallel-to-serial converted signal; performing fast Fourier transform on the parallel-to-serial converted signal to obtain a transformed signal; determining the signal strength and signal-to-noise ratio of the received first RF signal according to the transformed signal; determining the first detection data according to the first RF signal transmission power and the signal strength and signal-to-noise ratio of the received first RF signal; and transmitting the first detection data to the FPGA embedded processor.

[0056] Specifically, the FPGA embedded processor is used to compare the first detection data with the standard value to obtain the test result of the first RF channel, including: using the FPGA embedded processor to compare the signal strength, signal-to-noise ratio and transmission signal power of the first RF signal received by the first RF channel with the corresponding standard values ​​in the electrical parameter table; when the signal strength, signal-to-noise ratio and transmission signal power differ from the corresponding standard values ​​by no more than a preset value, it is determined that the first RF channel is operating normally; when the signal strength, signal-to-noise ratio, or transmission signal power differs from the corresponding standard value by more than a preset value, it is determined that the first RF channel is operating abnormally.

[0057] Specifically, the FPGA embedded RF unit testing method based on the universal interconnect bus provided by the present invention also includes: using an automatic testing machine to generate a second RF signal according to configuration parameters; establishing a second RF channel for the FPGA embedded RF unit to receive the second RF signal; detecting the second RF signal received by the second RF channel to obtain second detection data, and transmitting the second detection data to the FPGA embedded processor; using the FPGA embedded processor to compare the second detection data with the standard value to obtain a test result of the second RF channel; when the test results of the first RF channel and the test results of the second RF channel are both working normally, the FPGA embedded RF unit test based on the universal interconnect bus passes.

[0058] Specifically, an automatic test machine is used to generate a second radio frequency signal according to configuration parameters, including: using the automatic test machine to generate a second single-tone signal; using the automatic test machine to configure the FPGA embedded radio frequency unit according to the configuration parameters; based on the second single-tone signal, outputting the second radio frequency signal corresponding to the configuration parameters in the FPGA embedded radio frequency unit.

[0059] Specifically, a second RF channel for the FPGA embedded RF unit to receive the second RF signal is established, including: connecting the signal generator and the spectrum analyzer to the automatic test machine through the GPIB interface, connecting an RF receiving pin of the FPGA embedded RF unit to the signal generator, and connecting an RF transmitting pin of the FPGA embedded RF unit to the spectrum analyzer, to obtain the second RF channel for the FPGA embedded RF unit to receive the second RF signal.

[0060] Specifically, the second RF signal received by the second RF channel is detected to obtain second detection data, including: the automatic test machine obtains the received second RF signal through the GPIB interface, and calculates the signal strength and signal-to-noise ratio of the received second RF signal; the automatic test machine reads the spectrum analyzer through the GPIB interface to obtain the transmission power of the second RF signal; and the second detection data is determined according to the transmission power of the second RF signal and the signal strength and signal-to-noise ratio of the received second RF signal.

[0061] Example:

[0062] Taking the design of internal test software code using Verilog and C language as an example, the following is combined with Figure 1 Each step in the embodiment of the present invention is described in detail.

[0063] The FPGA embedded radio frequency unit testing method based on the universal interconnect bus of the embodiment of the present invention includes steps S1 to S6, and each step is described in detail as follows:

[0064] S1: Use the FPGA embedded processor to configure the FPGA embedded radio frequency unit according to the configuration parameters and the transmit / receive duplex mode.

[0065] S2: Based on the internal programmable logic resources of the FPGA, a first RF signal corresponding to the configuration parameters is generated in the RF unit embedded in the FPGA.

[0066] S3: Establish a first RF channel for the FPGA embedded RF unit to receive the first RF signal.

[0067] S4: Detect the first radio frequency signal received by the first radio frequency channel to obtain first detection data, and transmit the first detection data to the FPGA embedded processor.

[0068] S5: Transmit the configuration parameters, the first radio frequency signal and the first detection data through the universal interconnection bus, and use the FPGA on-chip memory for caching.

[0069] S6: Using the FPGA embedded processor, compare the first detection data with the standard value to obtain a test result of the first radio frequency channel.

[0070] In the above implementation, an FPGA chip in-chip testing method is adopted to complete signal processing inside the chip, thereby realizing an automated test of an FPGA embedded radio frequency unit based on a universal interconnection bus. No external testing equipment is required, thus saving testing costs. The method has strong versatility and can test multiple frequency points, bandwidths and other parameters by loading different configuration files. Based on FPGA internal programmable logic resources such as FPGA embedded radio frequency units and FPGA embedded processors, a universal interconnection bus is used to interact with FPGA internal data, thereby realizing pipeline processing of test signal transmission, reception and judgment, speeding up test processing speed, reducing the amount of test cache, and requiring no additional hardware design. Only the FPGA on-chip memory is used for caching to realize FPGA built-in testing without the need for external memory such as DDR.

[0071] In some specific implementations of step S1, the FPGA embedded processor is used to configure the FPGA embedded radio frequency unit according to the configuration parameters and the transmit / receive duplex mode, including: according to the configuration parameters, the FPGA embedded processor is used to write the initial value of the FPGA embedded radio frequency unit configuration register; the FPGA embedded radio frequency unit is configured to the transmit / receive duplex mode to determine the working parameters; the FPGA embedded processor is used to call the hardware abstraction layer (HAL) C language function to initialize multiple working parameter states at the FPGA application layer, so as to subsequently implement the test of different frequency points and different working parameters of the radio frequency unit. The above working parameters include key parameters such as working frequency, gain, and attenuation.

[0072] For example, the working parameters of the FPGA embedded radio unit test are: under the maximum, minimum and typical frequency points and bandwidths specified by the configuration parameters, the received signal signal-to-noise ratio of the radio unit is measured, thereby measuring the transmission attenuation range, receiving gain range, maximum working bandwidth, minimum working bandwidth, maximum working frequency, minimum working frequency, transmission signal strength, received signal signal-to-noise ratio and other radio frequency parameter indicators. When testing different frequency points or bandwidths, the test method is consistent, and only the configuration code stream of the FPGA needs to be changed to make the radio unit work in the specified working mode.

[0073] In some specific implementations of step S2, based on the internal programmable logic resources of the FPGA, a first radio frequency signal corresponding to the configuration parameters is generated in the FPGA embedded radio frequency unit, including: using the internal programmable logic resources of the FPGA to generate a first single-tone signal through direct digital frequency synthesis; based on the first single-tone signal, the phase word and frequency word corresponding to the configuration parameters are configured in the FPGA embedded radio frequency unit, and the first radio frequency signal corresponding to the configuration parameters is output. Specifically, based on direct digital frequency synthesis, a single-tone signal is generated by using digital frequency synthesis inside the FPGA, and after configuring the phase word and frequency word, a digital orthogonal intermediate frequency signal of the required frequency is output. Direct digital frequency synthesis refers to generating a series of digital signals and converting them into analog signals through a digital-to-analog converter. DDS is the abbreviation of Direct Digital Synthesizer. DDS converts a series of digital signals into analog signals through a digital / analog converter. DDS directly synthesizes the required waveform based on the concept of phase. Compared with traditional frequency synthesizers, DDS has the advantages of low cost, low power consumption, high resolution and fast conversion time.

[0074] In some specific implementations of step S3, a first RF channel for receiving a first RF signal by an embedded RF unit in the FPGA is established, including: connecting a RF transmit pin of the embedded RF unit in the FPGA to multiple RF receive pins of the embedded RF unit in the FPGA through a power divider, respectively, to obtain multiple first RF channels for the embedded RF unit in the FPGA to receive the first RF signal. For example, using an SMA (SubMiniature version A) cable, a RF transmit pin TX1 of the embedded RF unit in the FPGA is connected to multiple RF receive pins RX11, RX12, to RX1N of the embedded RF unit in the FPGA through a power divider. The one or more first RF channels established are self-transmitting and self-receiving channels of the embedded RF unit in the FPGA, which are used for testing single-tone signals inside the FPGA to realize self-transmitting and self-receiving of the embedded RF unit in the FPGA. The test of the embedded RF unit in the FPGA is realized by detecting the transceiver signal of the first RF channel.

[0075] In some specific implementations of step S4, the first RF signal received by the first RF channel is detected to obtain first detection data, and the first detection data is transmitted to the FPGA embedded processor, including: using the FPGA on-chip memory to cache the first RF signal received by the first RF channel across clock domains; performing parallel-to-serial conversion on the cached first RF signal according to the corresponding RF channel to obtain a parallel-to-serial converted signal; performing fast Fourier transformation on the parallel-to-serial converted signal to obtain a transformed signal; determining the signal strength and signal-to-noise ratio of the received first RF signal according to the transformed signal; determining the first detection data according to the first RF signal transmission power and the signal strength and signal-to-noise ratio of the received first RF signal; and transmitting the first detection data to the FPGA embedded processor. By collecting the transceiver signal parameters in step S4, that is, the first detection data, it is used as the basis for testing the FPGA embedded RF unit.

[0076] In step S5, the configuration parameters, the first RF signal and the first detection data in the above steps are transmitted through the universal interconnect bus, and the above data and related data are cached using the FPGA on-chip memory. Specifically, the basic configuration of the hardware platform is read and written using the universal interconnect bus, the RF unit parameters are configured, and the intermediate frequency digital signal is transmitted. On the FPGA embedded processor, it is determined whether the frequency point is correct, and the signal-to-noise ratio result is printed through the serial port and GPIO (General-purpose input / output).

[0077] In the prior art, the test of the FPGA embedded radio frequency unit is connected to a complex external test platform, which generates a large amount of test data. This large amount of test data depends on the processing flow of the complex external test platform. The data is transmitted between the data interfaces of different external test platforms, resulting in multiple unnecessary data conversion processes, and the converted data needs to be verified multiple times, which results in a long data processing time, resulting in many data that cannot be processed quickly in real time, and need to be cached in the memory for waiting to be called. The FPGA on-chip memory is used as a cache, with a fast processing speed, but the cache capacity is small, which cannot meet the large amount of cached data generated by the FPGA embedded radio frequency unit test in the prior art. Therefore, in the prior art, DDR is usually used as an external memory of the FPGA on-chip system to cache data. DDR (that is, DDR SDRAM, Double Data Rate Synchronous Dynamic Random Access Memory, double rate synchronous dynamic random access memory) has a large storage capacity, but as an external device, the data stored in DDR needs to be transferred to the FPGA before the test data can be interacted, which will reduce the processing speed of the test data, and the external DDR will also increase the cost of the FPGA embedded radio frequency unit test.

[0078] In step S5, based on the internal programmable logic resources of the FPGA such as the FPGA embedded radio frequency unit and the FPGA embedded processor, a universal interconnection bus is used to interact with the internal data of the FPGA, thereby avoiding multiple unnecessary data conversion processes, improving the data transmission speed, and being able to realize pipeline processing of the transmission, reception and judgment of the test signal, thereby accelerating the test processing speed, reducing the test cache amount, and requiring no additional hardware design. Only the FPGA on-chip memory is used to cache the configuration parameters, the first radio frequency signal, the first detection data and other data and their related data, thereby being able to realize FPGA built-in testing without the need for external memory such as DDR.

[0079] In some specific implementations of step S6, an FPGA embedded processor is used to compare the first detection data with the standard value to obtain a test result of the first RF channel, including: using the FPGA embedded processor to compare the signal strength, signal-to-noise ratio and transmitted signal power of the first RF signal received by the first RF channel with the corresponding standard values ​​in the electrical parameter table; when the signal strength, signal-to-noise ratio and transmitted signal power differ from the corresponding standard values ​​by no more than a preset value, it is determined that the first RF channel is operating normally; when the signal strength, signal-to-noise ratio, or transmitted signal power differs from the corresponding standard value by more than a preset value, it is determined that the first RF channel is operating abnormally.

[0080] Through step S6, the single tone signal test inside the FPGA is completed, and the self-transmission and self-reception of the radio frequency unit embedded in the FPGA is realized. The test of the radio frequency unit embedded in the FPGA is realized by detecting the transceiver signal of the first radio frequency channel.

[0081] The above steps S1 to S6 are used for FPGA internal single-tone signal testing. In actual testing, FPGA external single-tone signal testing can also be added to judge the consistency of the FPGA internal single-tone signal test results and the FPGA external single-tone signal test results. When both the FPGA internal single-tone signal test results and the FPGA external single-tone signal test results pass, it is determined that the FPGA embedded radio frequency unit test has passed.

[0082] In some specific implementations of adding FPGA external single tone signal testing, automatic processing can be achieved by designing corresponding software modules. The corresponding software module design process is as follows: Figure 2 As shown, the following steps are included:

[0083] Step 1: Based on the internal programmable logic resources of the FPGA, a radio frequency unit test stimulus generation module is developed to generate a first radio frequency signal.

[0084] Step 2: Generate a radio frequency unit configuration module and configure the radio frequency unit to a corresponding working mode to implement testing of different frequency points and different working modes of the radio frequency unit.

[0085] Step 3: Based on the internal programmable logic resources of the FPGA, develop a RF unit test response analysis module to detect the first RF signal received by the first RF channel to obtain first detection data, and transmit the first detection data to the FPGA embedded processor, or detect the second RF signal received by the second RF channel to obtain second detection data, and transmit the second detection data to the FPGA embedded processor.

[0086] Step 4: Realize data interaction between the test stimulus generation module, the RF unit configuration module, the test response analysis module and the RF unit through the universal interconnection bus inside the FPGA.

[0087] Step 5: Build the physical connection of the RF channel, complete the FPGA bit stream configuration, generate the input signal required for the test through the FPGA or external signal source, and process the RF output result through the FPGA internal test response analysis module to realize the built-in self-test of the FPGA embedded RF unit.

[0088] The data interaction of the above software modules is as follows Figure 3 As shown in the figure, RFSoC (Radio Frequency System on Chip) represents a system on chip with an FPGA embedded in the RF unit, wherein the FPGA embedded in the RF unit receives and transmits RF signals through a general interconnect bus. The configuration module is set based on the FPGA embedded processor. GPIO is a general input and output interface. The data interaction between the test stimulus generation module, the configuration module, and the test response analysis module and the RF unit is carried out through the general interconnect bus.

[0089] In some specific implementations of adding FPGA external single-tone signal testing, an embodiment of the present invention provides an FPGA embedded RF unit testing method based on a universal interconnect bus, which also includes: using an automatic testing machine to generate a second RF signal according to configuration parameters; establishing a second RF channel for the FPGA embedded RF unit to receive the second RF signal; detecting the second RF signal received by the second RF channel to obtain second detection data, and transmitting the second detection data to the FPGA embedded processor; using the FPGA embedded processor to compare the second detection data with the specification value to obtain a test result of the second RF channel; when the test results of the first RF channel and the test results of the second RF channel are both working normally, the FPGA embedded RF unit test based on the universal interconnect bus passes.

[0090] For example, Figure 4As shown, the software and hardware test platforms are built respectively. The software platform refers to the above software modules, and the hardware platform refers to the external automatic test machine. The physical connection of the RF channel is built, the FPGA code stream configuration is completed, and the GPIB control signal source generates the required input signal and external reference clock. The automatic test machine configures the FPGA through the SMAP method. The FPGA embedded processor configures the FPGA embedded RF unit and automatically establishes a connection.

[0091] Figure 4 The transmitting channel 1 and receiving channel 1 in the RF channel correspond to the second RF channel, which is used for transmitting and receiving the second RF signal of the hardware platform. The second RF signal received by the second RF channel is detected to obtain second detection data. For example, the automatic test machine reads the spectrum analyzer through the GPIB interface to obtain the second RF signal transmission power; the second detection data is determined according to the second RF signal transmission power and the signal strength and signal-to-noise ratio of the received second RF signal. The second RF channel is judged: the second detection data is compared with the standard value to obtain the test result of the second RF channel, and the function and performance of the second RF channel are judged.

[0092] Figure 4 The remaining channels in the RF channel correspond to the first RF channel, which is used for the RF signal transmission and reception of the software platform, that is, the self-transmission and self-reception of the first RF signal by the FPGA embedded RF unit. Specifically, multiple first RF channels can be formed by establishing a one-to-many pin connection. For example, a RF transmission pin TX1 of the FPGA embedded RF unit is connected to multiple RF receiving pins RX11, RX12, to RX1N of the FPGA embedded RF unit through a power divider, thereby obtaining multiple first RF channels such as TX1 to RX11, TX1 to RX12, and TX1 to RX13. Judge the first RF channel: compare the first detection data of the multiple first RF channels with the standard values ​​respectively, and obtain the test results of the multiple first RF channels.

[0093] Figure 4 In the process, the RF output result is processed by the FPGA internal test response analysis module, the judgment results of the first RF channel and the second RF channel are processed, the built-in self-test of the FPGA embedded RF unit is realized, and the test is ended.

[0094] In the above implementation scheme with an automatic test machine, the test results of the automatic test machine are compared with the test results of the FPGA embedded radio frequency unit based on the universal interconnect bus of the present invention, which can enhance the reliability of the final test results. In addition, only an automatic test machine is added, which reduces the number of external test platforms for testing FPGA embedded radio frequency units in the prior art, and simplifies the complex external test platforms in the prior art.

[0095] In some specific implementations, an automatic test machine is used to generate a second radio frequency signal according to configuration parameters, including: using the automatic test machine to generate a second single-tone signal; using the automatic test machine to configure the FPGA embedded radio frequency unit according to the configuration parameters; based on the second single-tone signal, the FPGA embedded radio frequency unit outputs the second radio frequency signal corresponding to the configuration parameters. For example, the automatic test machine configures the FPGA through the SMAP (Service Management Access Point) method; after successfully configuring the FPGA code stream, the FPGA embedded processor is started, and the FPGA embedded radio frequency unit is automatically configured, so that the FPGA embedded radio frequency unit works in a preset working state.

[0096] In some specific implementations, a second RF channel for receiving a second RF signal by an FPGA embedded RF unit is established, including: connecting a signal generator and a spectrum analyzer to an automatic test machine via a GPIB (General-Purpose Interface Bus) interface, connecting a RF receiving pin of the FPGA embedded RF unit to the signal generator, and connecting a RF transmitting pin of the FPGA embedded RF unit to the spectrum analyzer, so as to obtain a second RF channel for the FPGA embedded RF unit to receive the second RF signal. For example, an SMA cable is used to connect an RF receiving pin RX2 of the FPGA embedded RF unit to an external signal generator, and an SMA cable is used to connect an RF transmitting pin TX2 of the FPGA embedded RF unit to an external spectrum analyzer, and the signal generator and the spectrum analyzer are connected to the automatic test machine via a GPIB interface.

[0097] The general interconnect bus, GPIO and GPIB mentioned above are different. The general interconnect bus is used to interconnect signals within the FPGA. GPIO is a general IO interface. GPIB is an interface for an ATE (Automatic Test Equipment) machine. GPIB controls the signal source to generate the required input signals and external reference clocks.

[0098] In some specific implementations, the second RF signal received by the second RF channel is detected to obtain the second detection data, including: the automatic test machine obtains the received second RF signal through the GPIB interface, and calculates the signal strength and signal-to-noise ratio of the received second RF signal; the automatic test machine reads the spectrum analyzer through the GPIB interface to obtain the second RF signal transmission power; and the second detection data is determined according to the second RF signal transmission power and the signal strength and signal-to-noise ratio of the received second RF signal. For example, the automatic test machine captures the digital interface data, calculates the signal strength and received signal-to-noise ratio of the received second RF signal; the automatic test machine reads the spectrum analyzer data through the GPIB to obtain the transmission power of the second RF signal. The second detection data such as the second RF signal transmission power, the signal strength and signal-to-noise ratio of the received second RF signal are transmitted to the FPGA embedded processor. The specification value in the electrical parameter table is used as the specification value, and the second detection data is compared with the specification value using the FPGA embedded processor to obtain the test result of the second RF channel, and the function and performance of the second RF channel are determined. When both the test result of the second RF channel and the test result of the first RF channel pass, that is, when both the test result of the FPGA internal single-tone signal and the test result of the FPGA external single-tone signal pass, it is determined that the FPGA embedded RF unit test passes.

Claims

1. A method for testing an FPGA embedded radio frequency unit based on a universal interconnect bus, characterized in that: The steps include: Step 1: Use the FPGA embedded processor to configure the FPGA embedded radio unit according to the configuration parameters and transmit / receive duplex mode; Step 2: Based on the internal programmable logic resources of the FPGA, the RF unit embedded in the FPGA generates a first RF signal corresponding to the configuration parameters; Step 3: Establish a first RF channel for the FPGA embedded RF unit to receive the first RF signal; Step 4: Detect the first radio frequency signal received by the first radio frequency channel to obtain first detection data, and transmit the first detection data to the FPGA embedded processor; Step 5: Transmit the configuration parameters, the first radio frequency signal and the first detection data through the universal interconnection bus, and use the FPGA on-chip memory for caching; Using the FPGA embedded processor, the first detection data is compared with the standard value to obtain the test result of the first radio frequency channel.

2. The method for testing an FPGA embedded radio frequency unit based on a universal interconnect bus according to claim 1, characterized in that: The step 1 is specifically as follows: Step 1-1: Use the FPGA embedded processor to write the initial value of the FPGA embedded radio unit configuration register according to the configuration parameters; Step 1-2: Configure the FPGA embedded radio unit to transmit and receive duplex mode and determine the operating parameters; Step 1-3: Use the FPGA embedded processor to call the hardware abstraction layer function and initialize multiple working parameter states at the FPGA application layer.

3. The method for testing an FPGA embedded radio frequency unit based on a universal interconnect bus according to claim 2, characterized in that: The step 2 is specifically as follows: Step 2-1: Generate a first single tone signal by direct digital frequency synthesis using the internal programmable logic resources of the FPGA; Step 2-2: Based on the first single-tone signal, configure the phase word and frequency word corresponding to the configuration parameters in the FPGA embedded radio frequency unit, and output the first radio frequency signal corresponding to the configuration parameters.

4. The method for testing an FPGA embedded radio frequency unit based on a universal interconnect bus according to claim 3, characterized in that: The step 3 is specifically as follows: A radio frequency transmitting pin of the radio frequency unit embedded in the FPGA is connected to multiple radio frequency receiving pins of the radio frequency unit embedded in the FPGA through a power divider to obtain multiple first radio frequency channels for the radio frequency unit embedded in the FPGA to receive the first radio frequency signal.

5. The method for testing an FPGA embedded radio frequency unit based on a universal interconnect bus according to claim 4, characterized in that: The step 4 is specifically as follows: Step 4-1: Use the FPGA on-chip memory to cache the first RF signal received by the first RF channel across clock domains; Step 4-2: performing parallel-to-serial conversion on the cached first RF signal according to the corresponding RF channel to obtain a parallel-to-serial converted signal; Step 4-3: Perform fast Fourier transform on the parallel-to-serial converted signal to obtain a transformed signal; Step 4-4: Determine the signal strength and signal-to-noise ratio of the received first radio frequency signal according to the transformed signal; Step 4-5: determining first detection data according to the transmission power of the first radio frequency signal and the signal strength and signal-to-noise ratio of the received first radio frequency signal; Step 4-6: Transmit the first detection data to the FPGA embedded processor.

6. The method for testing an FPGA embedded radio frequency unit based on a universal interconnect bus according to claim 5, characterized in that: The step 5 is specifically as follows: Step 5-1: Using the FPGA embedded processor, compare the signal strength, signal-to-noise ratio, and transmit signal power of the first RF signal received by the first RF channel with the corresponding specification values ​​in the electrical parameter table; Step 5-2: When the signal strength, signal-to-noise ratio, and transmitted signal power all differ from the corresponding standard values ​​by no more than a preset value, it is determined that the first RF channel is operating normally; when the signal strength or signal-to-noise ratio or transmitted signal power differs from the corresponding standard values ​​by more than a preset value, it is determined that the first RF channel is operating abnormally.

7. The method for testing an FPGA embedded radio frequency unit based on a universal interconnect bus according to claim 6, characterized in that: The FPGA embedded radio frequency unit testing method further includes: Using an automatic test machine, generating a second radio frequency signal according to configuration parameters; Establishing a second radio frequency channel for the FPGA embedded radio frequency unit to receive a second radio frequency signal; Detecting a second radio frequency signal received by the second radio frequency channel to obtain second detection data, and transmitting the second detection data to the FPGA embedded processor; Using the FPGA embedded processor, the second detection data is compared with the standard value to obtain the test result of the second radio frequency channel; When the test results of the first RF channel and the test results of the second RF channel are both normal, the test of the FPGA embedded RF unit based on the universal interconnection bus passes.

8. The method for testing an FPGA embedded radio frequency unit based on a universal interconnect bus according to claim 7, characterized in that: The method of using the automatic test machine to generate the second radio frequency signal according to the configuration parameters includes: Using an automatic test machine to generate a second single tone signal; Use an automatic test machine to configure the FPGA embedded radio frequency unit according to the configuration parameters; Based on the second single tone signal, the FPGA embedded radio frequency unit outputs a second radio frequency signal corresponding to the configuration parameter.

9. The method for testing an FPGA embedded radio frequency unit based on a universal interconnect bus according to claim 8, characterized in that: The method of establishing a second RF channel for the FPGA embedded RF unit to receive the second RF signal includes: connecting the signal generator and the spectrum analyzer to the automatic test machine through the GPIB interface, connecting an RF receiving pin of the FPGA embedded RF unit to the signal generator, and connecting an RF transmitting pin of the FPGA embedded RF unit to the spectrum analyzer, so as to obtain the second RF channel for the FPGA embedded RF unit to receive the second RF signal.

10. The method for testing an FPGA embedded radio frequency unit based on a universal interconnect bus according to claim 9, characterized in that: The detecting of the second radio frequency signal received by the second radio frequency channel to obtain the second detection data includes: the automatic test machine obtains the received second radio frequency signal through the GPIB interface, and calculates the signal strength and signal-to-noise ratio of the received second radio frequency signal; the automatic test machine reads the spectrum analyzer through the GPIB interface to obtain the transmission power of the second radio frequency signal; and determines the second detection data according to the transmission power of the second radio frequency signal and the signal strength and signal-to-noise ratio of the received second radio frequency signal.

Images