Method for reducing multi-point progressive blocking in network-on-chip (NoC) based on priority scheduling

Abstract

The invention belongs to the field of real-time embedded operating systems, and particularly relates to a method for reducing multipoint progressive blocking in a network-on-chip (NoC) based on priority scheduling, which comprises a brand new router structure and a working mode thereof. The utilization rate of the virtual channel of each port is improved by adopting the shared virtual channel; recording whether there is no buffered data in the current data stream by adding a buffer record table; using a variable virtual channel pointer to distinguish the buffered data stream from the data stream passing through the virtual channel; according to the method, the probability of occurrence of a multipoint progressive blocking phenomenon in the whole network-on-chip is reduced, so that the network-on-chip can work by using a safer time limit.

Description

Technical Field

[0001] The invention belongs to the field of real-time embedded operating systems, and in particular relates to a technical solution for reducing the occurrence of multi-point progressive blocking in a network on chip (NoC) based on priority scheduling. Background Art

[0002] Network-on-Chip (NoC) is a communication architecture for multi-core systems on a chip (SoC), which solves the bottleneck problem of traditional bus architecture when processing large amounts of parallel data transmission. NoC connects multiple cores, memories, peripherals and other integrated modules in a network, and uses routers and links to transmit data packets, thereby improving the scalability of the system and data transmission efficiency.

[0003] In high-performance computing scenarios, the performance of NoC can directly affect the execution efficiency of computing tasks. NoC can reduce communication delays and optimize data transmission paths, thereby improving the system's throughput and overall computing performance. In deep learning accelerators, its role is not only communication, but also involves data allocation, task scheduling, and cache management. Efficient NoC design can greatly increase training and inference speeds and reduce power consumption, making real-time processing of large-scale neural network models possible. It can be concluded that NoC is not only the core technology for solving on-chip multi-core communication problems, but also can significantly improve the scalability and performance of the system.

[0004] Currently, wormhole router is a common design method for network-on-chip (NoC) routers, which is used to achieve efficient transmission of data packets in NoC. Wormhole routing is a flow control mechanism that divides data packets into smaller transmission units (flits) and transmits these flits one by one, reducing network latency and the need for buffers. It uses virtual channels to avoid chain blocking caused by blocking propagation and can effectively prevent deadlock.

[0005] However, in networks on a chip (NoC) using wormhole routers, the multi-point progressive blocking problem is a common performance bottleneck. This phenomenon occurs when the network load is high and multiple packets compete for resources, causing the congestion in the network to gradually accumulate and spread. The problems that the multi-point progressive blocking problem will bring to the network are: 1. Increased latency: Due to the simultaneous congestion on multiple nodes, the transmission time of data packets in the network increases significantly, resulting in higher communication delays. 2. Decreased throughput: As congestion accumulates, the effective throughput of the system will decrease, the bandwidth utilization of the network will decrease, and the overall performance will be affected. 3. Formation of local hot spots: Some links and nodes are overloaded, causing local hot spots, further exacerbating the congestion problem.

[0006] Although there are many studies on the optimization of on-chip network transmission time, few studies have been conducted to reduce the probability of multi-point progressive blocking by starting from the structure of the router itself. In addition, in actual environments, on-chip networks composed of wormhole routers have problems with routing algorithms, deadlock blocking, and excessive area. Therefore, it is an urgent problem to optimize the transmission limit of on-chip networks by redesigning the structure of routers. Summary of the invention

[0007] To solve the above problems, the present invention proposes a method for reducing the occurrence of multi-point progressive blocking in a priority-scheduling-based network on chip.

[0008] In view of the difficulty of solving the above problems in the prior art, the present invention proposes a method for reducing the probability of multi-point progressive blocking by using a network-on-chip structure composed of a shared buffer router. By sharing the virtual channels of the router's input ports and writing the cached Flits into different types of virtual channels in a differentiated manner, the present invention reduces the possibility of multi-point progressive blocking caused by data flow Flits and ensures the security of the estimated time limit of the network-on-chip.

[0009] The technology adopted by the present invention comprises the following steps:

[0010] Step 1, reconstruct the router structure: create a cache table and record the cache information. Abandon the original head flit to determine the transmission mode of the output port, use the cache table to record the output port of the head flit, connect the ports of the same priority in the router with an internal bus, form a shared buffer structure based on priority, and add the record fields of the input port and output port for each priority flow number. Inside the shared buffer, use the dynamic pointer method to distinguish the Flit buffered in the virtual channel of the router input port and the Flit passing through.

[0011] Step 2, when arbitration is lost and cache is performed: a clockwise cache algorithm is used and dynamic pointers are used for caching. When blocking is about to occur, the Flits that have not been arbitrated are stored in the VCs of different input ports of the same router in a clockwise order. It should be noted that after the pointer of the priority virtual channel corresponding to the current port points to the maximum value, the Flits are stored in a clockwise order to other ports and the corresponding dynamic pointers are modified. When storing, the endpoint of the corresponding Packet and its priority need to be recorded in the shared cache record table, and the direction of the dynamic pointer needs to be changed to distinguish the Flits.

[0012] Step 3, when arbitration is obtained and the transmission link is transmitted: a clockwise search algorithm is used to refer to the cache record table for routing transmission. After obtaining link arbitration, the Flit is further routed according to the cache table. It should be noted that the retrieval algorithm is used to route the Flit after the local port is output. The dynamic pointer of the local port changes forward, and the dynamic pointer of other ports of the router changes backward.

[0013] The beneficial effect of the present invention is that, in view of the situation of multi-point progressive blocking, starting from the structure and working mechanism of the router, the area that can be buffered for the flow of each priority is expanded to reduce the situation where blocking may occur. In addition, by expanding the bufferable range, the utilization rate of the router virtual channel can be improved, and by adding a cache table, the head Flit no longer carries the path information, and the path can be directly searched by priority. The present invention has the advantages of low cost and easy implementation, and has good scalability and practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The working principle diagram of the router of the present invention;

[0015] Figure 2 It is the principle diagram of the virtual channel dynamic pointer of the present invention;

[0016] Figure 3 It is a structural diagram of a router of the present invention;

[0017] Figure 4 It is a flow chart of the present invention based on the shared buffer router transmission Flit; DETAILED DESCRIPTION

[0018] The present invention will be further described below in conjunction with the accompanying drawings and embodiments:

[0019] The present invention aims at NoC, modifies the router structure, redesigns its working mechanism and logically expands the available buffer, thereby reducing the probability of multi-point progressive blocking and improving the security of information transmission in the on-chip network.

[0020] Figure 1The working principle diagram of the router of the present invention is as follows: first, each port of the router is connected to the cache table through a control bus. In order to ensure that the Flit cached to other ports can be correctly sent to the correct port, the cache table needs to record the starting point and end point of the current priority Flit; then, when the Flit needs to be buffered, it is stored in the virtual channel of the corresponding priority of the corresponding input port in a clockwise order; finally, when the buffered Flit needs to be output, the dynamic pointer of the input port is also retrieved in the clockwise direction to find the corresponding Flit of its cache, and then the cache table information is retrieved, and the end point of the data flow record of the corresponding priority is used as the basis, and the routing algorithm is used to output to the corresponding output port.

[0021] Figure 2 The structure diagram of the reconstructed router of the present invention mainly includes two reconstruction principles: ① High utilization principle: In order to give full play to the utilization of the virtual channels of each port, the input buffers of each port are connected together through a control bus; ② Buffered data and passed data separation principle: Because the buffered Flit after reconstruction will occupy the buffers of other input ports, dynamic pointers are assigned to the virtual channels of each priority level to distinguish the buffered data from the data flowing through the port itself.

[0022] Figure 4 This is a flow chart of a strategy for reducing multi-point progressive blocking under the condition of a reconstructed router of the present invention. When two flows with different priorities compete for the output port of the same router, the convenience of the head Flit carrying path information will be sacrificed. By adding a cache table to record cache and path information, the multi-point progressive blocking problem is preferentially reduced. The routing process of a flow is analyzed starting from step 101. The specific steps are as follows:

[0023] In step 102, when the head Flit of each flow enters the corresponding router, the corresponding information of the cache table is updated, including its output port and end point coordinates.

[0024] In step 103, it is determined whether the flows with different priorities compete for the link. If so, step 105 is performed; if not, step 104 is performed.

[0025] In step 105, it is determined whether the buffer corresponding to the low priority is full. If not, step 106 is executed. If the buffer is full, step 107 is executed. After executing step 106, step 105 needs to be re-determined.

[0026] In step 104, the data flow obtains information about its path and whether to cache it to other ports according to its priority information. Then, step 108 is executed.

[0027] In step 108, it is necessary to determine whether the current information flow has a Flit cached to other ports. If so, step 109 is executed, otherwise, step 110 is executed.

[0028] In step 109, the flits stored in the remaining ports need to be output in sequence, and the information in the cache table needs to be updated after each output of the flits, until there are no buffered flits in the remaining ports.

[0029] In step 110, the corresponding Flit finds the corresponding output port according to the XY route, thereby passing through the router smoothly.

[0030] Step 111 ends, and the buffers of four different input ports are connected to form a shared buffer by updating the cache table, thereby expanding the process of blocking the transmission of other routers upwards when the low priority flow is cached due to competition because the buffer is full. It can be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1.S1: A method for reducing the occurrence of multi-point progressive blocking in a priority-based scheduling network on chip (NoC), characterized in that: The following steps are involved: Step 1: Reconstruct the router structure: share virtual channels, create a cache table, and record cache information. Use the cache table to record the output port of the head Flit. Inside the virtual channel, use the dynamic pointer method to distinguish the Flit buffered in the virtual channel of the router input port and the Flit passed. Step 2: When arbitration is lost and cache is performed: a clockwise cache algorithm is used and dynamic pointers are used for caching. When blocking is about to occur, the Flits that have not been arbitrated are stored in the VCs of different input ports of the same router in a clockwise order. When storing, the destination of the corresponding Packet and its priority need to be recorded in the shared cache record table. Step 3, when arbitration is obtained and the transmission link is transmitted: a clockwise search algorithm is used to refer to the cache record table for routing transmission. After obtaining link arbitration, the Flit is further routed according to the cache table, and the dynamic pointer of the local port changes forward, and the dynamic pointer of other ports of the router changes backward. S2: According to a method for reducing the occurrence of multi-point progressive blocking in a priority-based scheduling network on chip according to claim 1, characterized in that: Abandon the original head flit to determine the transmission mode of the output port, and use the cache table to record the transmission destination of the data stream. In addition, the cache table needs to record whether it is cached to other ports to provide a basis for outputting Flit. The sum of the pointer to the buffered flit and the pointer to the passed flit needs to be reserved in the virtual channel to reserve a space to prevent deadlock and blocking. S3: A method for reducing multi-point progressive blocking in a priority-based scheduling network on a chip according to claim 1, characterized in that: In step 2, the buffer of the corresponding priority flow is expanded based on the shared cache table without increasing the physical area of ​​the router, so as to maximize the utilization rate of each input port of the router. Specifically, the following steps are included: S31: Streams of different priorities need to be stored in a cache table according to the priority, starting point, end point, and cache format; S32: According to the contention situation, the low-priority streams will begin to be cached in the virtual channel buffers of the corresponding priorities of the remaining input ports, and the cache field of the shared cache table needs to be modified. The cache direction is stored in a clockwise direction starting from the current input port. S4: A method for reducing multi-point progressive blocking in a priority-based scheduling network on a chip according to claim 1, characterized in that: In step 2, a dynamic pointer is added to distinguish between the Flits cached in the same virtual channel and the Flits flowing through. In order to prevent a deadlock caused by a single type of Flit filling the entire buffer, the variable pointer needs to be controlled to point to a position where the buffer size minus 1 is the maximum. The specific steps include: S41: When link competition occurs, the low-priority flow needs to modify the cache table's cache information, and then cache Flit to the virtual channel of the corresponding port. S42: When the virtual channel of the corresponding port is full of Flits, it starts to be stored in the corresponding priority virtual channel caches of the remaining ports in a clockwise direction. Each time a Flit is stored, the pointer indicating the cache size needs to be dynamically changed so that it always points to the next position of the Flit to be cached. Thus, a shared buffer connecting various input ports is formed. S5: A method for reducing multi-point progressive blocking in a priority-based scheduling network on a chip according to claim 1, characterized in that: In step 3, when link contention does not exist, Flits are outputted again in a clockwise order through the cache table information, and the cache pointer and the buffer table need to be modified at the same time.

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