Silicon carbide super-junction planar gate transverse MOS device and manufacturing method thereof

Abstract

The invention relates to a silicon carbide super-junction planar gate transverse MOS device and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The device sequentially comprises a substrate and an epitaxial layer from bottom to top, a drain electrode region A and a source electrode region A are arranged on the two sides of the epitaxial layer respectively, drain electrode metal and source electrode metal are arranged in the drain electrode region A and the source electrode region A respectively, a p column region is arranged in the epitaxial layer, a p well region is arranged in the p column region, a p + region is arranged in the p well region, and a p + region is arranged in the p + region. A drain region B and a source region B are symmetrically arranged on the adjacent sides of the p + region, a gate oxide layer is arranged in the middle of the epitaxial layer, gate polycrystalline silicon is arranged on the upper side of the gate oxide layer, dielectric layers are arranged on the peripheral side of the gate polycrystalline silicon and the upper side of the p column region, and top metal is arranged between the dielectric layers and on the top side of the source metal and the top side of the drain metal. According to the invention, the doping concentration of the drift region can be improved while the withstand voltage of the device is ensured, and higher withstand voltage and lower on resistance of the device are realized.

Description

Technical Field

[0001] The invention relates to a silicon carbide superjunction planar gate lateral MOS device and a manufacturing method thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] SiC is particularly suitable for the manufacture of high breakdown voltage, high temperature and even high power electronic devices due to its physical properties such as large bandgap, good thermal conductivity, high critical breakdown electric field strength, and high electron saturation drift velocity, and is gradually emerging in the field of power electronic device applications. Based on this, SiC metal-oxide semiconductor field effect transistor (MOSFET) devices have the advantages of high breakdown voltage, high switching speed, low on-resistance and good high temperature radiation resistance, and occupy an increasingly important position in the application of new generation power electronic devices.

[0003] Devices made of silicon carbide are widely used in motor drives, switching power supplies and various power conversions, and are particularly suitable for high-power, high-efficiency applications. The working principle of traditional MOSFET is to control the switch through the device by controlling the gate potential of the semiconductor device, and to achieve high voltage tolerance through the built-in drift region. High withstand voltage requires a low concentration drift region, and too low impurity concentration in the drift region will lead to an increase in the specific on-resistance and thus increase the conduction loss of the device. Therefore, high breakdown voltage and low on-resistance are a pair of contradictory parameters. Superjunction structure is an effective technical solution to the above-mentioned problems, but superjunction structure is rarely used in lateral devices; restricted by the properties of silicon carbide, the potential advantages of silicon carbide in manufacturing power devices have not been fully realized, and for this reason, the present invention is proposed. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides a silicon carbide superjunction planar gate lateral MOS device, which can ensure the voltage resistance of the device while increasing the doping concentration in the drift region, thereby achieving higher voltage resistance and lower on-resistance of the device.

[0005] The present invention also provides a method for manufacturing the above-mentioned silicon carbide superjunction planar gate lateral MOS device.

[0006] The technical solution of the present invention is as follows: A silicon carbide superjunction planar gate lateral MOS device includes a substrate and an epitaxial layer from bottom to top, a drain region A and a source region A are respectively arranged on both sides of the epitaxial layer, a drain metal and a source metal are respectively arranged in the drain region A and the source region A, a p column region is arranged in the epitaxial layer, a p well region is arranged in the p well region, a drain region B and a source region B are symmetrically arranged on the adjacent sides of the p + region, a gate oxide layer is arranged in the middle of the epitaxial layer, a gate polysilicon is arranged on the upper side of the gate oxide layer, a dielectric layer is arranged on the peripheral side of the gate polysilicon and on the upper side of the p column region, the source metal, the drain metal and the gate polysilicon are isolated, and a top metal is arranged between the dielectric layers, the top side of the source metal and the top side of the drain metal. The source metal extends out of the source region A to cover part of the p + region, and the drain metal only covers the drain region A completely.

[0007] Preferably, according to the present invention, the substrate is a 4-degree tilted silicon carbide semi-insulating substrate with a resistivity of ≥105 mΩ·cm; The epitaxial layer is lightly doped with n-type, and the doping concentration is 1×10 16 -8×10 16 cm -3 .

[0008] According to the preferred embodiment of the present invention, the ions injected into the p column region are aluminum ions with a doping concentration of 1×10 16 -8×10 16 cm -3 , thus ensuring good voltage resistance. When the operating voltage is 1200V, the thickness of the p-column area is 1-1.5μm.

[0009] According to the preferred embodiment of the present invention, the depth of the p-well region is 0.3-0.5 μm, and the implanted ions in the p-well region are aluminum ions. In order to ensure that the device does not break down prematurely, the doping concentration of the p-well region is 1×10 17 -4×10 17 cm -3 .

[0010] According to the preferred embodiment of the present invention, the implanted ions in the p+ region are aluminum ions. In order to ensure good ohmic contact, the concentration of aluminum ions is greater than 1×10 18 cm -3 .

[0011] According to the preferred embodiment of the present invention, the implanted ions in the drain region A, the source region A, the drain region B and the source region B are nitrogen ions, and the nitrogen ion concentration is greater than 1×10 19 cm -3 .

[0012] The manufacturing method of the above-mentioned silicon carbide superjunction planar gate lateral MOS device comprises the following steps: (1) growing an epitaxial layer on a substrate; (2) forming a first hard mask layer on the upper side of the epitaxial layer, etching the first hard mask layer using a mask to expose a window for ion implantation in the p-column region, and performing ion implantation to form the p-column region; (3) removing the first hard mask layer, forming a second hard mask layer, etching the second hard mask layer using a mask to expose a window for ion implantation in the p-well region, and performing ion implantation to form a p-well region; (4) removing the second hard mask layer, forming a third hard mask layer, performing p-type implantation, and forming a p+ region; (5) removing the third hard mask layer on the surface, forming a fourth hard mask layer, and forming a groove by dry plasma etching; (6) removing the fourth hard mask layer, forming a fifth hard mask layer, etching an implantation window using a mask, performing n-type implantation, and forming a drain region A, a source region A, a drain region B, and a source region B; (7) removing the fifth hard mask layer, depositing a cap layer, annealing in an inert gas atmosphere to activate the implanted ions, and removing the cap layer after the annealing is completed; (8) Perform gate oxidation to form a gate oxide layer, deposit gate polysilicon, and then make a dielectric layer. Make source metal and drain metal in the drain region A and the source region A, sputter the top metal and anneal, and the device is completed.

[0013] Preferably, according to the present invention, the first hard mask layer, the second hard mask layer, the third hard mask layer, the fourth hard mask layer and the fifth hard mask layer are made of the same material, and the material composition is one of the following combinations: a. From bottom to top: ion implantation barrier layer (e.g. silicon dioxide layer), oxide layer (e.g. silicon dioxide); b. From bottom to top: ion implantation barrier layer (such as silicon dioxide layer) and polysilicon layer; c. From bottom to top: ion implantation barrier layer (e.g. silicon dioxide layer), polysilicon layer, metal layer (e.g. nickel, titanium, gold, copper, chromium, aluminum); d. From bottom to top: ion implantation barrier layer (eg, silicon dioxide layer), polysilicon layer, oxide layer (eg, silicon dioxide layer).

[0014] The beneficial effects of the present invention are: The present invention uses a 4-degree tilted silicon carbide semi-insulating substrate, which has the advantages of low cost and no need for a buffer layer compared to the commonly used n-type substrate; compared to the traditional lateral device structure, the electric field distribution in the super junction region is more uniform, avoiding premature breakdown due to excessive concentration of the electric field, and the super junction structure maintains a low on-resistance while increasing the breakdown voltage of the device, thereby enhancing the device's withstand voltage capability; and the process steps are simple, saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a cross-sectional schematic diagram of the present invention; Figure 2 This is a schematic diagram of the product structure of step (1) of the present invention; Figure 3 This is a schematic diagram of the product structure of step (2) of the present invention; Figure 4 This is a schematic diagram of the product structure of step (3) of the present invention; Figure 5 This is a schematic diagram of the product structure of step (4) of the present invention; Figure 6 This is a schematic diagram of the product structure of step (5) of the present invention; Figure 7 This is a schematic diagram of the product structure of step (6) of the present invention; Among them: 1. substrate; 2. epitaxial layer; 3. p-column region; 4. p-well region; 5. p+ region; 6. source region A; 7. drain region A; 8. gate oxide layer; 9. gate polysilicon; 10. dielectric layer; 11. source metal; 12. top metal; 13. source region B; 14. drain region B; 15. drain metal. DETAILED DESCRIPTION

[0016] The present invention will be further described below by way of embodiments in conjunction with the accompanying drawings, but is not limited thereto.

[0017] Embodiment 1: like Figure 1 As shown, this embodiment provides a silicon carbide superjunction planar gate lateral MOS device, which includes a substrate 1 and an epitaxial layer 2 from bottom to top, wherein a drain region A7 and a source region A6 are respectively arranged on both sides of the epitaxial layer 2, and a drain metal 15 and a source metal 11 are respectively arranged in the drain region A7 and the source region A6, a p-column region 3 is arranged in the epitaxial layer 2, a p-well region 4 is arranged in the p-column region 3, a p+ region 5 is arranged in the p-well region 4, and a drain region B14 and a source region B13 are symmetrically arranged in the p-well region 4 adjacent to the p+ region 5, a gate oxide layer 8 is arranged in the middle of the epitaxial layer 2, a gate polysilicon 9 is arranged on the upper side of the gate oxide layer 8, a dielectric layer 10 is arranged around the gate polysilicon 9 and on the upper side of the p-column region 3, the source metal 11, the drain metal 15 and the gate polysilicon 9 are isolated, and a top metal 12 is arranged between the dielectric layers 10 and on the top side of the source metal 11 and the drain metal 15. The source metal 11 extends out of the source region A6 to cover a portion of the p+ region 5 , and the drain metal 15 only covers the entire drain region A7 .

[0018] Substrate 1 is a 4-degree tilted silicon carbide semi-insulating substrate with a resistivity of ≥105 mΩ·cm; Epitaxial layer 2 is lightly doped with n-type, with a doping concentration of 1×10 16 -8×10 16 cm -3 .

[0019] The ions injected into the p column region 3 are aluminum ions with a doping concentration of 1×10 16 -8×10 16 cm -3 , thereby ensuring good withstand voltage. When the operating voltage is 1200V, the thickness of the p-column region 3 is 1-1.5μm.

[0020] The depth of the p-well region 4 is 0.3-0.5 μm. The implanted ions in the p-well region 4 are aluminum ions. In order to ensure that the device does not break down prematurely, the doping concentration of the p-well region 4 is 1×10 17 -4×10 17 cm -3 .

[0021] The implanted ions in the p+ region 5 are aluminum ions. To ensure good ohmic contact, the concentration of aluminum ions is greater than 1×10 18 cm -3 .

[0022] The implanted ions in the drain region A7, the source region A6, the drain region B14, and the source region B13 are nitrogen ions, and the nitrogen ion concentration is greater than 1×10 19 cm -3 .

[0023] The manufacturing method of the above-mentioned silicon carbide superjunction planar gate lateral MOS device comprises the following steps: (1) Grow an epitaxial layer 2 on a substrate 1, such as Figure 2 As shown; (2) A first hard mask layer is formed on the upper side of the epitaxial layer 2, and the first hard mask layer is etched using a mask to expose a window for ion implantation in the p-column region, and ion implantation is performed to form a p-column region 3, such as Figure 3 As shown; (3) removing the first hard mask layer, forming a second hard mask layer, etching the second hard mask layer using a mask to expose a window for ion implantation in the p-well region, and performing ion implantation to form a p-well region 4, such as Figure 4 As shown; (4) Remove the second hard mask layer, make a third hard mask layer, perform p-type implantation, and make a p+ region 5, such as Figure 5 As shown; (5) Remove the third hard mask layer on the surface, make a fourth hard mask layer, and form a groove by dry plasma etching, such as Figure 6 As shown; (6) Remove the fourth hard mask layer, form a fifth hard mask layer, use the mask to etch the implantation window, perform n-type implantation, and form the drain region A7, the source region A6, the drain region B14, and the source region B13, as shown in FIG. Figure 7 As shown; (7) removing the fifth hard mask layer, depositing a cap layer, annealing in an inert gas atmosphere to activate the implanted ions, and removing the cap layer after the annealing is completed; (8) Gate oxidation is performed to form a gate oxide layer 8, and gate polysilicon 9 is deposited. Then, a dielectric layer 10 is made, and source metal 11 and drain metal 15 are made in the drain region A7 and the source region A6. The top metal 12 is sputtered and annealed, and the device is completed.

[0024] The first hard mask layer, the second hard mask layer, the third hard mask layer, the fourth hard mask layer and the fifth hard mask layer are made of the same material, which is a silicon dioxide layer and a polysilicon layer from bottom to top.

[0025] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A silicon carbide superjunction planar gate lateral MOS device, characterized in that: From bottom to top, it includes a substrate and an epitaxial layer, a drain region A and a source region A are respectively arranged on both sides of the epitaxial layer, a drain metal and a source metal are respectively arranged in the drain region A and the source region A, a p-column region is arranged in the epitaxial layer, a p-well region is arranged in the p-column region, a p+ region is arranged in the p-well region, a drain region B and a source region B are symmetrically arranged on the adjacent sides of the p+ region, a gate oxide layer is arranged in the middle of the epitaxial layer, a gate polysilicon is arranged on the upper side of the gate oxide layer, a dielectric layer is arranged on the surrounding side of the gate polysilicon and on the upper side of the p-column region, and a top metal is arranged between the dielectric layers and on the top sides of the source metal and the drain metal.

2. The silicon carbide superjunction planar gate lateral MOS device according to claim 1, characterized in that: The substrate is a 4-degree tilted silicon carbide semi-insulating substrate with a resistivity of ≥105mΩ·cm; The epitaxial layer is lightly doped with n-type, and the doping concentration is 1×10 16 -8×10 16 cm -3 .

3. The silicon carbide superjunction planar gate lateral MOS device according to claim 2, characterized in that: The ions injected into the p-column region are aluminum ions with a doping concentration of 1×10 16 -8×10 16 cm -3 , when the operating voltage is 1200V, the thickness of the p-column region is 1-1.5μm.

4. The silicon carbide superjunction planar gate lateral MOS device according to claim 3, characterized in that: The depth of the p-well region is 0.3-0.5 μm, the implanted ions in the p-well region are aluminum ions, and the doping concentration in the p-well region is 1×10 17 -4×10 17 cm -3 .

5. The silicon carbide superjunction planar gate lateral MOS device according to claim 4, characterized in that: The implanted ions in the p+ region are aluminum ions, and the concentration of aluminum ions is greater than 1×10 18 cm -3 .

6. The silicon carbide superjunction planar gate lateral MOS device according to claim 5, characterized in that: The implanted ions in the drain region A, the source region A, the drain region B, and the source region B are nitrogen ions, and the nitrogen ion concentration is greater than 1×10 19 cm -3 .

7. The method for manufacturing a silicon carbide superjunction planar gate lateral MOS device according to claim 6, characterized in that: Here are the steps: (1) growing an epitaxial layer on a substrate; (2) forming a first hard mask layer on the upper side of the epitaxial layer, etching the first hard mask layer using a mask to expose a window for ion implantation in the p-column region, and performing ion implantation to form the p-column region; (3) removing the first hard mask layer, forming a second hard mask layer, etching the second hard mask layer using a mask to expose a window for ion implantation in the p-well region, and performing ion implantation to form a p-well region; (4) removing the second hard mask layer, forming a third hard mask layer, performing p-type implantation, and forming a p+ region; (5) removing the third hard mask layer on the surface, forming a fourth hard mask layer, and forming a groove by dry plasma etching; (6) removing the fourth hard mask layer, forming a fifth hard mask layer, etching an implantation window using a mask, performing n-type implantation, and forming a drain region A, a source region A, a drain region B, and a source region B; (7) removing the fifth hard mask layer, depositing a cap layer, annealing in an inert gas atmosphere to activate the implanted ions, and removing the cap layer after the annealing is completed; (8) Perform gate oxidation to form a gate oxide layer, deposit gate polysilicon, and then make a dielectric layer. Make source metal and drain metal in the drain region A and the source region A, sputter the top metal and anneal, and the device is completed.

8. The method for manufacturing a silicon carbide superjunction planar gate lateral MOS device according to claim 7, characterized in that: The first hard mask layer, the second hard mask layer, the third hard mask layer, the fourth hard mask layer and the fifth hard mask layer are made of the same material, and the material composition adopts one of the following combinations: a. From bottom to top: ion implantation barrier layer and oxide layer; b. From bottom to top: ion implantation barrier layer and polysilicon layer; c. From bottom to top: ion implantation barrier layer, polysilicon layer, and metal layer; d. From bottom to top: ion implantation barrier layer, polysilicon layer, and oxide layer.

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