SJ-MOSFET device and manufacturing method thereof

Abstract

The invention discloses an SJ-MOSFET device. The SJ-MOSFET device comprises a first conductive type substrate; a first conductive type epitaxial layer; a source region; a body region; a second conductive type doped column; and the trench gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region. On the other hand, the invention discloses a manufacturing method. The grid electrode and the grid electrode groove are arranged on the side face of the doped column, a part of the grid electrode groove is arranged in the doped column, so that the area of the grid electrode groove occupying the MESA is small, the grid electrode groove is arranged towards the interior of the doped column, the cell size and the pitch between two source electrode contact holes can be reduced to the maximum extent, and the manufacturing cost is reduced. And meanwhile, no JFET resistor exists, so that the optimization of the on-resistance is realized.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a SJ-MOSFET device and a manufacturing method thereof. Background Art

[0002] At present, in semiconductor device technology, SJ-MOSFET device (Super Junction Trench Mosfet) technology is widely used, especially in the field of medium and high voltage switching converters. Compared with the traditional voltage-withstand structure, the super structure forms alternating P-type and N-type regions in the drift region of the conventional device. It can make the resistivity of the drift region lower without compromising the voltage-withstand capability of the device. Therefore, the device can also achieve a lower on-resistance and reduce the power consumption of the system. Therefore, it is widely used in high-voltage and high-frequency switching power supply circuits.

[0003] The current SJ MOSFET devices all have a gate in the middle of two Pillars, one gate controls two channels, and the source contact hole is punched on the Pillar. The surge capability needs to be improved, and the dynamic parameter matching application adjustment freedom is not high. Summary of the invention

[0004] In view of this, in order to solve the problem of the background technology, (this part is not modified, and will be modified together when the claims are determined) the present invention provides a SJ-MOSFET device, including:

[0005] a first conductive type substrate;

[0006] A first conductivity type epitaxial layer, wherein the first conductivity type epitaxial layer is disposed on a first conductivity type substrate;

[0007] A source region, wherein the source region is disposed on an upper surface of the first conductivity type epitaxial layer;

[0008] a body region, the body region being arranged below the source region;

[0009] A second conductive type doped column, wherein the second conductive type doped column is disposed in the first conductive type epitaxial layer and runs through the source region and the body region;

[0010] A trench gate is disposed on a side of the second conductive type doped column and penetrates the source region and the body region.

[0011] Preferably, it also includes a dielectric layer and a metal layer,

[0012] The dielectric layer is arranged above the first conductive type epitaxial layer, the metal layer is arranged above the dielectric layer, contact holes are opened on the dielectric layer, and the metal layer is electrically connected to the source region and the second conductive type doped column through the corresponding contact holes respectively;

[0013] The depth of the contact hole extends to a depth corresponding to the body region.

[0014] Another aspect of the present invention discloses a method for manufacturing a SJ-MOSFET device, comprising the following steps:

[0015] providing a substrate, and disposing an epitaxial layer on the substrate;

[0016] forming a second conductivity type doped column in the epitaxial layer;

[0017] Performing ion implantation on the upper surface of the epitaxial layer to form a body region;

[0018] Etching the side of the second conductive type doped column to form a second trench;

[0019] forming a trench gate in the second trench;

[0020] forming a source region on the upper surface of the body region;

[0021] forming a dielectric layer above the epitaxial layer;

[0022] forming a contact hole on the dielectric layer, wherein the contact hole penetrates the source region and extends to the body region;

[0023] forming a CT region at the bottom of the contact hole by ion implantation and annealing;

[0024] Deposition is performed on the dielectric layer to form a metal layer.

[0025] Preferably, forming a second conductivity type doped column in the epitaxial layer comprises:

[0026] forming a second conductivity type doped column in the epitaxial layer by a multi-layer epitaxial implantation process, wherein the multi-layer epitaxial implantation process includes epitaxial growth, photolithography and ion implantation;

[0027] or,

[0028] Etching is performed on the epitaxial layer and the barrier layer to form a first trench, and then a second conductive type doped column is formed in the first trench by a single epitaxial layer implantation process.

[0029] Preferably, after forming the second trench, the method further comprises the step of: growing a sacrificial oxide layer on the second trench and removing the layer.

[0030] Preferably, after forming the second trench, a HDP process is performed on the second trench to fill the second trench and then etch back to form a thick oxide layer at the bottom of the second trench.

[0031] Preferably, forming a trench gate and / or a trench dummy gate in the second trench comprises: generating a gate oxide layer in the second trench and then filling it to form gate polysilicon.

[0032] Preferably, the trench dummy gate is electrically connected to the metal layer through a contact hole.

[0033] The beneficial effects of the present invention are:

[0034] (1) The present invention arranges the gate and the gate trench on the side of the doped column, and a part of the gate trench is arranged inside the doped column, so that the gate trench occupies less area of ​​the MESA, and the gate trench is arranged further inside the doped column, which can minimize the cell size and the pitch between the two source contact holes. At the same time, there is no JFET resistance, and the on-resistance is optimized.

[0035] (2) In the present invention, contact holes are provided on both the second conductive type doped column and the MESA region. The contact holes are electrically connected to the source, so that there are two source contact holes in one cell, which greatly improves the surge capability of the device.

[0036] (3) The present invention saves the MESA area by setting the gate groove, so that the MESA contact hole can be made wider than the doped column contact hole, which greatly improves the UIS capability of the device. The width of the MESA contact hole can even extend to the doped column contact hole and form a common contact hole, thereby maximizing the improvement of the UIS capability of the device and improving the surge capability.

[0037] (4) Each channel of the present invention is independently controlled by a gate, and the number of gates is halved, which reduces the Cgs and Cgd of the device, improves the switching speed, reduces the switching loss, and enhances the current short-circuit capability of the product.

[0038] (5) Although the present invention changes the internal structure of the device, the present invention does not increase the layout and process costs of the device in terms of the manufacturing method. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figures 1 to 9 It is a schematic diagram of a flow chart of an embodiment of the present invention;

[0041] Figures 10 to 12 It is a schematic structural diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The core of the present invention is to provide a SJ-MOSFET device and a method for manufacturing the same. The present invention sets the gate and the gate groove on the side of the doped column, and a part of the gate groove is set inside the doped column, so that the gate groove occupies less area of ​​the MESA, and the gate groove is set further inside the doped column, which can minimize the cell size and the pitch between the two source contact holes, and at the same time, there is no JFET resistance, so the on-resistance is optimized. At the same time, the source contact holes are increased, and the surge capacity is improved. In addition, the present invention also reduces the Cgs and Cgd of the device, improves the switching speed, improves the switching speed, reduces the switching loss, and improves the current short-circuit capacity of the product.

[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] Embodiment 1

[0045] Figures 1 to 9 A method for manufacturing a SJ-MOSFET device provided in this embodiment is shown, comprising the following steps:

[0046] S1: Figure 1 As shown, a substrate 1 is prepared, and an epitaxial layer 2 is formed on the substrate 1 .

[0047] S2: Figure 2 As shown, a first trench 4 is formed on the epitaxial layer 2 (left), and then a second conductive type doped column 41 is formed in the first trench 4 by a single-layer epitaxial layer implantation process (right).

[0048] S3: Figure 3 As shown, ion implantation is performed on the upper surface of the epitaxial layer 2 and then diffusion is performed to form a body region 5.

[0049] S4: Figure 4 As shown, etching is performed on the side of the second conductive type doped column 41 to form a second trench 6 .

[0050] S5: Figure 5 As shown, a trench gate 7 is formed in the second trench 6; preferably, a gate oxide layer is first formed in the second trench 6, and then filled to form gate polysilicon, and finally the trench gate 7 is formed.

[0051] S6: Figure 6 As shown, a source region 8 is formed on the upper surface of the body region 5 ; preferably, ion implantation is performed on the upper surface of the body region 5 , and then annealing is performed to form the source region 8 .

[0052] S7: Figure 7 As shown, a dielectric layer 9 is formed on the epitaxial layer 2. Preferably, the dielectric layer 9 is formed by oxide deposition.

[0053] S8: Figure 8 As shown, a contact hole 10 is formed on the dielectric layer 9, and the contact hole 10 extends through the source region to the body region; preferably, etching is performed from the dielectric layer 9, and the etching depth extends to the depth corresponding to the body region, the contact hole 10 is arranged in the middle of the second conductive type doped column 41, and between two second conductive type doped columns 41, and then the CT region is formed at the bottom of the contact hole 10 that contacts the body region by ion implantation and annealing.

[0054] S9: Fig. 9 As shown, deposition is performed on the dielectric layer 9 to form a metal layer 11 , and the metal layer 11 is also deposited downward at the contact hole 10 , so that the source region 8 and the second conductive type doped column 41 are electrically connected to the metal layer 11 respectively.

[0055] In a preferred embodiment, in step S2, the second conductive type doped column 41 may be formed in the epitaxial layer 2 by a multi-layer epitaxial implantation process, wherein the multi-layer epitaxial implantation process includes epitaxial growth, photolithography and ion implantation.

[0056] In a preferred embodiment, after forming the second trench 6 in step S4, the step of: growing and removing a sacrificial oxide layer on the second trench 6 is further included. Preferably, a thick oxide structure (TBO) is then formed at the bottom of the second trench 6. One implementation method may be to perform HDP process filling and etching back to form a thick oxide layer at the bottom of the second trench 6, which improves the withstand voltage, reduces the Cgd capacitance, and helps optimize the device manufacturing process.

[0057] Embodiment 2

[0058] like Fig. 9 As shown, this embodiment discloses a SJ-MOSFET device, including:

[0059] A substrate 1 of a first conductivity type;

[0060] An epitaxial layer 2 of a first conductivity type, wherein the epitaxial layer 2 of the first conductivity type is disposed on a substrate 1 of the first conductivity type;

[0061] A source region 8, the source region is arranged on the upper surface of the epitaxial layer 2 of the first conductivity type;

[0062] A body region 7, wherein the body region 7 is arranged below the source region 8;

[0063] A second conductive type doped column 41, which is disposed in the first conductive type epitaxial layer 2 and penetrates the source region 8 and the body region 7;

[0064] A trench gate 7, which is disposed on a side of the second conductive type doped column 41 and extends through the source region to the body region;

[0065] A dielectric layer 9 and a metal layer 11, wherein the dielectric layer 9 is arranged above the epitaxial layer 2 of the first conductive type, and the metal layer 11 is arranged above the dielectric layer 9. A contact hole is opened on the dielectric layer 9. The contact hole 10 is divided into a doped column contact hole 101 and a MESA contact hole 102 according to different setting positions. The metal layer 11 is electrically connected to the second conductive type doped column through the doped column contact hole 101, and the metal layer 11 is electrically connected to the source region 8 through the MESA contact hole 102. The contact hole 10 penetrates the dielectric layer 9 and the source region 8, and extends to the depth corresponding to the body region 7.

[0066] Preferably, the arrangement of the contact hole 10 in the embodiment of the present invention can be changed according to the arrangement of the trench gate 7 .

[0067] Method 1

[0068] The trench gates 7 are all disposed at one end of the second conductive type doped column 41. Fig. 9 As shown, both are arranged at the right end, then the MESA contact hole 102 between the two second conductive type doped columns 41 can extend toward the end of the second conductive type doped column 41 where the trench gate 7 is not arranged, as shown in FIG. Fig.10 As shown, the width of the MESA contact hole 102 is increased, which greatly improves the UIS capability of the device. Fig.11 As shown, the MESA contact hole 102 can even extend to the doped column contact hole 101 to form a common contact hole 103, which can maximize the UIS capability of the device. The manufacturing method of this method is similar to that of the first embodiment, and only the etching position needs to be increased in the step of etching the contact hole, and no additional manufacturing steps are required.

[0069] Method 2

[0070] The trench gate 7 is disposed between two adjacent second conductivity type doped columns 41. Fig.12As shown, the second conductive type doped column 41 includes a first doped column 411, a second doped column 412 and a third doped column 413 arranged in sequence. For the convenience of illustration, the third doped column 413 is added, but in actual practice it is not limited to only three doped columns, which belongs to the scope that those skilled in the art should be familiar with, and will not be repeated here; the trench gate 7 is arranged between the first doped column 411 and the second doped column 412; the trench gate 7 is not arranged between the second doped column 412 and the third doped column 413. At this time, because there is no trench gate 7, the usable area of ​​the MESA area becomes larger, and the width of the MESA contact hole 102 between the second doped column 412 and the third doped column 413 can be made larger than the MESA contact hole 102 between the first doped column 411 and the second doped column 412, so as to improve the UIS capability of the device. The manufacturing method of this method is similar to that of the first embodiment, and it is only necessary to increase the etching position in the step of etching the contact hole 10 and adjust the position of the etching trench gate 7, and no additional manufacturing steps are required.

[0071] In the embodiment of the present invention, the gate and the gate trench are arranged on the side of the doped column, and a part of the gate trench is arranged inside the doped column, so that the gate trench occupies less area of ​​the MESA, and the gate trench is arranged further inside the doped column, which can minimize the cell size and the pitch between the two source contact holes. At the same time, there is no JFET resistance, thereby optimizing the on-resistance.

[0072] Each channel of the present invention is independently controlled by a gate, the number of gates is halved, the Cgs and Cgd of the device are reduced, the switching speed is increased, the switching loss is reduced, and the current short-circuit capability of the product is improved.

[0073] In the present invention, contact holes are arranged on the second conductive type doped column and the MESA region, and the contact holes are electrically connected to the source, so that two source contact holes are provided in one cell, which greatly improves the surge capacity of the device.

[0074] The present invention can also set the width of the contact hole in the MESA region to be larger, further improving the UIS capability of the device.

[0075] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0076] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A SJ-MOSFET device, characterized in that: include: a first conductive type substrate; A first conductivity type epitaxial layer, wherein the first conductivity type epitaxial layer is disposed on a first conductivity type substrate; A source region, wherein the source region is disposed on an upper surface of the first conductivity type epitaxial layer; a body region, the body region being arranged below the source region; A second conductive type doped column, wherein the second conductive type doped column is disposed in the first conductive type epitaxial layer and runs through the source region and the body region; A trench gate is disposed on a side of the second conductive type doped column and penetrates the source region and the body region.

2. The SJ-MOSFET device according to claim 1, characterized in that: It also includes a dielectric layer and a metal layer. The dielectric layer is arranged above the first conductive type epitaxial layer, the metal layer is arranged above the dielectric layer, contact holes are opened on the dielectric layer, the contact holes include doped column contact holes and MESA contact holes, the metal layer is electrically connected to the second conductive type doped column through the doped column contact holes, and the metal layer is electrically connected to the source region through the MESA contact holes; The depth of the contact hole extends to a depth corresponding to the body region.

3. The SJ-MOSFET device according to claim 2, characterized in that: The second conductive type doped column includes a first doped column, a second doped column and a third doped column arranged in sequence; the trench gate is arranged between the first doped column and the second doped column; and no trench gate is arranged between the second doped column and the third doped column.

4. The SJ-MOSFET device according to claim 3, characterized in that: The width of the MESA contact hole is greater than the width of the doping column contact hole.

5. The SJ-MOSFET device according to claim 2, characterized in that: The second conductive type doped column comprises a first doped column, a second doped column and a third doped column which are arranged in sequence; and the trench gates are all arranged at one end of the second conductive type doped column.

6. The SJ-MOSFET device according to claim 5, characterized in that: At least one of the MESA contact holes and at least one of the doped column contact holes form a common contact hole.

7. A method for manufacturing a SJ-MOSFET device, characterized in that: The steps include: providing a substrate, and disposing an epitaxial layer on the substrate; forming a second conductivity type doped column in the epitaxial layer; Performing ion implantation on the upper surface of the epitaxial layer to form a body region; Etching the side of the second conductive type doped column to form a second trench; forming a trench gate in the second trench; forming a source region on the upper surface of the body region; forming a dielectric layer above the epitaxial layer; forming a contact hole on the dielectric layer, wherein the contact hole penetrates the source region and extends to the body region; forming a CT region at the bottom of the contact hole by ion implantation and annealing; Deposition is performed on the dielectric layer to form a metal layer.

8. The method according to claim 7, characterized in that: Forming a second conductive type doped column in the epitaxial layer, comprising: forming a second conductivity type doped column in the epitaxial layer by a multi-layer epitaxial implantation process, wherein the multi-layer epitaxial implantation process includes epitaxial growth, photolithography and ion implantation; or, Etching is performed on the epitaxial layer and the barrier layer to form a first trench, and then a second conductive type doped column is formed in the first trench by a single epitaxial layer implantation process.

9. The manufacturing method according to claim 7, characterized in that: After forming the second trench, the method further includes the steps of: growing a sacrificial oxide layer on the second trench and removing the layer.

10. The manufacturing method according to claim 7, characterized in that: After forming the second trench, a HDP process is performed on the second trench to fill and then etch back to form a thick oxide layer at the bottom of the second trench.

11. The manufacturing method according to claim 7, characterized in that: Forming a trench gate and / or a trench dummy gate in the second trench includes: generating a gate oxide layer in the second trench, and then filling it to form gate polysilicon.

12. The manufacturing method according to claim 7, characterized in that: The contact holes include doped column contact holes and MESA contact holes, the metal layer is electrically connected to the second conductive type doped column through the doped column contact holes, and the metal layer is electrically connected to the source region through the MESA contact holes; The depth of the contact hole extends to a depth corresponding to the body region.

13. The manufacturing method according to claim 7, characterized in that: The second conductive type doped column includes a first doped column, a second doped column and a third doped column arranged in sequence; the trench gate is arranged between the first doped column and the second doped column; and no trench gate is arranged between the second doped column and the third doped column.

14. The manufacturing method according to claim 7, characterized in that: A width of the MESA contact hole between the second doping column and the third doping column is greater than a width of the MESA contact hole between the first doping column and the second doping column.

15. The manufacturing method according to claim 7, characterized in that: The trench gates are all arranged at one end of the second conductive type doped column, and the MESA contact hole extends toward one end of the second conductive type doped column where the trench gates are not arranged.

16. The manufacturing method according to claim 7, characterized in that: At least one of the MESA contact holes and at least one of the doped column contact holes form a common contact hole.

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