SiC MOSFET device and preparation method thereof

Abstract

The invention provides a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method thereof, and the method comprises the following steps: preparing and forming an epitaxial layer on a SiC substrate, and respectively forming an inverted floating layer and a P-WELL layer on the surfaces of an N-type base layer and a current expansion layer through ion implantation; preparing an N-type source layer, a P + layer and a grid layer on the epitaxial layer; and sequentially preparing and forming an ILD layer, an electrode layer and a passivation layer on the surface of the device to obtain a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device. Through the arrangement of the inverted floating layer, when the device is short-circuited, the P-WELL layer is connected with the inverted floating layer through the P + layer, namely, heat borne by the P + layer is dispersed into a semiconductor material, burnout is not easy to occur after the heat is dispersed, and the short-circuit tolerance capability is improved; when the device works normally, the inversion floating layer forms a depletion layer, so that the electric field trend at the corner of the P-WELL layer becomes slow, and the voltage endurance capability of the device is enhanced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a SiC MOSFET device and a preparation method thereof. Background Art

[0002] As one of the representatives of the third generation wide bandgap semiconductor materials, silicon carbide has the characteristics of large bandgap width, high critical breakdown electric field, high thermal conductivity and high electron saturation drift velocity, which makes it have broad application prospects in the field of high-power, high-temperature and high-frequency power electronics. Silicon carbide, or SiC, is suitable for making high-voltage power devices because of its high critical electric field. Reverse withstand voltage and device on-resistance (current capability) are two characteristics that need to be balanced with each other.

[0003] In the prior art, for N-channel planar SiC MOSFET devices, when the PN junction formed by the P-WELL layer and the epitaxial material is reverse biased, the edge of the P-type injection well is prone to burnout due to the curvature effect of the P-WELL edge. At the same time, when a short-circuit high current passes through the P+ layer, thermal burnout is likely to occur because the heat point is close to the device surface. Summary of the invention

[0004] In view of the deficiencies in the prior art, the object of the present invention is to provide a SiC MOSFET device and a method for preparing the same, aiming to solve the technical problems of poor short-circuit current capability and low withstand voltage of the device in the prior art.

[0005] In order to achieve the above object, the present invention is implemented by the following technical solution: a method for preparing a SiC MOSFET device, comprising the following steps: Providing a SiC substrate; An epitaxial layer including an N-type base layer and a current spreading layer is prepared on the SiC substrate, and an inverted floating layer and a P-WELL layer are formed on the surfaces of the N-type base layer and the current spreading layer respectively by ion implantation; An N-type source layer is formed on the surface of the epitaxial layer, a P+ layer is formed on the side of the cell region of the epitaxial layer, and a gate layer is generated on the surface of the N-type source layer, the bottom of the P+ layer is flush with the bottom of the inverted floating layer, and the top of the P+ layer is flush with the top of the P-WELL layer; An ILD layer, an electrode layer and a passivation layer are sequentially formed on the surface of the device to obtain a SiC MOSFET device; The steps of forming an inverted floating layer and a P-WELL layer on the surface of the N-type base layer and the current spreading layer by ion implantation specifically include: Based on the first implantation parameter, an inverted floating layer is formed on the surface of the N-type base layer by ion implantation; Forming a P-WELL layer on the surface of the current spreading layer by ion implantation based on a second implantation parameter; The first implantation parameters include: the implantation material polarity is P type, the implantation energy is 60KeV-2MeV, and the implantation dose is 1e11-5e14 / cm 2 .

[0006] Compared with the prior art, the beneficial effects of the present invention are as follows: by arranging an inverted floating layer on the surface of the N-type base layer, that is, on the bottom side of the current expansion layer, the reverse withstand voltage is increased without increasing the on-resistance, and at the same time it is beneficial to improve the short-circuit current tolerance capability; when the device is short-circuited, the P-WELL layer is connected to the inverted floating layer through the P+ layer, which is equivalent to dispersing the heat borne by the P+ layer position into the semiconductor material. After the heat is dissipated, burning is less likely to occur, thereby improving the short-circuit tolerance capability; when the device is working normally, the inverted floating layer will form a depletion layer to change the electric field trend at the corner of the P-WELL layer, making it slow, thereby enhancing the voltage resistance of the device.

[0007] According to one aspect of the above technical solution, the step of preparing an epitaxial layer including an N-type base layer and a current spreading layer on the SiC substrate specifically includes: An epitaxial material layer including an N-type base layer is deposited on the SiC substrate, and a current spreading layer is formed on the N-type base layer by ion implantation based on a third implantation parameter to prepare an epitaxial layer.

[0008] According to one aspect of the above technical solution, the step of forming an inverted floating layer and a P-WELL layer on the surface of the N-type base layer and the current spreading layer by ion implantation specifically includes: The mask photoresist used in the process of preparing the inverted floating layer ion implantation is the same as the mask photoresist used in the process of preparing the P-WELL layer ion implantation.

[0009] According to one aspect of the above technical solution, the steps of preparing an N-type source layer on the surface of the epitaxial layer, forming a P+ layer on the side of the cell region of the epitaxial layer, and generating a gate layer on the surface of the N-type source layer specifically include: Based on the fourth implantation parameter, an N-type source layer is formed on the surface of the P-WELL layer by self-aligned ion implantation; Forming a P+ layer on the side of the cell region of the epitaxial layer by ion implantation based on a fifth implantation parameter; A gate layer is formed on the surface of the epitaxial layer, wherein the gate layer includes a gate oxide layer and a doped polysilicon layer which are sequentially arranged on the epitaxial layer.

[0010] According to one aspect of the above technical solution, the second injection parameters include: the injection material polarity is P type, the injection concentration is 1e16-1e18 / cm 3 The third injection parameters include: the injection material polarity is N-type, the injection concentration is 1e16-1e18 / cm 3 The fourth injection parameters include: the injection material is N-type, the injection concentration is 1e19-1e20 / cm 3 The fifth injection parameters include: the injection material is P type, the injection concentration is 1e19-1e20 / cm 3 .

[0011] According to one aspect of the above technical solution, the ILD layer is made of SiO2.

[0012] According to one aspect of the above technical solution, the thickness h of the gate oxide layer satisfies: h>20nm.

[0013] According to one aspect of the above technical solution, the steps of sequentially preparing an ILD layer, an electrode layer and a passivation layer on the device surface specifically include: Depositing an ILD layer on the surface of the device by a chemical vapor deposition process, and forming a contact hole on the ILD layer by a photolithography mask process; A barrier metal layer and an electrode metal layer are sequentially sputtered on the ILD layer by a physical vapor deposition process, and then the gate source is separated and etched to obtain an electrode layer; A passivation layer is prepared on the electrode layer.

[0014] According to one aspect of the above technical solution, the barrier metal layer is made of one of Ni, Ti, Co, and W, and the electrode metal layer is made of one of Al, AlCu, and AlSiCu.

[0015] On the other hand, the present invention further provides a SiC MOSFET device, which is prepared by a method for preparing a SiC MOSFET device in the above technical solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a flow chart of a method for preparing a SiC MOSFET device in a first embodiment of the present invention; Figure 2 It is a schematic diagram of a partial cross-sectional structure of a device prepared in step S210 in the first embodiment of the present invention; Figure 3 It is a schematic diagram of a partial cross-sectional structure of the device prepared in step S220 in the first embodiment of the present invention; Figure 4 It is a schematic diagram of a partial cross-sectional structure of the device prepared in step S230 in the first embodiment of the present invention; Figure 5 It is a schematic diagram of a partial cross-sectional structure of a device prepared in step S310 in the first embodiment of the present invention; Figure 6 It is a schematic diagram of a partial cross-sectional structure of the device prepared in step S320 in the first embodiment of the present invention; Figure 7 It is a schematic diagram of a partial cross-sectional structure of the device prepared in step S330 in the first embodiment of the present invention; Figure 8 It is a schematic diagram of a partial cross-sectional structure of a device prepared in step S410 in the first embodiment of the present invention; Fig. 9 It is a schematic diagram of a partial cross-sectional structure of the device prepared in step S420 in the first embodiment of the present invention; Description of main component symbols: N-type base layer 101, current spreading layer 001, inverted floating layer 103, P-WELL layer 105, N-type source layer 104, P+ layer 102, gate oxide layer 302, doped polysilicon layer 201, ILD layer 301, electrode layer 401; The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0017] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0018] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0020] See also Figure 1 , which is a flow chart of a method for preparing a SiC MOSFET device in a first embodiment of the present invention, as shown in Figure 1 As shown, the method comprises the following steps: Step S100, providing a SiC substrate.

[0021] Step S200, forming an epitaxial layer including an N-type base layer and a current spreading layer on the SiC substrate, and forming an inversion floating layer and a P-WELL layer on the surface of the N-type base layer and the current spreading layer by ion implantation. The P-WELL layer 105 is also called a P-well, a P-type implantation well or a P-wall.

[0022] Specifically, in this embodiment, the step of preparing and forming an epitaxial layer including an N-type base layer 101 and a current spreading layer 001 on the SiC substrate specifically includes: Step S210, depositing an epitaxial material layer including an N-type base layer on the SiC substrate, and forming a current spreading layer on the N-type base layer by ion implantation based on a third implantation parameter to prepare an epitaxial layer.

[0023] By performing ion implantation of N-type impurities on one side of the surface of the epitaxial material layer, a current spreading layer 001 with a higher polarity is formed, and the other area of ​​the epitaxial material layer where the impurities are not implanted is the N-type base layer 101. Preferably, the epitaxial thickness of the above-mentioned N-type base layer 101 is preferably 5-17um. Preferably, in this embodiment, the third implantation parameter includes: the implantation material polarity is N-type, the implantation concentration is 1e16-1e18 / cm 3 For ease of understanding, the schematic diagram of a partial cross-sectional structure of the device prepared in step S210 is as follows: Figure 2 As shown, the dotted line in the figure is the boundary point between the N-type base layer 101 and the current spreading layer 001 , which are made of the same material, except that the polarity concentration of the material injected into the current spreading layer 001 is greater than that of the N-type base layer 101 .

[0024] The steps of forming an inverted floating layer and a P-WELL layer on the surface of the N-type base layer 101 and the current spreading layer 001 by ion implantation specifically include: Step S220, forming an inverted floating layer on the surface of the N-type base layer by ion implantation based on the first implantation parameter. For ease of understanding, a partial cross-sectional structure diagram of the device prepared in the above step S220 is shown in FIG. Figure 3As shown, the "inversion" in the inversion floating layer 103 means that the polarity of the material is opposite to that of the epitaxial layer. Preferably, in this embodiment, the first implantation parameters include: the polarity of the implanted material is P type, the implantation energy is 60KeV-2MeV, and the implantation dose is 1e11-5e14 / cm 2 .

[0025] Step S230, forming a P-WELL layer on the surface of the current spreading layer by ion implantation based on a second implantation parameter. Preferably, in this embodiment, the second implantation parameter includes: the implantation material polarity is P type, the implantation concentration is 1e16-1e18 / cm 3 For ease of understanding, the schematic diagram of a partial cross-sectional structure of the device prepared in step S230 is as follows: Figure 4 As shown, in the present embodiment, the mask photoresist used in the ion implantation process for preparing the inverted floating layer 103 is the same as the mask photoresist used in the ion implantation process for preparing the P-WELL layer 105. The preparation of the inverted floating layer 103 in the present solution does not add any additional steps on the basis of the existing planar MOSFET process, and can be formed by only one ion implantation. Moreover, the mask photoresist used in the ion implantation process is the same as that used in the preparation process of the P-WELL layer 105, which has good compatibility with the existing process and low implementation cost.

[0026] In step S300, an N-type source layer is prepared on the surface of the epitaxial layer, a P+ layer is prepared on the side of the cell region of the epitaxial layer, and a gate layer is generated on the surface of the N-type source layer. The bottom of the P+ layer is flush with the bottom of the inverted floating layer, and the top of the P+ layer is flush with the top of the P-WELL layer.

[0027] Further, in this embodiment, the steps of preparing an N-type source layer on the surface of the epitaxial layer, forming a P+ layer on the side of the cell region of the epitaxial layer, and generating a gate layer on the surface of the N-type source layer specifically include: Step S310, forming an N-type source layer on the surface of the P-WELL layer by self-aligned ion implantation based on a fourth implantation parameter. Preferably, in this embodiment, the fourth implantation parameter includes: the implantation material is N-type, the implantation concentration is 1e19-1e20 / cm 3 For ease of understanding, the schematic diagram of a partial cross-sectional structure of the device prepared in step S310 is as follows: Figure 5 As shown, the N-type source layer 104 is located on the surface of the P-WELL layer 105 .

[0028] Step S320, forming a P+ layer on the side of the cell region of the epitaxial layer by ion implantation based on the fifth implantation parameter. Preferably, in this embodiment, the fifth implantation parameter includes: the implantation material is P type, the implantation concentration is 1e19-1e20 / cm 3 For ease of understanding, the schematic diagram of the partial cross-sectional structure of the device prepared in step S320 is as follows: Figure 6 As shown, the bottom of the P+ layer 102 is flush with the bottom of the inverted floating layer 103 , and the top of the P+ layer 102 is flush with the top of the P-WELL layer 105 .

[0029] Step S330, forming a gate layer on the surface of the epitaxial layer, wherein the gate layer includes a gate oxide layer and a doped polysilicon layer sequentially disposed on the epitaxial layer. For ease of understanding, a partial cross-sectional structural diagram of the device prepared in the above step S330 is shown in FIG. Figure 7 As shown, the gate oxide layer 302 is located on the surface of the epitaxial layer, namely, the current spreading layer 001 , the P-WELL layer 105 and the N-type source layer 104 ; the doped polysilicon layer 201 is located on the surface of the gate oxide layer 302 .

[0030] Step S400: forming an ILD layer, an electrode layer and a passivation layer on the surface of the device in sequence to obtain a SiC MOSFET device.

[0031] Specifically, in this embodiment, the steps of sequentially preparing an ILD layer, an electrode layer and a passivation layer on the device surface specifically include: Step S410, depositing an ILD layer on the surface of the device by a chemical vapor deposition process, and forming contact holes on the ILD layer by a photolithography mask process. For ease of understanding, a partial cross-sectional structure diagram of the device prepared in the above step S410 is shown in FIG. Figure 8 As shown, the ILD layer 301 is located on the surface of the gate layer and the N-type source layer 104 .

[0032] Step S420, a barrier metal layer and an electrode metal layer are sequentially sputtered on the ILD layer by a physical vapor deposition process, and then the gate source is subjected to a separation etching process to obtain an electrode layer. For ease of understanding, a partial cross-sectional structure diagram of the device obtained in the above step S420 is shown in FIG. Fig. 9 As shown, the electrode layer 401 is located on the surface of the ILD layer 301 .

[0033] Specifically, the barrier metal layer is made of one of Ni, Ti, Co, and W, and the electrode metal layer is made of one of Al, AlCu, and AlSiCu. In this embodiment, the barrier metal layer is preferably made of Ni, and the electrode metal layer is preferably made of Al.

[0034] In summary, the method for preparing the SiC MOSFET device in the above embodiment of the present invention increases the reverse withstand voltage without increasing the on-resistance by setting an inversion floating layer 103 on the surface of the N-type base layer 101, that is, on the bottom side of the current extension layer 001, and is beneficial to improving the short-circuit current tolerance capability; when the device is short-circuited, the P-WELL layer 105 is connected to the inversion floating layer 103 through the P+ layer 102, which is equivalent to dispersing the heat borne by the P+ layer 102 into the semiconductor material. After the heat is dispersed, burning is not likely to occur, thereby improving the short-circuit tolerance capability; when the device is working normally, the inversion floating layer 103 will form a depletion layer to change the electric field trend at the corner of the P-WELL layer 105, making it slow, thereby enhancing the voltage resistance of the device.

[0035] A second embodiment of the present invention provides a SiC MOSFET device, which is manufactured by the method for manufacturing the SiC MOSFET device in the above embodiment.

[0036] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0037] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A method for preparing a SiC MOSFET device, characterized in that: The following steps are involved: Providing a SiC substrate; An epitaxial layer including an N-type base layer and a current spreading layer is prepared on the SiC substrate, and an inverted floating layer and a P-WELL layer are formed on the surfaces of the N-type base layer and the current spreading layer respectively by ion implantation; An N-type source layer is formed on the surface of the epitaxial layer, a P+ layer is formed on the side of the cell region of the epitaxial layer, and a gate layer is generated on the surface of the N-type source layer, the bottom of the P+ layer is flush with the bottom of the inverted floating layer, and the top of the P+ layer is flush with the top of the P-WELL layer; An ILD layer, an electrode layer and a passivation layer are sequentially formed on the surface of the device to obtain a SiC MOSFET device; The steps of forming an inverted floating layer and a P-WELL layer on the surface of the N-type base layer and the current spreading layer by ion implantation specifically include: Based on the first implantation parameter, an inverted floating layer is formed on the surface of the N-type base layer by ion implantation; Forming a P-WELL layer on the surface of the current spreading layer by ion implantation based on a second implantation parameter; The first implantation parameters include: the implantation material polarity is P type, the implantation energy is 60KeV-2MeV, and the implantation dose is 1e11-5e14 / cm 2 .

2. The method for preparing a SiC MOSFET device according to claim 1, characterized in that: The step of preparing an epitaxial layer including an N-type base layer and a current spreading layer on the SiC substrate specifically includes: An epitaxial material layer including an N-type base layer is deposited on the SiC substrate, and a current spreading layer is formed on the N-type base layer by ion implantation based on a third implantation parameter to prepare an epitaxial layer.

3. The method for preparing a SiC MOSFET device according to claim 2, characterized in that: The step of forming an inverted floating layer and a P-WELL layer on the surface of the N-type base layer and the current spreading layer by ion implantation specifically includes: The mask photoresist used in the process of preparing the inverted floating layer ion implantation is the same as the mask photoresist used in the process of preparing the P-WELL layer ion implantation.

4. The method for preparing a SiC MOSFET device according to claim 3, characterized in that: The steps of preparing an N-type source layer on the surface of the epitaxial layer, forming a P+ layer on the side of the cell region of the epitaxial layer, and generating a gate layer on the surface of the N-type source layer specifically include: Based on the fourth implantation parameter, an N-type source layer is formed on the surface of the P-WELL layer by self-aligned ion implantation; Forming a P+ layer on the side of the cell region of the epitaxial layer by ion implantation based on a fifth implantation parameter; A gate layer is formed on the surface of the epitaxial layer, wherein the gate layer includes a gate oxide layer and a doped polysilicon layer which are sequentially arranged on the epitaxial layer.

5. The method for preparing a SiC MOSFET device according to claim 4, characterized in that: The second injection parameters include: the injection material polarity is P type, the injection concentration is 1e16-1e18 / cm 3 The third injection parameters include: the injection material polarity is N-type, the injection concentration is 1e16-1e18 / cm 3 The fourth injection parameters include: the injection material is N-type, the injection concentration is 1e19-1e20 / cm 3 The fifth injection parameters include: the injection material is P type, the injection concentration is 1e19-1e20 / cm 3 .

6. The method for preparing a SiC MOSFET device according to claim 1, characterized in that: The ILD layer is made of SiO2.

7. The method for preparing a SiC MOSFET device according to claim 4, characterized in that: The thickness h of the gate oxide layer satisfies: h>20nm.

8. The method for preparing a SiC MOSFET device according to claim 1, characterized in that: The steps of sequentially preparing an ILD layer, an electrode layer and a passivation layer on the device surface specifically include: Depositing an ILD layer on the surface of the device by a chemical vapor deposition process, and forming a contact hole on the ILD layer by a photolithography mask process; A barrier metal layer and an electrode metal layer are sequentially sputtered on the ILD layer by a physical vapor deposition process, and then the gate source is separated and etched to obtain an electrode layer; A passivation layer is prepared on the electrode layer.

9. The method for preparing a SiC MOSFET device according to claim 8, characterized in that: The barrier metal layer is prepared from one of Ni, Ti, Co and W, and the electrode metal layer is prepared from one of Al, AlCu and AlSiCu.

10. A SiC MOSFET device, characterized in that: The SiC MOSFET device is prepared by the method for preparing a SiC MOSFET device according to any one of claims 1 to 9.

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