Solar cell and manufacturing method thereof

Abstract

According to the solar cell and the manufacturing method thereof, the structure of a grid line electrode is improved, so that a main grid electrode comprises a first metal layer and a second metal layer which are stacked in sequence, the first metal layer penetrates through a first passivation layer and is electrically connected with a silicon substrate, and effective collection and transmission of current are achieved; the silver element of the second metal layer is lower than that of the first metal layer, so that the silver consumption of the main gate electrode is reduced, and the cost of the main gate electrode is reduced; the fine gate electrode comprises a third metal layer and a fourth metal layer which are stacked in sequence, and the silver element content of the fourth metal layer is lower than that of the third metal layer, so that the silver consumption of the fine gate electrode is reduced, and the cost of the fine gate electrode is reduced; by designing the structures of the main gate electrode and the fine gate electrode and reasonably matching the material of each metal layer of the main gate electrode and the fine gate electrode, the efficient photoelectric conversion of the solar cell is ensured, the silver consumption of the gate line electrode of the solar cell is reduced, the production cost is reduced, and the market competitiveness of the solar cell is improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a method for manufacturing the same. Background Art

[0002] With the rapid development of photovoltaic power generation, how to reduce the production cost of solar cells and maintain the market competitiveness of solar cells is an urgent problem to be solved by those skilled in the art.

[0003] In particular, the existing solar cell grid lines use all-silver paste for electrical connection and current collection. With the increasing depletion of global silver mine resources and the continued rise in international silver prices, the manufacturing cost of crystalline silicon cells remains high, seriously restricting its further development. Summary of the invention

[0004] Based on this, it is necessary to provide a solar cell and a method for manufacturing the same in order to solve the problem that the manufacturing cost of crystalline silicon cells in the prior art remains high.

[0005] In a first aspect, the present disclosure provides a solar cell, comprising:

[0006] A silicon substrate, wherein a first passivation layer is provided on a first surface of the silicon substrate;

[0007] A gate line electrode, disposed on the first passivation layer, the gate line electrode comprising a main gate electrode and a fine gate electrode electrically connected to the main gate electrode;

[0008] The main gate electrode comprises a first metal layer and a second metal layer stacked in sequence; the first metal layer at least partially passes through the first passivation layer to be electrically connected to the silicon substrate, and the content of silver element in the second metal layer is lower than the content of silver element in the first metal layer;

[0009] The fine gate electrode includes a third metal layer and a fourth metal layer, and the content of silver element in the fourth metal layer is lower than the content of silver element in the third metal layer.

[0010] Optionally, the first metal layer is made of burn-through silver paste; the second metal layer is made of solder paste;

[0011] The third metal layer is made of non-fire-through silver paste; the fourth metal layer is made of copper-containing paste or aluminum-containing paste.

[0012] Optionally, a thickness ratio of the first metal layer to the second metal layer is 3:1-1:3; a thickness ratio of the third metal layer to the fourth metal layer is 3:1-1:3.

[0013] Optionally, the first metal layer and the second metal layer have the same thickness; the third metal layer and the fourth metal layer have the same thickness.

[0014] Optionally, the first metal layer is electrically connected to the third metal layer; and the fourth metal layer covers a surface of the third metal layer away from the silicon substrate and side walls other than a connection surface between the third metal layer and the first metal layer.

[0015] Optionally, the battery is a back contact battery, and the first surface is a backlight surface; the first surface of the silicon substrate has first regions and second regions that are alternately distributed, and the first regions and the second regions have opposite conductivity types; a first gate line electrode and a second gate line electrode are disposed on the first passivation layer;

[0016] The projection of the first gate line electrode on the silicon substrate falls on the first region, the first gate line electrode comprises a first main gate electrode and a first fine gate electrode, and at least a portion of the first main gate electrode penetrates the first passivation layer and is electrically connected to the first region;

[0017] The projection of the second gate line electrode on the silicon substrate falls on the second region. The second gate line electrode includes a second main gate electrode and a second fine gate electrode. At least a portion of the second main gate electrode is electrically connected to the second region through the first passivation layer.

[0018] In a second aspect, the present disclosure provides a method for manufacturing a solar cell, comprising:

[0019] Providing a silicon substrate, wherein a first passivation layer is formed on a first surface of the silicon substrate;

[0020] Printing a burn-through silver paste on the first passivation layer, and drying the burn-through silver paste to form a first metal layer;

[0021] Printing a non-burn-through silver paste on the first passivation layer, and drying the non-burn-through silver paste to form a third metal layer;

[0022] Laser sintering the first metal layer and the third metal layer so that the first metal layer is electrically connected to the third metal layer, and the first metal layer is at least partially electrically connected to the silicon substrate through the first passivation layer;

[0023] Printing solder paste on the first metal layer, and drying the solder paste to form a second metal layer, wherein the content of silver element in the second metal layer is lower than the content of silver element in the first metal layer; the first metal layer and the second metal layer form a main gate electrode;

[0024] A copper-containing paste or an aluminum-containing paste is printed on the third metal layer, and the copper-containing paste or the aluminum-containing paste is dried to form a fourth metal layer, wherein the content of silver element in the fourth metal layer is lower than the content of silver element in the third metal layer; the third metal layer and the fourth metal layer form a fine gate electrode, and the main gate electrode and the fine gate electrode form a gate line electrode.

[0025] Optionally, a thickness ratio of the first metal layer to the second metal layer is 3:1-1:3; a thickness ratio of the third metal layer to the fourth metal layer is 3:1-1:3.

[0026] Optionally, when printing copper-containing paste or aluminum-containing paste on the third metal layer, the copper-containing paste or aluminum-containing paste covers the surface of the third metal layer away from the silicon substrate and the sidewalls other than the connection surface between the third metal layer and the first metal layer.

[0027] Optionally, the battery is a back contact battery, and the manufacturing method includes:

[0028] Providing a silicon substrate, wherein a first passivation layer is formed on a first surface of the silicon substrate, the first surface is a backlight surface, the first surface has first regions and second regions that are alternately distributed, and the first regions and the second regions have opposite conductivity types;

[0029] Printing a burn-through silver paste on the first passivation layer in the first region and on the first passivation layer in the second region respectively, drying the burn-through silver paste, and forming a first metal layer on the first region and the second region respectively;

[0030] Printing a non-fire-through silver paste on the first passivation layer in the first region, drying the non-fire-through silver paste, and forming a third metal layer on the first region;

[0031] Printing a non-fire-through silver paste on the first passivation layer in the second region, drying the non-fire-through silver paste, and forming a third metal layer on the second region;

[0032] Laser sintering the first metal layer and the third metal layer on the first region and the first metal layer and the third metal layer on the second region, so that the first metal layer in the first region is electrically connected to the third metal layer in the first region, a partial region of the first metal layer in the first region is burned through the first passivation layer and is electrically connected to the first region, and at the same time, the third metal layer in the second region is electrically connected to the first metal layer in the second region, and a partial region of the first metal layer in the second region is burned through the first passivation layer and is electrically connected to the second region;

[0033] Solder paste is printed on the first metal layer of the first region and the first metal layer of the second region respectively, and the solder paste is dried to form a second metal layer; the content of silver element in the second metal layer is lower than the content of silver element in the first metal layer; the first metal layer and the second metal layer of the first region form a first main gate electrode, and the first metal layer and the second metal layer of the second region form a second main gate electrode;

[0034] Printing a copper-containing paste or an aluminum-containing paste on the third metal layer of the first region, drying the copper-containing paste or the aluminum-containing paste to form a fourth metal layer, wherein the content of silver element in the fourth metal layer is lower than the content of silver element in the third metal layer; the third metal layer and the fourth metal layer of the first region form a first fine gate electrode, and the first main gate electrode and the first fine gate electrode form a first gate line electrode;

[0035] Print copper-containing paste or aluminum-containing paste on the third metal layer in the second area, and dry the copper-containing paste or aluminum-containing paste to form a fourth metal layer; the third metal layer and the fourth metal layer in the second area form a second fine gate electrode, and the second main gate electrode and the second fine gate electrode form a second gate line electrode.

[0036] The solar cell and the manufacturing method thereof disclosed in the present invention improve the structure of the grid line electrode so that the main grid electrode includes a first metal layer and a second metal layer stacked in sequence, the first metal layer passes through a first passivation layer and is electrically connected to a silicon substrate to realize effective current collection and transmission, the silver element content of the second metal layer is lower than that of the first metal layer, so as to reduce the silver consumption of the main grid electrode and reduce the cost of the main grid electrode; the fine grid electrode includes a third metal layer and a fourth metal layer stacked in sequence, the silver element content of the fourth metal layer is lower than that of the third metal layer, so as to reduce the silver consumption of the fine grid electrode and reduce the cost of the fine grid electrode; the present invention designs the structure of the main grid electrode and the fine grid electrode and reasonably matches the materials of each metal layer of the main grid electrode and the fine grid electrode, so that the solar cell can reduce the silver consumption of the grid line electrode of the solar cell while ensuring efficient photoelectric conversion, reduce the production cost, and enhance the market competitiveness of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 is a schematic structural diagram of a gate line electrode provided in an embodiment;

[0039] Figure 2is a schematic structural diagram of a first gate line electrode and a second gate line electrode provided in an embodiment;

[0040] Figure 3 is a top view of a first surface of a solar cell provided in an embodiment;

[0041] Figure 4 A solar cell provided in an embodiment Figure 3 Sectional view along line AA;

[0042] Figure 5 A solar cell provided in an embodiment Figure 3 Sectional view of the middle BB line;

[0043] Figure 6 is a process flow chart of a method for manufacturing a solar cell provided in an embodiment;

[0044] Figure 7 It is a process flow chart of a method for manufacturing a solar cell provided in another embodiment.

[0045] Description of reference numerals:

[0046] 20. Silicon substrate; 20a. First surface; 21. Tunneling layer; 22. First semiconductor doping layer; 23. Second semiconductor doping layer; 30. Gate line electrode; 31. Main gate electrode; 32. Fine gate electrode; 130. First gate line electrode; 131. First main gate electrode; 132. First fine gate electrode; 230. Second gate line electrode; 231. Second main gate electrode; 232. Second fine gate electrode; 40. First passivation layer; 51. First metal layer; 52. Second metal layer; 53. Third metal layer; 54. Fourth metal layer; 60. Second passivation layer; A1. First region; A2. Second region; D1. First direction; D2. Second direction. DETAILED DESCRIPTION

[0047] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0049] At present, the high cost and complex process of manufacturing some solar cells have become an important obstacle to their large-scale industrialization. How to reduce their production costs and improve their market competitiveness is an urgent problem to be solved by those skilled in the art.

[0050] For example, the interdigitated back contact (IBC) crystalline silicon solar cell is a platform-type photovoltaic cell with wide compatibility. IBC cells can be easily combined with a variety of high-efficiency cell technologies. IBC cells have the characteristics of a front-side grid-free design and a finger-shaped cross arrangement formed by positive and negative metal grid lines on the back. IBC cells can further promote the improvement of photoelectric conversion efficiency. For example, the integration of IBC technology with heterojunction cell (Heterojunction with Intrinsic Thin-layer, HJT) technology can develop HBC cells with excellent performance; and the combination of IBC technology with tunnel oxide passivated contact cell (Tunnel Oxide Passivated Contact, TOPCON) technology can create high-efficiency TBC cells. However, the preparation cost of IBC cells is high and the process is complex, and the production cost is high, which is not conducive to large-scale industrial production. The metallization patterns of existing IBC cells generally use full silver paste for electrical connection and current collection, and the manufacturing cost is high, which seriously restricts its further development.

[0051] According to an exemplary embodiment, this embodiment provides a solar cell, such as Figure 1 And refer to Figure 4 , Figure 5 As shown, the solar cell includes a silicon substrate 20 and a gate electrode 30. A first passivation layer 40 is provided on a first surface 20a of the silicon substrate 20. The silicon substrate 20 may be an N-type substrate or a P-type substrate. The first passivation layer 40 is used to protect the silicon substrate 20 and reduce the surface recombination loss of the silicon substrate 20. The first passivation layer 40 is formed with a contact window. The gate electrode 30 is provided on the first passivation layer 40. The gate electrode 30 includes a main gate electrode 31 and a fine gate electrode 32 electrically connected to the main gate electrode 31. The main gate electrode 31 includes a The fine gate electrode 32 includes a first metal layer 51 and a second metal layer 52 stacked in sequence; the first metal layer 51 at least partially passes through the first passivation layer 40 to be electrically connected to the silicon substrate 20. Specifically, the first metal layer 51 contacts the silicon substrate 20 through a contact window of the first passivation layer 40, and the content of silver element in the second metal layer 52 is lower than the content of silver element in the first metal layer 51; the fine gate electrode 32 includes a third metal layer 53 and a fourth metal layer 54, and the content of silver element in the fourth metal layer 54 is lower than the content of silver element in the third metal layer 53.

[0052] The solar cell of this embodiment improves the structure of the gate electrode 30 so that the main gate electrode 31 includes a first metal layer 51 and a second metal layer 52 stacked in sequence, the first metal layer 51 passes through the first passivation layer 40 and is electrically connected to the silicon substrate 20 to achieve effective collection and transmission of current, and the silver content of the second metal layer 52 is lower than that of the first metal layer 51, so as to reduce the silver consumption of the main gate electrode 31 and reduce the cost of the main gate electrode 31; the fine gate electrode 32 includes a third metal layer 53 and a fourth metal layer 54 stacked in sequence, and the silver content of the fourth metal layer 54 is lower than that of the third metal layer 53, so as to reduce the silver consumption of the fine gate electrode 32 and reduce the cost of the fine gate electrode 32; by designing the structures of the main gate electrode 31 and the fine gate electrode 32, the materials of each metal layer of the main gate electrode 31 and the fine gate electrode 32 are reasonably matched, so that the solar cell can reduce the silver consumption of the gate electrode 30 of the solar cell while ensuring efficient photoelectric conversion, reduce production costs, and enhance the market competitiveness of the solar cell.

[0053] Among them, the types of solar cells in the embodiments of the present application include but are not limited to Passivated Emitter Rear Cell (PERC), Tunnel Oxide Passivated Contact Cell (TOPCON), Heterojunction with Intrinsic Thin-layer (HJT), Back Contact Cell (BC), Perovskite Solar Cells (PSC), etc. The types of solar cells in this embodiment are not specifically limited.

[0054] For BC cells, the emitter, surface field and metal electrode are all set on the back of the cell and cross-distributed. The front of the cell uses SiN x / SiO x The double-layer anti-reflection passivation film removes the metal electrode from the front of the battery, allowing the battery to receive more incident light, reducing optical losses and improving photoelectric conversion efficiency.

[0055] For TOPCon cells, along the thickness direction, TOPCon cells include metal silver electrodes, front surface silicon nitride passivation layers, boron-doped emitters, N-type base silicon layers, diffused doping layers, ultra-thin silicon oxide, doped polysilicon, silicon nitride, and metal silver electrodes. The back of the cell is composed of an ultra-thin silicon oxide layer (1nm~2nm) and a phosphorus-doped microcrystalline amorphous mixed Si film, which together form a passivation contact structure. This structure can block the recombination of minority carrier holes and increase the open circuit voltage and short circuit current of the cell. The ultra-thin oxide layer allows majority electrons to tunnel into the polysilicon layer while blocking the recombination of minority carrier holes. The good passivation effect of ultra-thin silicon oxide and heavily doped silicon film causes the energy band on the silicon wafer surface to bend, thereby forming a field passivation effect, greatly increasing the probability of electron tunneling, and reducing the contact resistance, which increases the open circuit voltage and short circuit current of the cell, thereby improving the cell conversion efficiency.

[0056] For HJT cells, along the thickness direction, the HJT cells include a front low-temperature silver electrode, a front conductive film, an N-type amorphous silicon film, an intrinsic amorphous silicon film, an N-type base silicon layer, an intrinsic amorphous silicon film, a P-type amorphous silicon film, a back conductive film, and a back low-temperature silver electrode.

[0057] For PERC cells, along the thickness direction, the PERC cell includes a front surface metal silver electrode, a front surface silicon nitride passivation layer, a phosphorus layer emitter, a P-type base silicon layer, a local aluminum back field, a metal aluminum back electrode, a back passivation layer (Al2O3 / SiN x ). PERC cells use a passivation film to passivate the back side, replacing the all-aluminum back side field, enhancing the internal back reflection of light in the silicon substrate, reducing the recombination rate on the back side, and increasing the efficiency of the cell by 0.5%-1%.

[0058] For PSC cells, along the thickness direction, the perovskite cell includes substrate material, conductive film, electron transport layer (titanium dioxide), perovskite absorption layer (hole transport layer), and metal cathode. Perovskite materials have a high light absorption coefficient and a long carrier diffusion distance. After the photons absorbed by the perovskite material are converted into electrons, they are easily collected by the electrode with low loss, so they can generate higher photoelectric voltage and current, making the perovskite show a higher photoelectric conversion efficiency.

[0059] In some embodiments, reference Figure 1 , Figure 2 , Figure 4 , Figure 5 The first metal layer 51 of the main gate electrode 31 is made of a burn-through silver paste; the second metal layer 52 of the main gate electrode 31 is made of a solder paste.

[0060] The burn-through silver paste can penetrate the first passivation layer 40. Therefore, the first metal layer 51 of the main gate electrode 31 of this embodiment can burn through the first passivation layer 40 to form a contact window during production. The first metal layer 51 is electrically connected to the silicon substrate 20 through the contact window, thereby reducing the contact resistance between the first metal layer 51 and the silicon substrate 20, and improving the current collection efficiency of the main gate electrode 31. In this embodiment, the burn-through silver paste is used to produce the first metal layer 51 of the main gate electrode 31, and a good contact effect can be achieved with less silver paste.

[0061] The second metal layer 52 of the main grid electrode 31 is made of solder paste, which is a lower cost material commonly used in the solar cell manufacturing process. By using solder paste to replace part of the silver paste, the manufacturing cost of the main grid electrode 31 is significantly reduced. At the same time, the solder paste has good conductivity and good mechanical properties after curing. The second metal layer 52 can protect the first metal layer 51 made of silver underneath.

[0062] In this embodiment, the burn-through silver paste is used in combination with the solder paste to produce the first metal layer 51 and the second metal layer 52 of the main gate electrode 31, thereby optimizing the structure of the main gate electrode 31, ensuring that the main gate electrode 31 has good current collection efficiency and the solar cell has high photoelectric conversion efficiency, while effectively reducing the production cost, which is in line with the development trend of reducing costs and increasing efficiency in the photovoltaic industry.

[0063] In some embodiments, reference Figure 1 , Figure 2 , Figure 4 , Figure 5 The third metal layer 53 of the fine gate electrode 32 is made of a non-fire-through silver paste; the fourth metal layer 54 of the fine gate electrode 32 is made of a copper-containing paste or an aluminum-containing paste.

[0064] The fine gate electrode 32 is used to transmit current. The third metal layer 53 is made of non-burn-through silver paste and has good conductivity, which ensures the current transmission efficiency of the fine gate electrode 32 and does not need to penetrate the first passivation layer 40, thereby reducing the difficulty and cost of preparation.

[0065] The fourth metal layer 54 is made of a metal paste with a lower cost to reduce the silver consumption of the fine gate electrode 32, which can significantly reduce the manufacturing cost of the fine gate electrode 32. In this embodiment, the fourth metal layer 54 is made by using a copper-containing paste or an aluminum-containing paste to replace part of the silver paste. For example, the fourth metal layer 54 can be made of aluminum paste, copper paste, copper-aluminum paste, silver-copper paste, silver-aluminum paste, etc., so that the fourth metal layer 54 has good conductivity, and the fourth metal layer 54 also has good corrosion resistance and mechanical strength, which can ensure the stability and reliability of the fine gate electrode 32 during long-term use.

[0066] In some embodiments, reference Figure 1, Figure 2 , Figure 4 , Figure 5 , a thickness ratio of the first metal layer 51 to the second metal layer 52 is 3:1-1:3; illustratively, the thickness ratio of the first metal layer 51 to the second metal layer 52 can be 3:1, 2:1, 1:1, 1:2 or 1:3.

[0067] The thickness ratio of the third metal layer 53 to the fourth metal layer 54 is 3:1-1:3. For example, the thickness ratio of the third metal layer 53 to the fourth metal layer 54 may be 3:1, 2:1, 1:1, 1:2 or 1:3.

[0068] In this way, the gate electrode 30 has good conductivity, the solar cell has high photoelectric conversion efficiency, and at the same time, the silver consumption of the gate electrode 30 is reduced, thereby reducing the cost of the solar cell.

[0069] In some embodiments, the thickness of the first metal layer 51 is equal to that of the second metal layer 52 ; the thickness of the third metal layer 53 is equal to that of the fourth metal layer 54 .

[0070] In this embodiment, the thickness of the first metal layer 51 is half of the total thickness of the main gate electrode 31, the thickness of the second metal layer 52 is half of the total thickness of the main gate electrode 31; the thickness of the third metal layer 53 is half of the total thickness of the fine gate electrode 32, and the thickness of the fourth metal layer 54 is half of the total thickness of the fine gate electrode 32. According to the test, the photoelectric conversion efficiency of the solar cell in this embodiment is improved by about 0.05%.

[0071] In some embodiments, reference Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , the first metal layer 51 is electrically connected to the third metal layer 53 ; the fourth metal layer 54 covers the surface of the third metal layer 53 away from the silicon substrate 20 and the sidewalls other than the connection surface between the third metal layer 53 and the first metal layer 51 .

[0072] In this way, the first metal layer 51 and the third metal layer 53 are connected by a silver-silver layer, ensuring that the main gate electrode 31 and the fine gate electrode 32 have low contact resistance, which can reduce current transmission loss and is beneficial to improving the current collection ability of the solar cell. At the same time, the fourth metal layer 54 covers the surface of the third metal layer 53 away from the side of the silicon substrate 20 and the side walls other than the connection surface between the third metal layer 53 and the first metal layer 51, which can increase the contact area between the third metal layer 53 and the fourth metal layer 54, reduce the contact resistance of the fine gate electrode 32, and further reduce the current transmission loss of the fine gate electrode 32, further improve the current collection ability of the solar cell, and improve the photoelectric conversion efficiency.

[0073] In some embodiments, the solar cell of this embodiment is a back contact cell (BC cell), referring to Figure 2 , Figure 3 , Figure 4 , Figure 5 , the first surface 20a of the solar cell is the backlight surface; the first surface 20a of the silicon substrate 20 has a first area A1 and a second area A2 that are alternately distributed, and the conductivity types of the first area A1 and the second area A2 are opposite; a first gate line electrode 130 and a second gate line electrode 230 are arranged on the first passivation layer 40; the projection of the first gate line electrode 130 formed on the silicon substrate 20 falls on the first area A1, the first gate line electrode 130 includes a first main gate electrode 131 and a first fine gate electrode 132, and at least a part of the first main gate electrode 131 is electrically connected to the first area A1 through the first passivation layer 40; the projection of the second gate line electrode 230 formed on the silicon substrate 20 falls on the second area A2, the second gate line electrode 230 includes a second main gate electrode 231 and a second fine gate electrode 232, and at least a part of the second main gate electrode 231 is electrically connected to the second area A2 through the first passivation layer 40.

[0074] Specifically, the first surface 20a of the silicon substrate 20 is also covered with a tunneling layer 21, which is a silicon oxide layer. The first region A1 is also provided with a first semiconductor doping layer 22, and the second region A2 is provided with a second semiconductor doping layer 23, and the first semiconductor doping layer 22 and the second semiconductor doping layer 23 are both arranged on the side of the tunneling layer 21 away from the silicon substrate 20. The first passivation layer 40 covers the first semiconductor doping layer 22 and the second semiconductor doping layer 23 away from the tunneling layer 21. The first passivation layer 40 has a first contact window at the position of the first region A1, and the first passivation layer 40 has a second contact window at the position of the second region A2.

[0075] The first semiconductor doping layer 22 and the second semiconductor doping layer 23 have opposite conductivity types. For example, the first semiconductor doping layer 22 is a P-poly layer, and the second semiconductor doping layer 23 is an N-poly layer, and vice versa.

[0076] Reference Figure 2 , Figure 3 , Figure 4 , Figure 5 The first gate line electrode 130 is disposed on a side of the first passivation layer 40 away from the first semiconductor doping layer 22. The first gate line electrode 130 includes a first main gate electrode 131 and a first fine gate electrode 132. The first main gate electrode 131 extends along a first direction D1, and the first fine gate electrode 132 extends along a second direction D2 different from the first direction D1. The first main gate electrode 131 and the first fine gate electrode 132 are connected to form an interdigital structure. The first main gate electrode 131 is in contact with the first semiconductor doping layer 22 through a first contact window.

[0077] Reference Figure 2 , Figure 3 , Figure 4 , Figure 5 The second gate line electrode 230 is disposed on a side of the first passivation layer 40 away from the second semiconductor doping layer 23. The second gate line electrode 230 includes a second main gate electrode 231 and a second fine gate electrode 232. The second main gate electrode 231 extends along a first direction D1, and the second fine gate electrode 232 extends along a second direction D2 different from the first direction D1. The second main gate electrode 231 and the second fine gate electrode 232 are connected to form an interdigital structure. The second main gate electrode 231 is in contact with the second semiconductor doping layer 23 through a second contact window.

[0078] The first gate line electrode 130 and the second gate line electrode 230 both have the structure of the gate electrode in the above embodiment, the first main gate electrode 131 and the second main gate electrode 231 both include a stacked first metal layer 51 and a second metal layer 52, and the first fine gate electrode 132 and the second fine gate electrode 232 both include a stacked third metal layer 53 and a fourth metal layer 54.

[0079] The back contact battery of this embodiment reduces the silver consumption of the first gate line electrode 130 and the second gate line electrode 230, reduces the production cost of the back contact battery, and overcomes the problem that the high production cost of the back contact battery is not conducive to large-scale industrial production.

[0080] According to an exemplary embodiment, the present disclosure provides a method for manufacturing a solar cell, such as Figure 6 As shown, the method for manufacturing a solar cell of this embodiment includes the following steps:

[0081] Step S101: providing a silicon substrate, wherein a first passivation layer is formed on a first surface of the silicon substrate.

[0082] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 In this embodiment, a silicon substrate 20 is used to make a solar cell. In other embodiments, a germanium silicon substrate 20 or a germanium substrate or other semiconductor material substrate can also be used to make a cell. The silicon substrate 20 can be an N-type substrate or a P-type substrate.

[0083] A first passivation layer 40 is formed on the first surface 20 a of the silicon substrate 20 . The first passivation layer 40 is used to protect the silicon substrate 20 and reduce the surface recombination loss of the silicon substrate 20 , which is beneficial to improving the photoelectric conversion efficiency and stability of the solar cell.

[0084] The first passivation layer 40 may include at least one of an aluminum oxide layer, a silicon oxide layer, and a silicon nitride layer, or the first passivation layer 40 may include a stacked plurality of layers. For example, the first passivation layer 40 may include an aluminum oxide layer and a silicon nitride layer sequentially stacked on the first surface 20a of the silicon substrate 20.

[0085] The aluminum oxide layer can effectively prevent the impurities and moisture in the external environment from corroding the inside of the battery. At the same time, aluminum oxide can also reduce the number of dangling bonds on the surface of the silicon substrate 20, thereby reducing the surface recombination rate and increasing the open circuit voltage and short circuit current of the battery. The silicon nitride layer has good insulation properties and corrosion resistance, and can further reduce the recombination loss on the surface of the silicon substrate 20.

[0086] Reference Figure 4 , Figure 5 As shown, the second surface of the silicon substrate 20 opposite to the first surface 20 a is covered with a second passivation layer 60 . By way of example, the second passivation layer 600 may include an aluminum oxide layer and a silicon nitride layer stacked in sequence.

[0087] Step S102: printing a burn-through silver paste on the first passivation layer, and drying the burn-through silver paste to form a first metal layer.

[0088] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 The burn-through silver paste is printed in the region of the main gate electrode 31 on the first passivation layer 40. The burn-through silver paste can penetrate the first passivation layer 40 in the subsequent sintering process to be electrically connected to the silicon substrate 20. Then, the burn-through silver paste is dried at a temperature of 250° C. to 300° C. to remove the solvent and water in the paste, thereby forming the first metal layer 51.

[0089] Step S103: printing a non-fire-through type silver paste on the first passivation layer, and drying the non-fire-through type silver paste to form a third metal layer.

[0090] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 A non-fire-through silver paste is printed in the region of the fine gate electrode 32 on the first passivation layer 40 . After printing, the non-fire-through silver paste is dried at a temperature of 250° C.-300° C. to form a third metal layer 53 .

[0091] Step S104: laser sintering the first metal layer and the third metal layer so that the first metal layer is electrically connected to the third metal layer, and the first metal layer is at least partially electrically connected to the silicon substrate through the first passivation layer.

[0092] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 In this embodiment, parameters such as the energy density, pulse width and frequency of the laser beam are selected according to the material and thickness of the first metal layer 51 and the second metal layer 52, and the first metal layer 51 and the third metal layer 53 are sintered by irradiating the laser beam. During the sintering process, the laser beam will quickly heat the first metal layer 51 and the second metal layer 52, causing them to melt and form good contact with the adjacent metal layers. At the same time, through laser sintering, one end face of the third metal layer 53 is electrically connected to the first metal layer 51.

[0093] At the same time, laser sintering can also allow the first metal layer 51 to at least partially pass through the first passivation layer 40, forming a contact window in the first passivation layer 40. The first metal layer 51 is electrically connected to the silicon substrate 20 through the contact window, which can improve the current collection efficiency of the main gate electrode 31.

[0094] Step S105: printing solder paste on the first metal layer, and drying the solder paste to form a second metal layer, wherein the content of silver element in the second metal layer is lower than the content of silver element in the first metal layer; the first metal layer and the second metal layer form a main gate electrode.

[0095] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , solder paste is printed on the first metal layer 51, and after printing, it is dried at 250°C-300°C to form the second metal layer 52 on the first metal layer 51. The solder paste has good conductivity and good mechanical properties after curing. The second metal layer 52 can protect the first metal layer 51 made of silver underneath.

[0096] Step S106: printing copper-containing paste or aluminum-containing paste on the third metal layer, and drying the copper-containing paste or aluminum-containing paste to form a fourth metal layer, wherein the content of silver element in the fourth metal layer is lower than the content of silver element in the third metal layer; the third metal layer and the fourth metal layer form a fine gate electrode, and the main gate electrode and the fine gate electrode form a gate line electrode.

[0097] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5, a tin paste containing copper or aluminum is printed on the first metal layer 51. For example, aluminum paste, copper paste, copper-aluminum paste, silver-copper paste, silver-aluminum paste and other metal pastes with lower costs can be printed. Then, the paste is dried to form a fourth metal layer 54. The drying temperature can be 250°C-300°C. The fourth metal layer 54 has good conductivity, and the fourth metal layer 54 also has good corrosion resistance and mechanical strength, which can ensure the stability and reliability of the fine gate electrode 32 during long-term use.

[0098] The manufacturing method of the solar cell of the present embodiment optimizes the manufacturing process, and the main gate electrode 31 formed includes a stacked first metal layer 51 and a second metal layer 52. The first metal layer 51 is electrically connected to the silicon substrate 20, and the contact resistance between the first metal layer 51 and the silicon substrate 20 is reduced, which can improve the current collection efficiency of the main gate electrode 31. The content of silver element in the second metal layer 52 is lower than the content of silver element in the first metal layer 51, which reduces the manufacturing cost of the main gate electrode 31. The fine gate electrode 32 formed in the present embodiment includes a stacked third metal layer 53 and a fourth metal layer 54. The third metal layer 53 forms a silver-silver layer connection with the first metal layer 51, ensuring that the main gate electrode 31 and the fine gate electrode 32 have low contact resistance, which can reduce current transmission loss and is beneficial to improving the current collection ability of the solar cell. The content of silver element in the fourth metal layer 54 is lower than the content of silver element in the third metal layer 53, which reduces the manufacturing cost of the fine gate electrode 32. The total silver consumption of the solar cell can be reduced by 30%-40%, which greatly saves the manufacturing cost and is beneficial to improving the market competitiveness of the solar cell.

[0099] In some embodiments, the thickness ratio of the first metal layer 51 to the second metal layer 52 is 3:1-1:3; illustratively, the thickness ratio of the first metal layer 51 to the second metal layer 52 may be 3:1, 2:1, 1:1, 1:2 or 1:3.

[0100] The thickness ratio of the third metal layer 53 to the fourth metal layer 54 is 3:1-1:3. For example, the thickness ratio of the third metal layer 53 to the fourth metal layer 54 may be 3:1, 2:1, 1:1, 1:2 or 1:3.

[0101] In this way, the gate electrode 30 has good conductivity, the solar cell has high photoelectric conversion efficiency, and at the same time, the silver consumption of the gate electrode 30 is reduced, thereby reducing the cost of the solar cell.

[0102] In some embodiments, the thickness of the first metal layer 51 is equal to that of the second metal layer 52 ; the thickness of the third metal layer 53 is equal to that of the fourth metal layer 54 .

[0103] In this embodiment, the thickness of the first metal layer 51 is half of the total thickness of the main gate electrode 31, the thickness of the second metal layer 52 is half of the total thickness of the main gate electrode 31; the thickness of the third metal layer 53 is half of the total thickness of the fine gate electrode 32, and the thickness of the fourth metal layer 54 is half of the total thickness of the fine gate electrode 32. According to the test, the photoelectric conversion efficiency of the solar cell in this embodiment is improved by about 0.05%.

[0104] In some embodiments, when printing the copper-containing paste or the aluminum-containing paste on the third metal layer 53, the copper-containing paste or the aluminum-containing paste covers the surface of the third metal layer 53 away from the silicon substrate 20 and the sidewalls other than the connection surface between the third metal layer 53 and the first metal layer 51. In this way, the fourth metal layer 54 covers the surface of the third metal layer 53 away from the silicon substrate 20 and the sidewalls other than the connection surface between the third metal layer 53 and the first metal layer 51, which can increase the contact area between the third metal layer 53 and the fourth metal layer 54, reduce the contact resistance of the fine gate electrode 32, further reduce the current transmission loss of the fine gate electrode 32, further improve the current collection capacity of the solar cell, and improve the photoelectric conversion efficiency.

[0105] In some embodiments, the method for manufacturing a solar cell of this embodiment is as follows: Figure 7 As shown, and refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 As shown, the battery of this embodiment is a back contact battery (BC battery), and the manufacturing method of this embodiment includes the following steps:

[0106] Step S201: providing a silicon substrate, wherein a first passivation layer is formed on a first surface of the silicon substrate, the first surface is a backlight surface, and the first surface has first regions and second regions that are alternately distributed, and the first regions and the second regions have opposite conductivity types.

[0107] The silicon substrate 20 may be an N-type substrate or a P-type substrate, and the first surface 20a of the silicon substrate 20 is a backlight surface. The first region A1 is stacked with a tunneling layer 21, a first semiconductor doping layer 22, and a first passivation layer 40 on a side away from the silicon substrate 20, and the second region A2 is stacked with a tunneling layer 21, a second semiconductor doping layer 23, and a first passivation layer 40 on a side away from the silicon substrate 20.

[0108] In this embodiment, the conductivity types of the first region A1 and the second region A2 are opposite, which means that the conductivity types of the first semiconductor doping layer 22 and the second semiconductor doping layer 23 are opposite. For example, the first semiconductor doping layer 22 is a P-poly layer and the second semiconductor doping layer 23 is an N-poly layer, and vice versa.

[0109] For example, the tunneling layer 21 is a silicon oxide layer.

[0110] For example, the first passivation layer 40 may include an aluminum oxide layer and a silicon nitride layer stacked in sequence.

[0111] Step S202: printing a burn-through silver paste on the first passivation layer of the first region and on the first passivation layer of the second region respectively, drying the burn-through silver paste, and forming a first metal layer on the first region and on the second region respectively.

[0112] The burn-through silver paste is printed in the first area A1 and the second area A2 respectively, and after drying, the first metal layer 51 of the first main gate electrode 131 and the first metal layer 51 of the second main gate electrode 231 are formed in the first area A1. The first metal layer 51 of the first main gate electrode 131 and the first metal layer 51 of the second main gate electrode 231 both extend along the first direction D1.

[0113] Step S203: printing a non-fire-through type silver paste on the first passivation layer in the first region, drying the non-fire-through type silver paste, and forming a third metal layer on the first region.

[0114] The third metal layer 53 of the first fine gate electrode 132 is formed in the first area A1, and the third metal layer 53 of the first fine gate electrode 132 extends along a second direction D2 different from the first direction D1. The first metal layer 51 of the first main gate electrode 131 and the third metal layer 53 of the first fine gate electrode 132 are arranged in an interdigitated shape.

[0115] Step S204: printing a non-fire-through type silver paste on the first passivation layer in the second region, drying the non-fire-through type silver paste, and forming a third metal layer on the second region.

[0116] The third metal layer 53 of the second fine gate electrode 232 is formed in the second area A2, and the third metal layer 53 of the second fine gate electrode 232 extends along a second direction D2 different from the first direction D1. The first metal layer 51 of the second main gate electrode 231 and the third metal layer 53 of the second fine gate electrode 232 are arranged in an interdigitated shape.

[0117] Step S205: laser sintering the first metal layer and the third metal layer on the first region and the first metal layer and the third metal layer on the second region, so that the first metal layer in the first region is electrically connected to the third metal layer in the first region, a partial area of ​​the first metal layer in the first region burns through the first passivation layer and is electrically connected to the first region, and at the same time, the third metal layer in the second region is electrically connected to the first metal layer in the second region, and a partial area of ​​the first metal layer in the second region burns through the first passivation layer and is electrically connected to the second region.

[0118] The first metal layer 51 and the second metal layer 52 are laser sintered to electrically connect the first metal layer 51 of the first main gate electrode 131 and the third metal layer 53 of the first fine gate electrode 132 , and to electrically connect the first metal layer 51 of the second main gate electrode 231 and the third metal layer 53 of the second fine gate electrode 232 .

[0119] At the same time, the first metal layer 51 of the first main gate electrode 131 at least partially burns through the first passivation layer 40, forming a first contact window in the first passivation layer 40, and the first main gate electrode 131 is in contact with the first semiconductor doping layer 22 through the first contact window. The first metal layer 51 of the second main gate electrode 231 at least partially burns through the first passivation layer 40, forming a second contact window in the first passivation layer 40, and the second main gate electrode 231 is in contact with the second semiconductor doping layer 23 through the second contact window.

[0120] Step S206: printing solder paste on the first metal layer of the first region and the first metal layer of the second region respectively, and drying the solder paste to form a second metal layer; the content of silver element in the second metal layer is lower than the content of silver element in the first metal layer; the first metal layer and the second metal layer of the first region form a first main gate electrode, and the first metal layer and the second metal layer of the second region form a second main gate electrode.

[0121] The second metal layer 52 of the first main gate electrode 131 is formed on the first metal layer 51 of the first main gate electrode 131 , and the second metal layer 52 of the second main gate electrode 231 is formed on the first metal layer 51 of the second main gate electrode 231 , so as to form the first main gate electrode 131 and the second main gate electrode 231 .

[0122] Step S207: printing copper-containing paste or aluminum-containing paste on the third metal layer of the first region, and drying the copper-containing paste or aluminum-containing paste to form a fourth metal layer, wherein the content of silver element in the fourth metal layer is lower than the content of silver element in the third metal layer; the third metal layer and the fourth metal layer of the first region form a first fine gate electrode, and the first main gate electrode and the first fine gate electrode form a first gate line electrode.

[0123] Step S208: printing copper-containing paste or aluminum-containing paste on the third metal layer in the second area, and drying the copper-containing paste or aluminum-containing paste to form a fourth metal layer; the third metal layer and the fourth metal layer in the second area form a second fine gate electrode, and the second main gate electrode and the second fine gate electrode form a second gate line electrode.

[0124] The method for manufacturing a solar cell of the present embodiment manufactures a back-contact cell, which ensures that the back-contact cell has a high photoelectric conversion efficiency. The main grid electrode 31 and the fine grid electrode 32 of the first grid line electrode 130 and the second grid line electrode 230 are made of a silver layer and a lower-cost metal layer structure, which reduces the use of high-cost silver paste in the back-contact cell, reduces the total silver consumption by 30%-40%, and improves the photoelectric conversion efficiency by about 0.05%, which greatly saves the production cost and overcomes the problem that the high production cost of the back-contact cell is not conducive to large-scale industrial production.

[0125] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0126] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A solar cell, characterized in that: include: A silicon substrate, wherein a first passivation layer is provided on a first surface of the silicon substrate; A gate line electrode, disposed on the first passivation layer, the gate line electrode comprising a main gate electrode and a fine gate electrode electrically connected to the main gate electrode; The main gate electrode comprises a first metal layer and a second metal layer stacked in sequence; the first metal layer at least partially passes through the first passivation layer to be electrically connected to the silicon substrate, and the content of silver element in the second metal layer is lower than the content of silver element in the first metal layer; The fine gate electrode includes a third metal layer and a fourth metal layer, and the content of silver element in the fourth metal layer is lower than the content of silver element in the third metal layer.

2. The solar cell according to claim 1, characterized in that The first metal layer is made of burn-through silver paste; the second metal layer is made of solder paste; The third metal layer is made of non-fire-through silver paste; the fourth metal layer is made of copper-containing paste or aluminum-containing paste.

3. The solar cell according to claim 1, characterized in that The thickness ratio of the first metal layer to the second metal layer is 3:1-1:3; the thickness ratio of the third metal layer to the fourth metal layer is 3:1-1:

3.

4. The solar cell according to claim 3, characterized in that: The thickness of the first metal layer is equal to that of the second metal layer; the thickness of the third metal layer is equal to that of the fourth metal layer.

5. The solar cell according to claim 1, characterized in that: The first metal layer is electrically connected to the third metal layer; the fourth metal layer covers the surface of the third metal layer away from the silicon substrate and the sidewalls other than the connection surface between the third metal layer and the first metal layer.

6. The solar cell according to claim 1, characterized in that The battery is a back contact battery, and the first surface is a backlight surface; the first surface of the silicon substrate has a first area and a second area that are alternately distributed, and the first area and the second area have opposite conductivity types; a first gate line electrode and a second gate line electrode are arranged on the first passivation layer; The projection of the first gate line electrode on the silicon substrate falls on the first region, the first gate line electrode comprises a first main gate electrode and a first fine gate electrode, and at least a portion of the first main gate electrode penetrates the first passivation layer and is electrically connected to the first region; The projection of the second gate line electrode on the silicon substrate falls on the second region. The second gate line electrode includes a second main gate electrode and a second fine gate electrode. At least a portion of the second main gate electrode is electrically connected to the second region through the first passivation layer.

7. A method for manufacturing a solar cell, characterized in that: include: Providing a silicon substrate, wherein a first passivation layer is formed on a first surface of the silicon substrate; Printing a burn-through silver paste on the first passivation layer, and drying the burn-through silver paste to form a first metal layer; Printing a non-burn-through silver paste on the first passivation layer, and drying the non-burn-through silver paste to form a third metal layer; Laser sintering the first metal layer and the third metal layer so that the first metal layer is electrically connected to the third metal layer, and the first metal layer is at least partially electrically connected to the silicon substrate through the first passivation layer; Printing solder paste on the first metal layer, and drying the solder paste to form a second metal layer, wherein the content of silver element in the second metal layer is lower than the content of silver element in the first metal layer; the first metal layer and the second metal layer form a main gate electrode; A copper-containing paste or an aluminum-containing paste is printed on the third metal layer, and the copper-containing paste or the aluminum-containing paste is dried to form a fourth metal layer, wherein the content of silver element in the fourth metal layer is lower than the content of silver element in the third metal layer; the third metal layer and the fourth metal layer form a fine gate electrode, and the main gate electrode and the fine gate electrode form a gate line electrode.

8. The method for manufacturing a solar cell according to claim 7, characterized in that: The thickness ratio of the first metal layer to the second metal layer is 3:1-1:3; the thickness ratio of the third metal layer to the fourth metal layer is 3:1-1:

3.

9. The method for manufacturing a solar cell according to claim 7, characterized in that: When printing copper-containing paste or aluminum-containing paste on the third metal layer, the copper-containing paste or aluminum-containing paste covers the surface of the third metal layer away from the silicon substrate and the sidewalls other than the connection surface between the third metal layer and the first metal layer.

10. The method for manufacturing a solar cell according to claim 7, characterized in that: The battery is a back contact battery, and the manufacturing method comprises: Providing a silicon substrate, wherein a first passivation layer is formed on a first surface of the silicon substrate, the first surface is a backlight surface, the first surface has first regions and second regions that are alternately distributed, and the first regions and the second regions have opposite conductivity types; Printing a burn-through silver paste on the first passivation layer in the first region and on the first passivation layer in the second region respectively, drying the burn-through silver paste, and forming a first metal layer on the first region and the second region respectively; Printing a non-fire-through silver paste on the first passivation layer in the first region, drying the non-fire-through silver paste, and forming a third metal layer on the first region; Printing a non-fire-through silver paste on the first passivation layer in the second region, drying the non-fire-through silver paste, and forming a third metal layer on the second region; Laser sintering the first metal layer and the third metal layer on the first region and the first metal layer and the third metal layer on the second region, so that the first metal layer in the first region is electrically connected to the third metal layer in the first region, a partial region of the first metal layer in the first region is burned through the first passivation layer and is electrically connected to the first region, and at the same time, the third metal layer in the second region is electrically connected to the first metal layer in the second region, and a partial region of the first metal layer in the second region is burned through the first passivation layer and is electrically connected to the second region; Solder paste is printed on the first metal layer of the first region and the first metal layer of the second region respectively, and the solder paste is dried to form a second metal layer; the content of silver element in the second metal layer is lower than the content of silver element in the first metal layer; the first metal layer and the second metal layer of the first region form a first main gate electrode, and the first metal layer and the second metal layer of the second region form a second main gate electrode; Printing a copper-containing paste or an aluminum-containing paste on the third metal layer of the first region, drying the copper-containing paste or the aluminum-containing paste to form a fourth metal layer, wherein the content of silver element in the fourth metal layer is lower than the content of silver element in the third metal layer; the third metal layer and the fourth metal layer of the first region form a first fine gate electrode, and the first main gate electrode and the first fine gate electrode form a first gate line electrode; Print copper-containing paste or aluminum-containing paste on the third metal layer in the second area, and dry the copper-containing paste or aluminum-containing paste to form a fourth metal layer; the third metal layer and the fourth metal layer in the second area form a second fine gate electrode, and the second main gate electrode and the second fine gate electrode form a second gate line electrode.

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