Method and device for preparing metallized grid line of heterojunction solar cell

Abstract

The invention relates to the technical field of preparation of a grid line of a heterojunction solar cell, in particular to a preparation method and device of a metallized grid line of the heterojunction solar cell, and the method specifically comprises the steps: carrying out the texturing of the front surface and the back surface of a monocrystalline silicon wafer, and forming a pyramid textured structure; cleaning the textured silicon wafer to form a clean surface state; respectively depositing silicon films on the front surface and the back surface of the cleaned silicon wafer, and then sequentially depositing a transparent conductive oxide layer film and a metal layer film; copper wires are laid on the front face and the back face of the silicon wafer after the metal layer thin film is prepared to serve as grid line electrodes, the silicon wafer with the prepared grid line electrodes is placed in an oxidizing acid solution, and the heterojunction solar cell piece with the grid line electrodes with different patterns on the front face and the back face is obtained. The cost is reduced by more than 70%, electroplating equipment is not needed, wastewater is not generated, additional equipment investment is not increased, and the method has a great mass production prospect.

Description

Technical Field

[0001] The present invention relates to the technical field of grid line preparation for heterojunction solar cells, and in particular to a method and a device for preparing metallized grid lines for heterojunction solar cells. Background Art

[0002] Heterojunction solar cells have attracted widespread attention in the industry for their high efficiency and low attenuation performance. However, the high cost of heterojunction solar cells due to the need to use low-temperature silver paste as the grid line has always limited their further large-scale production. In order to reduce the cost of preparing the metallized grid lines of heterojunction solar cells, copper electroplating technology for preparing copper grid lines has been introduced. The existing technology of using copper electroplating to prepare copper grid lines requires a large amount of equipment, and the complex production process reduces the production yield and also increases the equipment investment cost. In addition, copper electroplating produces a large amount of copper-containing wastewater, which causes greater environmental pressure. Therefore, the technology of copper electroplating to prepare copper grid lines has always been limited and has not been widely promoted, becoming a major problem in the development of heterojunction solar cell production. Summary of the Invention

[0003] The present invention aims to at least improve one of the technical problems existing in the prior art. To this end, the present invention provides a method and apparatus for preparing metallized grid lines of heterojunction solar cells.

[0004] The method for preparing a metallized grid line of a heterojunction solar cell according to the first embodiment of the present invention comprises the following steps: Step S1, texturing the front and back surfaces of a single crystal silicon wafer to form a pyramid textured structure; Step S2, cleaning the silicon wafer after texturing to remove metal impurities on the surface of the silicon wafer, and finally removing the surface oxide layer of the silicon wafer with hydrofluoric acid to form a clean surface state; Step S3, depositing silicon thin films on the front and back of the cleaned silicon wafer: depositing an intrinsic amorphous silicon layer and a doped amorphous silicon layer or a microcrystalline silicon thin film on the front of the silicon wafer in sequence; and depositing an intrinsic amorphous silicon layer and a doped amorphous silicon layer or a microcrystalline silicon thin film on the back of the silicon wafer in sequence; Step S4, depositing a transparent conductive oxide layer and a metal layer in sequence on the front surface of the silicon wafer after the amorphous silicon layer is deposited by physical vapor deposition; Step S5, depositing a transparent conductive oxide layer and a metal layer in sequence on the back side of the silicon wafer after the amorphous silicon layer is deposited by physical vapor deposition; Step S6: laying copper wires as front fine gate electrodes on the front surface of the silicon wafer after the metal layer film is formed. Then, 5 to 20 identical copper wires are laid in a direction perpendicular to the fine gate electrodes as front main gate electrodes. A mold is used to apply pressure and temperature to the copper wires on the surface of the silicon wafer. Under the dual effects of pressure and temperature, the tin layer on the surface of the copper wires and the metal layer on the surface of the silicon wafer are melted and welded together to form ohmic contacts to reduce contact resistance. Step S7: laying copper wires as back-side fine gate electrodes on the back side of the silicon wafer after the metal layer is formed. Then, 5 to 20 identical copper wires are laid in a direction perpendicular to the fine gate electrodes as back-side main gate electrodes. A mold is used to apply pressure and temperature to the copper wires on the surface of the silicon wafer. Under the dual effects of pressure and temperature, the tin layer on the surface of the copper wires and the metal layer on the surface of the silicon wafer are melted and welded together to form an ohmic contact to reduce contact resistance. In step S8, the silicon wafer with the front and back gate electrodes prepared is placed in an oxidizing acid solution to etch away the metal layer other than the gate electrodes, thereby forming a complete heterojunction solar cell with front and back gate electrodes of different patterns, thus completing the preparation process of the metallized gate electrodes of the heterojunction solar cell. According to the method for preparing the metallized grid lines of heterojunction solar cells according to the embodiments of the present invention, low-cost copper metal replaces expensive silver paste to achieve a silver-free processing design for the metallized grid lines of heterojunction solar cells. This not only reduces costs by more than 70%, but also does not require the use of electroplating equipment and does not generate wastewater. There is no additional equipment investment, and it has great prospects for mass production.

[0005] In a possible implementation of the first aspect, the copper wire in step S6 and step S7 is composed of a copper wire whose surface is protected by a tin layer, and the diameter of the copper wire is 5um-40um. The front fine gate electrode is paved with 50-200 copper wires for balancing the shading performance of the gate line and the conductivity of the gate line. If the number of gate lines is less than 50, the conductivity is insufficient, which will eventually lead to a decrease in battery efficiency; if the number of gate lines is greater than 200, the shading area of ​​the gate lines is too large, which will cause the current to decrease, and ultimately lead to a decrease in battery efficiency.

[0006] In a possible implementation manner of the first aspect, the copper wire is in any one of a circular, square, and triangular shape.

[0007] In a possible implementation of the first aspect, the copper wire diameter of the main gate electrode in step S6 and step S7 is 30-100 μm, which increases the shading area, ensures the battery efficiency, and reduces the production cost.

[0008] In a possible implementation of the first aspect, the pressure in step S6 and step S7 is 0.5N-10N, the temperature is 150°C-300°C, and the heating time is 10s-50s; thereby ensuring battery efficiency while improving product yield.

[0009] In a possible implementation of the first aspect, the acid solution in step S8 includes hydrochloric acid and / or sulfuric acid aqueous solution, the concentration of the acid solution is 1%-10%, and the etching time is 10s-60s; the cleaning is more thorough while improving the battery efficiency.

[0010] In a possible implementation of the first aspect, the transparent conductive oxide layer film in step S4 and step S5 is any one of an indium tin oxide layer, an element-doped indium oxide composite layer, and a zinc oxide material doped with aluminum or boron, and the thickness of the transparent conductive oxide layer film is 50 nm-200 nm; if the thickness is less than 50 nm, a good anti-reflection effect cannot be formed, and the conductivity is insufficient, which will eventually cause a decrease in battery efficiency; if the thickness is greater than 200 nm, excessive production costs are wasted, and too long a deposition time will also waste production capacity, which is not conducive to mass production.

[0011] In a possible implementation of the first aspect, the metal layer film in step S4 and step S5 is an alloy of one or more of copper, tin, nickel, and silver, and the thickness of the metal layer film is 50nm-300nm; if the thickness is less than 50nm, it is easy to burn through in the subsequent lamination process, destroying the transparent conductive layer, and ultimately reducing the battery efficiency; if the thickness is greater than 300nm, it will make subsequent acid etching difficult, easily produce residue, cause product defects, and also increase production costs.

[0012] In a possible implementation of the first aspect, in step S3, an intrinsic amorphous silicon layer and an doped amorphous silicon layer or a microcrystalline silicon film are deposited on the front and back sides of the silicon wafer by chemical vapor deposition; the main function of the film is to passivate the dangling bonds on the surface of the silicon wafer to reduce the defect density, and at the same time act as an emitter and electron collection layer to transmit the current generated by the silicon wafer to the electrode.

[0013] According to the second embodiment of the present invention, the device for preparing metallized grid lines for heterojunction solar cells performs the above-mentioned method for preparing metallized grid lines for heterojunction solar cells to prepare metallized grid lines for heterojunction solar cells.

[0014] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 The present invention is a flow chart of a method for preparing a metallized grid line of a heterojunction solar cell according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0018] It should be noted that when an element is referred to as being “fixed to” another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or there may be an intermediate element.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0020] Example 1 See Figure 1 As shown, this embodiment provides a method for preparing a metallized grid line of a heterojunction solar cell, which includes the following steps: Step S1, texturing the front and back surfaces of a single crystal silicon wafer to form a pyramid texture structure to reduce the surface reflectivity of the silicon wafer; Step S2, cleaning the silicon wafer after texturing to remove metal impurities on the surface of the silicon wafer, and finally removing the surface oxide layer of the silicon wafer with hydrofluoric acid to form a clean surface state; Step S3, depositing silicon thin films on the front and back of the cleaned silicon wafer: depositing an intrinsic amorphous silicon layer and a doped amorphous silicon layer or a microcrystalline silicon thin film on the front of the silicon wafer in sequence; and depositing an intrinsic amorphous silicon layer and a doped amorphous silicon layer or a microcrystalline silicon thin film on the back of the silicon wafer in sequence; Step S4, depositing a transparent conductive oxide layer and a metal layer in sequence on the front surface of the silicon wafer after the amorphous silicon layer is deposited by physical vapor deposition; Step S5, depositing a transparent conductive oxide layer and a metal layer in sequence on the back side of the silicon wafer after the amorphous silicon layer is deposited by physical vapor deposition; Step S6, preparing a gate line electrode on the front side of the silicon wafer after the metal layer film is prepared, specifically, laying a copper wire on the front side of the silicon wafer as a front fine gate electrode, wherein the copper wire refers to a copper wire with a tin-plated layer on the surface to be protected; then laying 5 to 20 identical copper wires in a direction perpendicular to the fine gate electrode as the front main gate electrode; finally, using a mold to apply a certain pressure and temperature to the copper wire on the surface of the silicon wafer, under the dual effects of pressure and temperature, the tin layer on the surface of the copper wire and the metal layer on the surface of the silicon wafer are melted and welded together to form an ohmic contact to reduce contact resistance; Step S7, preparing a gate line electrode on the back side of the silicon wafer after the metal layer is prepared, specifically, laying a copper wire on the back side of the silicon wafer as a back side fine gate electrode, then laying 5 to 20 identical copper wires in a direction perpendicular to the fine gate electrode as a back side main gate electrode, and finally using a mold to apply a certain pressure and temperature to the copper wire on the surface of the silicon wafer. Under the dual effects of pressure and temperature, the tin layer on the surface of the copper wire and the metal layer on the surface of the silicon wafer are melted and welded together to form an ohmic contact to reduce contact resistance; In step S8, the silicon wafer with the front and back gate electrodes prepared is placed in an acid solution with a certain oxidizing property to cleanly etch the metal layer other than the gate lines, thereby forming a complete heterojunction solar cell with front and back gate electrodes of different patterns, thereby completing the preparation process of the metallized gate lines of the heterojunction solar cell. According to the method for preparing the metallized grid lines of heterojunction solar cells according to the embodiments of the present invention, low-cost copper metal replaces expensive silver paste to achieve a silver-free processing design for the metallized grid lines of heterojunction solar cells. This not only reduces costs by more than 70%, but also does not require the use of electroplating equipment and does not generate wastewater. There is no additional equipment investment, and it has great prospects for mass production.

[0021] It should be noted that the copper wire in step S6 and step S7 is composed of copper wire with a tin layer on the surface for protection, and the diameter of the copper wire is 5um-40um. The front fine gate electrode is paved with 50-200 copper wires for balancing the light shielding and electrical conductivity of the gate wires. If the number of gate wires is less than 50, the conductivity is insufficient, which will eventually lead to a decrease in battery efficiency; if the number of gate wires is greater than 200, the light shielding area of ​​the gate wires is too large, which will cause the current to decrease, and ultimately lead to a decrease in battery efficiency.

[0022] It should be noted that the copper wire is in any of the shapes of circle, square and triangle.

[0023] It should be noted that the copper wire diameter of the main grid electrode in step S6 and step S7 is 30-100um, which increases the shading area to ensure battery efficiency while reducing production costs. The main grid serves as the final current outlet. If the diameter is less than 30um, the copper wire resistance is too large, resulting in a large efficiency loss; if the diameter is greater than 100um, the shading area and production cost will increase, which is not conducive to mass production.

[0024] It should be noted that the pressure in steps S6 and S7 is 0.5N-10N, the temperature is 150°C-300°C, and the heating time is 10s-50s; ensuring battery efficiency while improving product yield. Pressure, temperature, and time are key parameters in the lamination process. If the parameters are not within this range, the copper wire and metal layer will not be tightly bonded, resulting in high contact resistance and low battery efficiency. If the pressure is too high or the temperature is too high, the battery cell will break and the silicon film passivation effect will fail, which will seriously increase the production defect rate and reduce efficiency. Therefore, the process parameters need to be strictly controlled within this range.

[0025] It should be noted that the acid solution in step S8 comprises an aqueous solution of hydrochloric acid and / or sulfuric acid, with a concentration of 1%-10% and an etching time of 10s-60s; this provides a more thorough cleaning while improving battery efficiency. If the acid concentration or etching time is insufficient, it will be difficult to completely remove the metal layer other than the copper wire, resulting in an increase in the light-shielding area, a decrease in current, and ultimately a decrease in battery efficiency. If the concentration and etching time are too high, excessive corrosion will occur, damaging the transparent conductive film and silicon thin film layer on the surface of the silicon cell, which will also cause a serious decrease in cell efficiency.

[0026] It should be noted that the transparent conductive oxide layer film in step S4 and step S5 is any one of an indium tin oxide layer, an element-doped indium oxide composite layer, and a zinc oxide material doped with aluminum or boron, and the thickness of the transparent conductive oxide layer film is 50nm-200nm; if the thickness is less than 50nm, a good anti-reflection effect cannot be formed, and the conductivity is insufficient, which will eventually cause a decrease in battery efficiency; if the thickness is greater than 200nm, excessive production costs will be wasted, and too long a deposition time will also waste production capacity, which is not conducive to mass production.

[0027] It should be noted that the metal layer film in step S4 and step S5 is an alloy of one or more of copper, tin, nickel, and silver, and the thickness of the metal layer film is 50nm-300nm; if the thickness is less than 50nm, it is easy to burn through in the subsequent lamination process, destroying the transparent conductive layer and ultimately reducing the battery efficiency; if the thickness is greater than 300nm, it will make subsequent acid etching difficult, easily produce residues, cause product defects, and also increase production costs.

[0028] It should be noted that in step S3, chemical vapor deposition is used to deposit an intrinsic amorphous silicon layer and an doped amorphous silicon layer or a microcrystalline silicon film on the front and back of the silicon wafer; the main function of the film is to passivate the dangling bonds on the surface of the silicon wafer to reduce the defect density, and at the same time act as an emitter and electron collection layer to transmit the current generated by the silicon wafer to the electrode.

[0029] Example 2 This embodiment provides a device for preparing metallized grid lines for heterojunction solar cells, wherein the device performs the above-mentioned method for preparing metallized grid lines for heterojunction solar cells to prepare metallized grid lines for heterojunction solar cells.

[0030] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as a limitation to the invention.

[0031] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0032] Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments. Mentioning "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present embodiment application. The appearance of this phrase in various positions in the specification does not necessarily mean that they are all the same embodiments, nor are they independent or alternative embodiments that are mutually exclusive with other embodiments. It can be understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0033] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

Claims

1. A method for preparing a metallized grid line of a heterojunction solar cell, characterized in that: The steps include: Step S1, texturing the front and back sides of the single crystal silicon wafer to form a pyramid texture structure; Step S2, cleaning the silicon wafer after texturing to remove metal impurities on the surface of the silicon wafer, and finally removing the surface oxide layer of the silicon wafer with hydrofluoric acid to form a clean surface state; Step S3, depositing silicon thin films on the front and back of the cleaned silicon wafer respectively: depositing a layer of intrinsic amorphous silicon layer and a doped amorphous silicon layer or a microcrystalline silicon thin film on the front of the silicon wafer in sequence; depositing a layer of intrinsic amorphous silicon layer and a doped amorphous silicon layer or a microcrystalline silicon thin film on the back of the silicon wafer in sequence; Step S4, depositing a transparent conductive oxide layer and a metal layer in sequence on the front side of the silicon wafer after the amorphous silicon layer is deposited by using a physical vapor deposition method; Step S5, depositing a transparent conductive oxide layer film and a metal layer film in sequence on the back side of the silicon wafer after the amorphous silicon layer is deposited by using a physical vapor deposition method; Step S6, laying a copper wire as a front fine gate electrode on the front side of the silicon wafer after the metal layer film is prepared, and then laying 5 to 20 identical copper wires as a front main gate electrode in a direction perpendicular to the fine gate electrode, and applying pressure and temperature to the copper wire on the surface of the silicon wafer by using a mold, so that the tin layer on the surface of the copper wire and the metal layer on the surface of the silicon wafer are melted and welded together under the dual effects of pressure and temperature to form an ohmic contact to reduce contact resistance; Step S7, laying copper wires as back fine gate electrodes on the back side of the silicon wafer after the metal layer is prepared, and then laying 5 to 20 identical copper wires as back main gate electrodes in a direction perpendicular to the fine gate electrodes, and applying pressure and temperature to the copper wires on the surface of the silicon wafer using a mold, so that the tin layer on the surface of the copper wire and the metal layer on the surface of the silicon wafer are melted and welded together to form ohmic contact to reduce contact resistance under the dual effects of pressure and temperature; Step S8, placing the silicon wafer with the prepared front and back gate line electrodes in an oxidizing acid solution, etching the metal layer outside the gate lines cleanly, forming a complete heterojunction solar cell with front and back gate line electrodes of different patterns, and completing the preparation process of the metallized gate lines of the heterojunction solar cell.

2. The method for preparing a metallized grid line of a heterojunction solar cell according to claim 1, characterized in that: The copper wires in step S6 and step S7 are composed of copper wires with a tin layer on the surface for protection, the diameter of the copper wires is 5um-40um, and the front fine gate electrode is paved with 50-200 copper wires.

3. The method for preparing a metallized grid line of a heterojunction solar cell according to claim 2, characterized in that: The copper wire is in any of a circular, square, and triangular shape.

4. The method for preparing a metallized grid line of a heterojunction solar cell according to claim 1, characterized in that: The copper wire diameter of the main gate electrode in step S6 and step S7 is 30-100 um.

5. The method for preparing a metallized grid line of a heterojunction solar cell according to claim 1, characterized in that: The pressure in step S6 and step S7 is 0.5N-10N, the temperature is 150°C-300°C, and the heating time is 10s-50s.

6. The method for preparing a metallized grid line of a heterojunction solar cell according to claim 1, characterized in that: The acid solution in step S8 includes hydrochloric acid and / or sulfuric acid aqueous solution, the concentration of the acid solution is 1%-10%, and the etching time is 10s-60s.

7. The method for preparing a metallized grid line of a heterojunction solar cell according to claim 1, characterized in that: The transparent conductive oxide layer film in step S4 and step S5 is any one of an indium tin oxide layer, an indium oxide composite layer doped with elements, and a zinc oxide material doped with aluminum or boron elements. The thickness of the transparent conductive oxide layer film is 50nm-200nm.

8. The method for preparing a metallized grid line of a heterojunction solar cell according to claim 1, characterized in that: The metal layer film in step S4 and step S5 is an alloy of one or more of copper, tin, nickel, and silver, and the thickness of the metal layer film is 50nm-300nm.

9. The method for preparing a metallized grid line of a heterojunction solar cell according to claim 1, characterized in that: In step S3, an intrinsic amorphous silicon layer and a doped amorphous silicon layer or a microcrystalline silicon film are deposited on the front and back sides of the silicon wafer by chemical vapor deposition.

10. A device for preparing metallized grid lines of heterojunction solar cells, characterized in that: The device performs the method for preparing metallized grid lines of heterojunction solar cells as described in any one of claims 1 to 9 to prepare metallized grid lines of heterojunction solar cells.

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