Silicon wafer, solar cell, photovoltaic module and processing method of silicon wafer

Abstract

The invention discloses a silicon wafer, a solar cell, a photovoltaic module and a processing method of the silicon wafer, which are used for ensuring the uniformity of the mechanical strength of the silicon wafer and reducing the fragment rate of the silicon wafer and the module end. At least one side of the silicon wafer is provided with a groove, the surface of the silicon wafer is provided with a plurality of cutting line marks, the cutting line marks extend along a group of opposite sides of the silicon wafer, and the groove is located on at least one side of the other group of opposite sides of the silicon wafer. According to the silicon wafer, stress superposition of the groove and the cutting line marks in the direction perpendicular to the edge where the groove is located is avoided, the pressure borne by the surface of the silicon wafer in the direction parallel to the edge where the groove is located is basically not affected by the groove, and therefore it is guaranteed that the overall mechanical strength uniformity of the silicon wafer is good; according to the invention, the fragmentation rate of the battery assembly end manufacturing process can be reduced, the stability and reliability of the assembly end are improved, the production cost is reduced, and the product quality and working safety are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon wafer manufacturing, and in particular to a silicon wafer, a solar cell wafer, a photovoltaic module and a silicon wafer processing method. Background Art

[0002] In order to improve the efficiency of photovoltaic modules, some photovoltaic modules currently cancel / reduce the inter-cell spacing of solar cells in photovoltaic modules, specifically, by slotting the edge of silicon wafers. The existing slotted silicon wafers, due to the slots on the silicon wafers, have reduced uniformity in mechanical strength of the silicon wafers, a high rate of fragmentation during silicon wafer end processing, and high silicon wafer processing costs. Therefore, how to provide slotted silicon wafers that meet the needs of the back end without affecting the processing cost of the silicon wafers has become a problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0003] The purpose of the present invention is to provide a silicon wafer, a solar cell, a photovoltaic module and a processing method for a silicon wafer to ensure the uniformity of the mechanical strength of the silicon wafer, reduce the fragmentation rate of the battery module end process, improve the stability and reliability of the battery module end, reduce production costs, and improve product quality and work safety requirements.

[0004] In a first aspect, the present invention provides a silicon wafer having a groove on at least one side of the silicon wafer and a plurality of cutting line marks on the surface of the silicon wafer, wherein the cutting line marks extend along a set of opposite sides of the silicon wafer and the groove is located on at least one side of another set of opposite sides of the silicon wafer.

[0005] When the above technical solution is adopted, since there is a groove on at least one side of the silicon wafer, and the groove will affect the mechanical strength of the side where the groove is located, when the bending pressure test is performed on the surface of the silicon wafer in a direction perpendicular to the side where the groove is located, the pressure that the silicon wafer can withstand will be reduced, resulting in an increase in the fragmentation rate of the silicon wafer. If the cutting line mark is also perpendicular to the side where the groove is located, since the groove will form stress on the silicon wafer along the depth direction of the groove, the cutting line mark will further reduce the mechanical strength of the silicon wafer along the stress direction, resulting in poor uniformity of the mechanical strength of the entire silicon wafer, and cannot reduce the fragmentation rate of the battery component end process and improve the stability and reliability of the battery component end. After further research, the inventor of the present application proposed a silicon wafer such that the cutting line mark extends along a set of opposite sides of the silicon wafer, and the groove is located on at least one side of another set of opposite sides of the silicon wafer. This avoids the superposition of stress between the grooves and the cutting marks in the direction perpendicular to the sides where the grooves are located. The pressure that the silicon wafer can withstand is basically not affected by the stress of the cutting marks in this direction, thereby ensuring good uniformity of the overall mechanical strength of the silicon wafer and reducing the fragmentation rate. Without affecting the processing cost of the silicon wafer, it can reduce the fragmentation rate of the battery component process, improve the stability and reliability of the battery component, reduce production costs, and improve product quality and work safety.

[0006] In some possible implementations, grooves are provided on two opposite sides of the silicon wafer, so that the conductive interconnects between adjacent silicon wafers can pass through the grooves, further reducing the distance between adjacent silicon wafers and reducing the damage of the conductive interconnects to the silicon wafers during lamination.

[0007] In some possible implementations, the distance between two adjacent cutting line marks on the surface of the silicon wafer is 1 mm to 4 mm.

[0008] In the present application, the spacing between adjacent cutting marks refers to the distance between any point on one of the two adjacent cutting marks on the surface of the silicon wafer and the point at the corresponding position on the other adjacent cutting mark along the direction perpendicular to the tangent line where the point is located; a line mark spacing greater than 4mm will cause uneven stress distribution on the surface of the silicon wafer, increase the stress inside the silicon wafer, cause cracks and fractures inside the silicon wafer, and affect the appearance of the silicon wafer; a line mark spacing less than 1mm will affect the cutting efficiency.

[0009] In some possible implementations, the cutting marks of the silicon wafer are arc-shaped, and the distance from the arc bottom to the arc top of the cutting marks is less than 17 mm and greater than 1 mm.

[0010] The distance from the arc bottom to the arc top of the cutting line mark of the present application is less than 17mm. Since there is stress formed by the groove on at least one side of the other set of opposite sides of the silicon wafer, the stress generated by the cutting line mark can be improved to a certain extent, so that the strength uniformity of the entire surface of the silicon wafer is good and the silicon wafer fragmentation rate is low. The curvature of the cutting line mark is too small, the cutting force is insufficient, and the cutting accuracy and the flatness of the edge of the silicon wafer are poor. Without affecting the stress generated by the groove on the silicon wafer on the cutting line mark, the distance from the arc bottom to the arc top of the cutting line mark of the present application is greater than 1mm.

[0011] In some possible implementations, the strength uniformity of the silicon wafer is greater than or equal to 90%.

[0012] The strength uniformity of silicon wafers refers to the average strength between different silicon wafers under the same manufacturing process. The strength uniformity of silicon wafers has an important impact on the quality and stability of silicon wafers. Smaller strength uniformity may lead to unstable product quality. The strength uniformity of silicon wafers can be evaluated by statistical distribution. The strength of a group of silicon wafer samples is tested, and a strength distribution curve is drawn based on the test results. The uniformity is analyzed by statistical methods. Statistical indicators such as standard deviation, variance, and range can usually be used to describe the uniformity of silicon wafer strength. In this application, variance is used to calculate the strength uniformity of silicon wafers.

[0013] When conducting strength tests, a horizontal test bench is set up, and two support beams are installed on the horizontal test bench. The silicon wafer is placed on the two support beams. The span between the two support beams is 90mm, and the thickness of the silicon wafer is 40um to 170um. Then, a thrust is applied to the silicon wafer from top to bottom, and the specific data of the applied pressure and the distance of advancement are recorded by the sensor to measure the strength of the silicon wafer. The strength at different positions is recorded, and the strength uniformity of the silicon wafer can be obtained by calculating its variance. In some possible implementations, the groove depth of the groove is 0.3mm to 1mm. This groove depth range can provide sufficient accommodation depth for the conductive interconnect, minimize the spacing between adjacent battery cells, and will not significantly affect the mechanical strength of the silicon wafer.

[0014] In some possible implementations, the groove width is 5% to 15% of the length of the side where the groove is located. If the groove width is too small, it is not conducive to the passage of the conductive interconnection component. If the groove width is too large, it affects the overall mechanical strength of the silicon wafer and is inconvenient to process.

[0015] In some possible implementations, the groove width is 0.5 mm to 2 mm, and the length of the side where the groove is located is 180 mm to 230 mm.

[0016] In some possible implementations, the spacing between two adjacent grooves is 4% to 6% of the length of the side where the grooves are located. That is, the groove spacing is determined according to the position of the conductive interconnection member, and if the groove spacing is too small, the number of grooves is too large, which affects the mechanical strength of the silicon wafer; if the groove spacing is too large, the number of grooves is too small, so that some conductive interconnection members have no corresponding grooves to pass through, which is not conducive to reducing the spacing between the battery cells.

[0017] In some possible implementations, the distance between two adjacent grooves is 8 mm to 13 mm.

[0018] In a second aspect, the present invention further provides a method for processing a silicon wafer, comprising:

[0019] Providing a silicon rod, wherein the silicon rod has two opposite surfaces, and at least one surface is provided with a groove;

[0020] Bonding the silicon rod to the carrier plate so that the surface of the silicon rod having the groove or the surface opposite to the groove is close to the carrier plate;

[0021] The silicon rod is cut along the direction from the surface of the silicon rod opposite to the carrier plate to the surface bonded to the carrier plate to obtain a plurality of silicon wafers, wherein at least one side of the silicon wafer has a groove, and the cutting line marks obtained by cutting extend along a group of opposite sides of the silicon wafer, and the groove is located on at least one side of the other group of opposite sides of the silicon wafer.

[0022] In the case of adopting the above technical solution, the processing method cuts the silicon rod from the surface of the silicon rod opposite to the carrier plate to the surface bonded to the carrier plate, the cutting direction is parallel to the opening direction of the groove, and the side surface with the groove or the other side surface opposite to the groove is used as the cutting entry side, and a groove is formed on at least one side of the silicon wafer obtained by cutting corresponding to the position of the groove on the original silicon rod, and the cutting line marks obtained by cutting extend along a group of opposite sides of the silicon wafer, and the groove is located on at least one side of the other group of opposite sides of the silicon wafer. For the silicon wafer obtained by the slicing method, since the side where the extension direction of the cutting line marks on the silicon wafer is located is different from the side where the silicon wafer groove is located, the stress formed on the side where the groove is located will not be superimposed on the side where the cutting line marks are located, and the two are distributed in different directions of the silicon wafer, thereby alleviating the adverse effect of excessive stress formed in a single direction of the silicon wafer, so that the strength uniformity of the entire surface of the silicon wafer is relatively consistent, meeting the processing requirements of the back end, and will not cause the problem of high fragmentation rate of the silicon wafer end and the back end when in use.

[0023] In some possible implementations, the step of cutting the silicon rod to obtain a plurality of silicon wafers further includes adjusting the tension of the cutting wire mesh and the supply of the cutting fluid to ensure that the distance from the arc bottom to the arc top of the cutting line mark is greater than 1 mm and less than 17 mm.

[0024] In the case of adopting the above technical solution, by controlling the tension of the cutting wire net at 2N to 5N during the cutting process, the distance between the arc bottom and the arc top of the cutting line mark, that is, the curvature of the cutting line mark, is improved. If the curvature of the cutting line mark is too large, it will cause uneven stress in all directions on the surface of the silicon wafer. The distance from the arc bottom to the arc top of the cutting line mark of the present application is less than 17mm. Since there is a stress formed by the groove on at least one side of the other set of opposite sides of the silicon wafer, the stress generated by the cutting line mark can be improved to a certain extent, so that the strength uniformity of the entire surface of the silicon wafer is good and the silicon wafer fragmentation rate is low. The curvature of the cutting line mark is too small, the cutting force is insufficient, and the cutting accuracy and the flatness of the edge of the silicon wafer are poor. Without affecting the stress generated by the groove on the silicon wafer on the cutting line mark, the distance from the arc bottom to the arc top of the cutting line mark of the present application is greater than 1mm.

[0025] In some possible implementations, a plurality of grooves parallel to each other and arranged at intervals are opened through a grinding wheel assembly. A plurality of grinding wheels are arranged on the grinding wheel assembly, which can act on the surface of the silicon rod at the same time. The overall offset of the grooves on the processed silicon wafer is small, thereby improving the processing accuracy.

[0026] When the above technical solution is adopted, multiple grooves are opened on one surface of the silicon rod through a grinding wheel assembly that is rotatably supported at both ends. Since both ends of the grinding wheel assembly are rotatably supported, the rigidity of the grinding wheel assembly during operation is improved, and the grinding wheel thereon is not prone to shaking, thereby improving the quality of silicon rod grooving. Multiple grinding wheels are arranged on the grinding wheel assembly, which can simultaneously open multiple grooves on the surface of the silicon rod at one time, thereby improving the efficiency of silicon rod grooving.

[0027] In some possible implementations, a plurality of grooves parallel to each other and arranged at intervals are formed by a grinding wheel assembly, including:

[0028] A plurality of coarse grinding grooves which are parallel to each other and arranged at intervals are formed by a coarse grinding wheel assembly;

[0029] And / or, a plurality of parallel and spaced fine grinding grooves are formed by the fine grinding wheel assembly.

[0030] When the above technical solution is adopted, the rough grinding wheel assembly is used to groove the silicon rod to obtain the rough grinding groove, and the fine grinding wheel assembly is used to groove the silicon rod to obtain the fine grinding groove, thereby improving the processing quality of the groove.

[0031] In some possible implementations, before or after the grinding wheel assembly is used to open a plurality of grooves that are parallel to each other and spaced apart, the processing method further includes: grinding the surface. This arrangement can improve the flatness of the edge of the silicon wafer and improve the processing quality of the silicon wafer.

[0032] In a third aspect, the present invention further provides a solar cell comprising a silicon wafer, wherein the silicon wafer is a silicon wafer as described in any one of the above items. Since the solar cell adopts the silicon wafer described in any one of the above items, it has the same beneficial effects as the silicon wafer, which will not be described in detail.

[0033] In a fourth aspect, the present invention further provides a photovoltaic module, comprising at least two cells and a conductive interconnection member connecting adjacent cells, wherein the cell is a solar cell as described above, the conductive interconnection member passes through a groove of the solar cell, and the two ends of the conductive interconnection member are respectively connected to a front member and a back member of an adjacent solar cell. Since the photovoltaic module adopts the solar cell described above, it has the same beneficial effects as the solar cell, which will not be described in detail. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0035] Figure 1 A schematic diagram of the structure of a silicon wafer provided by an embodiment of the present invention;

[0036] Figure 2 for Figure 1 Schematic diagram of the three-point bending and pressing of the silicon wafer in the direction perpendicular to the cutting line marks;

[0037] Figure 3 for Figure 1Schematic diagram of the three-point bending and pressing of the silicon wafer in the direction parallel to the cutting line marks;

[0038] Figure 4 A schematic diagram of the structure of another silicon wafer provided for Comparative Example 1;

[0039] Figure 5 A schematic diagram of the operation of bending and pressing the silicon wafer at three points in a direction perpendicular to the cutting line marks in Comparative Example 1;

[0040] Figure 6 A schematic diagram of the operation of bending and pressing the silicon wafer at three points in a direction parallel to the cutting line marks in Comparative Example 1;

[0041] Figure 7 This is a graph showing the strength data of silicon wafers of the present application examples and comparative examples;

[0042] Figure 8 A schematic diagram of a silicon wafer structure provided for another embodiment of the present application.

[0043] Figure numerals: 1 is the first side, 2 is the second side, 3 is the groove, 4 is the cutting line mark, and 5 is the pressure rod. DETAILED DESCRIPTION

[0044] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0045] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0046] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0047] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by the terms "up", "down", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0048] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0049] like Figure 1 As shown, an embodiment of the present invention provides a silicon wafer, the silicon wafer having two opposite first sides 1 and two opposite second sides 2, the first sides 1 and the second sides 2 being perpendicular, at least one side of the silicon wafer having a groove 3, the groove 3 being used for subsequent conductive interconnection members to pass through. For example, the groove 3 may be provided on one first side 1, or may be provided on both of the two opposite first sides 1. There are a plurality of cutting line marks 4 on the surface of the silicon wafer, the cutting line marks 4 extending along a set of opposite sides of the silicon wafer, the groove 3 being located on at least one side of the other set of opposite sides of the silicon wafer, for example, the first side 1 having the groove 3 is provided, and the following description is made by taking the first side 1 having the groove 3 as an example. The cutting line marks 4 are grinding textures formed on the surface of the silicon wafer due to grinding between the cutting line and the surface of the silicon wafer during the reciprocating routing process. Since the silicon rod is fed relative to the cutting wire net, the cutting line is subjected to pressure from the silicon rod, and the cutting line forms a certain degree of bending in the feeding direction while reciprocating the cutting line, and each corresponding cutting line mark 4 is presented as an arc visible to the naked eye on the surface of the silicon wafer. Figure 1 In order to show the state of the cutting line marks 4 on the silicon wafer, some cutting line marks 4 are schematically drawn to show their contours and curvatures, etc., which do not represent the structure of the actual cutting line marks 4. It can be seen in the figure that multiple cutting line marks 4 are densely arranged along the cutting direction.

[0050] Since there is a groove 3 on the first side 1 of the silicon wafer, and the groove 3 will affect the uniformity of the mechanical strength of the first side 1 of the silicon wafer, the inventor of the present application, after further research, proposes a silicon wafer, which has a groove 3 on at least one side of the silicon wafer, and has a plurality of cutting lines 4 on the surface of the silicon wafer, the cutting lines 4 extending along a group of opposite sides of the silicon wafer, and the groove 3 is located on at least one side of the other group of opposite sides of the silicon wafer. Thus, the superposition of stresses of the groove 3 and the cutting lines 4 in the direction of the first side 1 is avoided, and the pressure that the surface of such a silicon wafer can withstand in the direction parallel to the first side 1 is basically not affected by the cutting lines in this direction, thereby ensuring good uniformity of the mechanical strength of the silicon wafer as a whole, reducing the fragmentation rate, and reducing the fragmentation rate of the battery assembly end process without affecting the processing cost of the silicon wafer, improving the stability and reliability of the assembly end, reducing production costs, and improving product quality and work safety.

[0051] Furthermore, if Figure 1 As shown, grooves 3 are provided on two opposite sides of the silicon wafer. That is, grooves 3 are provided on two opposite first sides 1. It is convenient for the conductive interconnection parts between adjacent silicon wafers to pass through the grooves 3, further reducing the distance between adjacent silicon wafers and reducing the damage of the conductive interconnection parts to the silicon wafers during lamination.

[0052] In some embodiments, the cutting line mark 4 of the silicon wafer is arc-shaped, wherein the distance from the arc bottom to the arc top of the cutting line mark 4 is greater than 1 mm and less than 17 mm.

[0053] It should be noted that the arc top here is the point in the cutting line mark 4 that is farthest from the arc bottom near the arc opening position, that is, it can be understood by those skilled in the art that the distance between the arc top and the arc bottom mentioned in this application refers to the distance between a point on the horizontal line at the bottom position of the arc and the farthest point near the arc opening position along the arc opening direction.

[0054] The distance from the arc bottom to the arc top of the cutting line mark 4 of the present application is less than 17mm. Since there is a stress formed by the groove 3 on at least one side of the other set of opposite sides of the silicon wafer, the stress generated by the cutting line mark 4 can be improved to a certain extent, so that the strength uniformity of the entire surface of the silicon wafer is good and the silicon wafer fragmentation rate is low. The curvature of the cutting line mark 4 is too small, the cutting force is insufficient, and the cutting accuracy and the flatness of the edge of the silicon wafer are poor. Without affecting the stress generated by the groove 3 on the silicon wafer on the cutting line mark 4, the distance from the arc bottom to the arc top of the cutting line mark 4 of the present application is greater than 1mm.

[0055] In some embodiments, the present application also proposes another silicon chip, such as Figure 8 As shown, a groove 3 is provided on one side of the silicon wafer. When the solar cells prepared by the silicon wafer are connected through the conductive interconnection member, the conductive interconnection member connects the front components and the back components of the adjacent solar cells through the groove 3 .

[0056] It is understandable that the silicon wafer with the groove 3 on one side of the silicon wafer can be obtained by slicing the silicon wafer with the grooves 3 on both sides of the silicon wafer, or the groove is directly formed on the half wafer when processing half of the silicon wafer. This application does not limit this.

[0057] In some embodiments, the mechanical strength of the silicon wafer is greater than 2N. The mechanical strength of the silicon wafer is described as follows: Figure 2 As shown, when bending pressure is applied to the silicon wafer in a direction perpendicular to the first side 1, it can be three-point bending pressure, four-point bending pressure, etc. Taking three-point bending pressure as an example, that is, the length direction of the pressure rod 5 is perpendicular to the first side 1, the maximum pressure on the silicon wafer is P1, and this maximum pressure P1 can be used as the mechanical strength of the silicon wafer in the direction perpendicular to the first side 1. Figure 3 As shown, when three-point bending pressure is applied to the silicon wafer in a direction parallel to the first side 1, that is, the length direction of the pressure rod 5 is parallel to the first side 1, the maximum pressure on the silicon wafer is P2, and this maximum pressure P2 can be used as the mechanical strength of the silicon wafer in the direction parallel to the first side 1. P1 and P2 represent the pressure when cracks or hidden cracks appear in the silicon wafer due to bending pressure, and P1 is less than P2.

[0058] Since the first side 1 has a groove 3, the setting of the groove 3 will affect the mechanical strength of the first side 1, and the second side 2 has no groove. In the case that the cutting line 4 extends along the second side 2, when three-point bending pressure is applied to the silicon wafer in a direction perpendicular to the first side 1, the maximum pressure P1 that the silicon wafer withstands is slightly smaller than the maximum pressure P2 that the silicon wafer withstands when three-point bending pressure is applied to the silicon wafer in a direction parallel to the first side 1.

[0059] Specifically, the range of P1 is 2N to 2.28N, and the range of P2 is 2.18N to 2.45N. It can be seen that the deviation of P1 and P2 is within 10%, indicating that the mechanical strength uniformity of the entire silicon wafer in two directions parallel to the first side 1 and perpendicular to the first side 2 is good, which can reduce the fragmentation rate of the battery component end process, improve the stability and reliability of the component end, reduce production costs, and improve product quality and work safety.

[0060] In order to more clearly reflect the uniformity of the mechanical strength of the silicon wafer in the present application, the mechanical strength of the silicon wafer in the present application is compared with that of another silicon wafer in Comparative Example 1 and the silicon wafer in Comparative Example 2, and the fragmentation rate is recorded. It should be noted that the silicon wafer in the present application is obtained by squaring and slicing the silicon rods prepared by the same crystal pulling process, and the selected silicon wafers have a thickness of 140um and a side length of 182.2*191.6.

[0061] Embodiment 1, as Figure 1 The silicon wafer in the present application is shown. The two opposite first sides 1 of the silicon wafer are provided with grooves 3. The surface of the silicon wafer has a plurality of cutting marks 4. The cutting marks 4 extend along the second side 2. 10 pieces of silicon wafers are selected for strength testing. Figure 2 As shown, a three-point bending test is performed on the silicon wafer parallel to the second side direction, and at this time, the pressure rod 5 is parallel to the second side 2. Figure 3 As shown, a three-point bending test is performed on the silicon wafer in a direction parallel to the first side. At this time, the pressure rod 5 is parallel to the first side 1 and perpendicular to the opening direction of the groove 3.

[0062] Comparative Example 1, such as Figure 4 As shown, the silicon wafer in comparative example 1 also has two opposite first sides 1 and two opposite second sides 2, the first sides 1 and the second sides 2 are perpendicular, and the two opposite first sides 1 have grooves 3, and the surface of the silicon wafer has multiple cutting marks 4. The only difference between the silicon wafer in comparative example 1 and the silicon wafer in the present application is that the cutting marks 4 extend along the first sides 1. Ten pieces of silicon wafers are also used for strength testing, as shown in FIG. Figure 5 As shown, the silicon wafer in comparative example 1 is subjected to a three-point bending test parallel to the first side 1. At this time, the pressure rod 5 is parallel to the first side 1 and perpendicular to the opening direction of the groove 3. Figure 6 As shown, the silicon wafer in comparative example 1 is subjected to a three-point bending test parallel to the second side 2 , and at this time, the pressure rod 5 is perpendicular to the first side 1 and parallel to the opening direction of the groove 3 .

[0063] The first side and the second side of the silicon wafer in comparative example 2 do not have grooves, and there are multiple cutting lines on the surface of the silicon wafer, and the cutting lines extend along the second side. The only difference from the silicon wafer in the present application is that there is no groove on the first side. Similarly, 10 pieces of silicon wafers are removed from the head and tail parts of the silicon rod for strength testing. The silicon wafers are subjected to a three-point bending test along the second direction. At this time, the pressure rod 5 is parallel to the second side 2. The silicon wafer is subjected to a three-point bending test along the first direction 1. At this time, it is parallel to the first side 1.

[0064] The silicon wafers in Example 1, Comparative Example 1 and Comparative Example 2 were subjected to three-point bending tests perpendicular to the second side and parallel to the second side.

[0065] The silicon wafers in the present application, the silicon wafers in comparative example 1 and the silicon wafers in comparative example 2 were subjected to three-point bending and compression tests in two directions to perform strength tests, and their averages were calculated and statistically analyzed to obtain the following results: Figure 7As shown, when the mechanical strength of the silicon wafer is tested, the silicon wafer in Example 1 of the present application is tested in a direction perpendicular to the first edge or in a direction parallel to the first edge, and the uniformity of the mechanical strength is high, which is calculated to be greater than 90%. In Comparative Example 1, since the cutting line marks extend along the edge where the groove is located on the silicon wafer, the mechanical strength of the silicon wafer obtained by testing along the edge perpendicular to the groove is significantly reduced, and along the direction parallel to the first edge, the difference is close to that of the silicon wafer without a groove in Comparative Example 2, resulting in low overall strength uniformity of the silicon wafer. According to statistics, when preparing this type of silicon wafer, the fragmentation rate is about 10%; the edge of the silicon wafer in Comparative Example 2 has no groove, and the overall strength of the silicon wafer is relatively high, but the strength uniformity is lower than that of Example 1 of the present application. When preparing the silicon wafer in this way, its fragmentation rate is about 0.8%; due to the influence of the groove, the strength of the silicon wafer in Example 1 of the present application is slightly reduced when the mechanical strength is tested in a direction parallel to the first edge, but it will not cause too much impact on subsequent manufacturing, and its fragmentation rate is generally less than 1%.

[0066] From the above comparison, it can be seen that the difference between P1 and P2 of the silicon wafer in this application is not much, and the mechanical strength of the entire silicon wafer in the two directions parallel to the first edge and perpendicular to the first edge is relatively uniform, ensuring the mechanical strength requirements of the silicon wafer in subsequent processes.

[0067] In some embodiments, the shape of the groove 3 can be semicircular, rectangular, V-shaped or U-shaped. These forms of grooves 3 can all allow the conductive interconnect to pass through, so as to reduce the spacing between adjacent battery cells. The bottom transition of the semicircular groove 3 is smoother and has higher mechanical strength.

[0068] In some embodiments, the groove depth H of the groove 3 is 0.3 mm to 1 mm, specifically 0.3 mm, 0.4 mm, 0.45 mm, 0.5 mm, 0.55 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm, etc. The groove depth H of the groove 3 refers to the distance between the position of the groove 3 farthest from the first side 1 and the first side 1. When the shape of the groove 3 is semicircular, the groove depth H is the radius of the semicircle. This groove depth range can provide sufficient accommodation depth for the conductive interconnection, minimize the spacing between adjacent battery cells, and will not significantly affect the mechanical strength of the silicon wafer.

[0069] In some embodiments, the groove width L of the groove 3 is 5% to 15% of the length of the first side 1, and can be specifically 0.5%, 7.7%, 8%, 8.2%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, etc. The groove width L of the groove 3 refers to the total span of the port of the groove 3 and the circular arc chamfers on both sides. If the groove width of the groove 3 is too small, it is not conducive to the passage of the conductive interconnection, and the conductive interconnection is easily damaged by contact with the groove wall of the groove 3. If the groove width of the groove 3 is too large, it affects the overall mechanical strength of the silicon wafer and is inconvenient to process. Considering the convenience of the passage of the conductive interconnection and the overall mechanical strength of the silicon wafer, the proportion of the groove width L of the groove 3 in this embodiment is selected to be 7% to 9%.

[0070] Exemplarily, the side length of the silicon wafer is 180 mm to 230 mm, for example, the side length of the silicon wafer is 180 ± 2 mm, 185 ± 2 mm, 190 ± 2 mm, 194 ± 2 mm, 198 ± 2 mm, 202 ± 2 mm, 210 ± 2 mm, 215 ± 2 mm, 218 ± 2 mm, 222 ± 2 mm, 226 ± 2 mm, 229 mm, 230 mm, etc. When the side length of the silicon wafer is about 182 mm, the lengths of the first side 1 and the second side 2 may be equal or unequal. Taking the side length of the first side 1 as 182 mm as an example, the groove width L of the groove 3 is 1 mm to 2 mm, and specifically may be 1 mm, 1.2 mm, 1.4 mm, 1.45 mm, 1.5 mm, 1.6 mm, 1.7 mm, 1.8 mm, 1.9 mm, 2 mm, etc.

[0071] In some embodiments, the spacing between two adjacent grooves 3 on the first side 1 is 4% to 6% of the side length of the first side 1, specifically 4%, 4.3%, 5.3%, etc., that is, the groove spacing between adjacent grooves 3 is determined according to the position of the conductive interconnection component, and the groove spacing is too small and the number of grooves 3 is too large, which affects the mechanical strength of the silicon wafer. If the groove spacing is too large and the number of grooves 3 is too small, some conductive interconnections will have no corresponding grooves to pass through, which is not conducive to reducing the spacing between battery cells. Considering the mechanical strength of the silicon wafer and facilitating the passage of the conductive interconnection component, the groove spacing in this embodiment is selected to be 4% to 6% on the first side 1.

[0072] For example, when the side length of the silicon wafer is about 182 mm, the lengths of the first side 1 and the second side 2 may be equal or unequal. Taking the side length of the first side 1 as 182 mm as an example, the spacing between two adjacent grooves 3 on the first side 1 is 9.45 mm to 9.55 mm, and specifically may be 9.45 mm, 9.47 mm, 9.50 mm, 9.52 mm, 9.55 mm, etc.

[0073] For the preparation of Figure 1The silicon wafer shown in the embodiment of the present invention also provides a method for processing a silicon wafer. The silicon wafer described in any of the above embodiments can be prepared by the method in this embodiment. The specific preparation method of the present application includes the following steps:

[0074] In step S100, a silicon rod is provided. The silicon rod has two opposite surfaces, and at least one surface is provided with a groove.

[0075] For example, the silicon rod may be a square silicon rod having four rectangular side faces and two square end faces, wherein the four rectangular side faces are arranged opposite to each other in pairs, wherein the two opposite rectangular side faces are the first surface and the second surface of the silicon rod, and at least one of the first surface and the second surface is provided with a plurality of grooves parallel to each other, wherein the grooves are strip grooves, and the other two opposite rectangular side faces do not have strip grooves. The length direction of the strip grooves is perpendicular to the two square end faces of the square silicon rod, that is, perpendicular to the surface formed after the silicon rod is sliced.

[0076] Step S200, bonding the silicon rod to the carrier plate, so that the surface of the silicon rod with the groove or the surface opposite to the groove is close to the carrier plate, and the surface can be the first surface or the second surface. That is, bonding one side surface of the silicon rod with the groove or the other side surface opposite to the groove to the carrier plate, wherein the carrier plate can be a resin plate or a plastic plate, and the carrier plate is bonded to the lower surface of the wafer tray.

[0077] Step S300, cutting along the direction from the surface of the silicon rod opposite to the carrier plate to the surface bonded to the carrier plate, for example, the cutting direction from the second surface to the first surface can be cut from the second surface until it is cut into the carrier plate, to obtain multiple silicon wafers, wherein a groove 3 is formed at the position corresponding to the strip groove on the first side 1 of the silicon wafer, and multiple cutting line marks 4 are formed on the surface of the silicon wafer, and the cutting line marks 4 extend along a group of opposite sides of the silicon wafer, and the groove 3 is located on at least one side of the other group of opposite sides of the silicon wafer. After the silicon rod is sliced, the first surface and the second surface form the opposite first side 1, and the strip groove is sliced ​​and divided to form the groove 3 on the first side 1, and the other two opposite rectangular sides form the opposite second side 2, which does not have a groove, and the groove 3 is used for the subsequent conductive interconnection to pass through.

[0078] In specific operation, the crystal support is driven to drive the carrier plate and the silicon rod to move relative to the cutting line along the direction from the second surface to the first surface. The silicon rod can be moved downward for cutting. During this process, the cutting line reciprocates along the direction parallel to the second surface to provide a cutting line speed. The cutting line starts from the second surface and cuts into the carrier plate. The entire silicon rod is cut to obtain a silicon wafer. The cutting line mark 4 appears as an arc visible to the naked eye on the surface of the silicon wafer. Figure 1In order to show the state of the cutting marks 4 on the silicon wafer, some cutting marks 4 are schematically drawn to show their contours and curvatures, which do not represent the actual structure of the cutting marks 4. Multiple cutting marks 4 are densely arranged along the cutting direction at a microscopic level. There are also cutting marks 4 on both sides of the groove 3. Figure 1 Only part of the cutting line 4 is shown.

[0079] When the above technical solution is adopted, the slicing method starts cutting from one side surface of the silicon rod along the direction close to the carrier plate, and the cutting direction is parallel to the opening direction of the groove 3. The side surface with the groove 3 or the other side surface opposite to the surface where the groove 3 is located is used as the cutting entry side. A groove 3 is formed on at least one first side 1 of the cut silicon wafer corresponding to the position of the original groove on the silicon rod, and multiple cutting lines 4 are formed on the two side surfaces of the silicon wafer, and the cutting lines 4 extend along the second side 2. The silicon wafer obtained by the slicing method has the cutting lines 4 on the silicon wafer perpendicular to the opening direction of the groove and parallel to the first side 1. The groove 3 will affect the mechanical strength of the first side 1 of the silicon wafer. Figure 2 As shown, when the three-point bending and pressing test is performed on the surface of the silicon wafer in a direction perpendicular to the first side 1, the maximum pressure that the silicon wafer can withstand will be reduced, resulting in an increase in the fragmentation rate of the silicon wafer. If the cutting line mark is also along the second side 2, since the groove 3 will form stress along the depth direction of the groove 3 on the silicon wafer, the cutting line mark 4 will further reduce the mechanical strength of the silicon wafer along the stress direction, resulting in poor mechanical strength of the entire silicon wafer, which cannot meet the requirements of reducing the fragmentation rate of the battery component end process, improving the stability and reliability of the component end, reducing production costs, and improving product quality and work safety. Therefore, the slicing method of the present application makes the cutting line mark 4 parallel to the first side 1 with the groove 3, thereby avoiding the superposition of stresses of the groove 3 and the cutting line mark 4 in the direction perpendicular to the first side 1. The pressure that the silicon wafer surface can withstand in the direction parallel to the first side 1 is basically not affected by the cutting line mark 4, thereby ensuring that the overall mechanical strength of the silicon wafer is relatively balanced, which can reduce the fragmentation rate of the battery component end process, improve the stability and reliability of the component end, reduce production costs, and improve product quality and work safety.

[0080] It should be noted that during the processing of the silicon wafers of the present application, the process of cutting the silicon rods into silicon wafers also includes adjusting the tension of the cutting wire mesh, the supply of cutting fluid, the line speed, etc., and reasonably adjusting the parameters given in the above cutting process in combination with the cutting force to ensure that the distance from the bottom to the top of the arc of the cutting line mark is between 1mm and 17mm.

[0081] The distance from the arc bottom to the arc top of the cutting line mark is less than 17mm. Since there is a stress formed by the groove on at least one side of the other set of opposite sides of the silicon wafer, the stress generated by the cutting line mark can be improved to a certain extent, so that the strength uniformity of the entire surface of the silicon wafer is good and the silicon wafer fragmentation rate is low. The curvature of the cutting line mark is too small, the cutting force is insufficient, and the cutting accuracy and the flatness of the edge of the silicon wafer are poor. Without affecting the stress generated by the groove on the silicon wafer on the cutting line mark, the distance from the arc bottom to the arc top of the cutting line mark of the present application is greater than 1mm.

[0082] In addition, in the process of bonding the grooved surface of the silicon rod to the carrier plate, the grooves on the silicon rod can be accurately aligned during gluing, thereby improving the alignment accuracy between the silicon rod and the carrier plate. For silicon rods with only one surface having a groove, after bonding one side of the groove to the carrier plate, the cutting line is not easy to contact the groove and cause fragmentation during slicing. In addition, there are grooves on the silicon wafer, and the silicon wafer needs to be diced into half slices at the battery end. The grooves on the silicon wafer have a certain marking effect on locating the dicing position, which improves the dicing accuracy and makes it easier for the battery cells prepared from the silicon wafer to be interconnected at the component end.

[0083] It should be noted that the three-point bending test refers to, for example Figure 2 and Figure 3 As shown, the obtained silicon wafer is subjected to three-point bending and pressing by three pressure rods 5. Specifically, two pressure rods 5 act on the same surface of the silicon wafer, and the third pressure rod 5 acts on the other surface of the silicon wafer, and the third pressure rod 5 is located between the two pressure rods 5. The three pressure rods 5 can be arranged parallel to each other at equal intervals. The three pressure rods 5 apply pressure perpendicular to the silicon wafer to make the silicon wafer bend and deform, and the maximum pressure that the silicon wafer can withstand before it breaks is obtained by testing. The arrangement directions of the pressure rods 5 relative to the silicon wafer are different, and the maximum pressure that the silicon wafer can withstand in the length direction of the first side 1 and the length direction of the second side 2 can be measured, that is, the mechanical strength of the silicon wafer in the length direction of the first side 1 and the length direction of the second side 2.

[0084] In some possible implementations, providing a silicon rod in step S100, wherein the silicon rod has two opposite surfaces and at least one surface has a groove, may specifically include the following steps:

[0085] Step S101, providing a silicon rod having two opposite surfaces.

[0086] Step S102, a plurality of grooves which are parallel to each other and arranged at intervals are opened at one time by a grinding wheel assembly, wherein the grinding wheel assembly has a plurality of grinding wheels arranged along its axial direction, each grinding wheel is used to open a corresponding groove, and both ends of the grinding wheel assembly are rotatably supported.

[0087] It can be seen that multiple grooves are opened on one surface of the silicon rod at one time through the grinding wheel assembly with rotation support at both ends. Since the grinding wheel assembly is rotation supported at both ends, the rigidity of the grinding wheel assembly during operation is improved, and the grinding wheel thereon is not prone to shaking, thereby improving the quality of silicon rod grooving. Multiple grinding wheels are arranged on the grinding wheel assembly, which can simultaneously open multiple grooves on the surface of the silicon rod at one time, thereby improving the efficiency of silicon rod grooving.

[0088] Further, in this embodiment, the step S102 of opening a plurality of grooves that are parallel to each other and spaced apart at one time by the grinding wheel assembly includes the following steps:

[0089] Step S1021, using a rough grinding wheel assembly to open a plurality of parallel and spaced rough grinding grooves at one time;

[0090] And / or, step S1022, a plurality of parallel and spaced fine grinding grooves are formed at one time by a fine grinding wheel assembly.

[0091] When the above technical solution is adopted, the rough grinding wheel assembly is used to groove the silicon rod to obtain the rough grinding groove, and the fine grinding wheel assembly is used to groove the silicon rod to obtain the fine grinding groove, thereby improving the processing quality of the groove.

[0092] In some embodiments, before or after the grinding wheel assembly is used to open a plurality of grooves that are parallel to each other and arranged at intervals at one time in step S102, the slicing method further includes the step of grinding the surface. That is, the surface of the silicon rod can be ground first and then grooved, or the surface of the silicon rod can be grooved first and then ground. In this way, the flatness of the edge of the silicon wafer can be improved by grinding, thereby improving the processing quality of the silicon wafer.

[0093] Furthermore, the grinding process may include rough grinding and fine grinding, where rough grinding is performed first and fine grinding is performed next to improve the grinding quality.

[0094] In some embodiments, after the silicon rod is cut in the direction from the surface of the silicon rod opposite to the carrier plate to the surface bonded to the carrier plate in step S300 to obtain a plurality of silicon wafers, the slicing method further comprises the following steps:

[0095] Step S400, the cutting line and the carrier plate are relatively moved in a direction opposite to the cutting direction until the cutting line is out of contact with the silicon wafer. Specifically, the crystal support, the carrier plate and the silicon wafer are driven to be lifted upward relative to the cutting line, so that the cutting line is gradually moved out of the silicon wafer from the position in the carrier plate, and the adjacent silicon wafers adsorbed together are separated.

[0096] Step S500, debonding the silicon wafer from the carrier plate, that is, debonding the silicon wafer so as to separate the silicon wafer from the carrier plate to obtain multiple independent silicon wafers, thus completing the entire slicing process of the silicon rod.

[0097] Furthermore, after the silicon rods are sliced ​​and silicon wafers are obtained, they can be inserted, cleaned and sorted in sequence to finally obtain silicon wafers of qualified quality. Specifically, when inserting the wafers, the silicon wafers are inserted into the basket, and the side of the silicon wafer with the groove faces the bottom rod of the basket, that is, the side of the silicon wafer with the groove is supported by the bottom rod to avoid collision between the side of the silicon wafer with the side rod or the teeth of the basket, thereby avoiding hidden cracks or damage to the silicon wafer. When cleaning, the basket carrying the silicon wafers is placed in a cleaning tank for cleaning. The cleaning can be repeated multiple times, and water washing, alkali washing, acid washing, etc. can be performed as needed.

[0098] Of course, the groove of the silicon wafer facing the bottom rod of the basket is not limited to the silicon wafer insertion, cleaning and sorting processes, but also applies to the silicon wafer insertion into the basket in the process sections of batteries and components. And in the silicon wafer flat washing and battery wet process section, the groove of the silicon wafer should be parallel to the conveying direction of the conveying rod to avoid damage to the groove.

[0099] Based on the silicon wafer described in any of the above embodiments, the present invention also provides a solar cell, including the silicon wafer described in any of the above embodiments. Since the solar cell adopts the silicon wafer described in any of the above embodiments, it has the same beneficial effects as the silicon wafer, which will not be described in detail.

[0100] The embodiment of the present invention also provides a photovoltaic module, including at least two cells arranged in a shingle shape and a conductive interconnection connecting adjacent cells, the cell is a solar cell as described in any of the above embodiments, the conductive interconnection passes through the groove of the solar cell, and the two ends of the conductive interconnection are respectively connected to the front component and the back component of the adjacent solar cell. Since the photovoltaic module adopts the solar cell described above, it has the same beneficial effects as the solar cell, which will not be described in detail. In addition, the solar cell of the photovoltaic module has a groove, and the conductive interconnection can pass through the groove. Therefore, there is no gap at the overlap of the two solar cells, that is, the overlapping position, which can increase the area of ​​the cell under the same area and improve the power generation efficiency.

[0101] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0102] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A silicon wafer, characterized in that: The silicon wafer has a groove, and the surface of the silicon wafer has a plurality of cutting lines, the cutting lines extend along a group of opposite sides of the silicon wafer, and the groove is located on at least one side of another group of opposite sides of the silicon wafer.

2. The silicon wafer according to claim 1, characterized in that: The grooves are formed on two opposite sides of the silicon wafer.

3. The silicon wafer according to claim 1, characterized in that: The distance between two adjacent cutting marks on the surface of the silicon wafer is 1 mm to 4 mm.

4. The silicon wafer according to claim 1, characterized in that: The cutting line mark is arc-shaped, and the distance from the arc bottom to the arc top of the cutting line mark is greater than 1 mm and less than 17 mm.

5. The silicon wafer according to claim 1, characterized in that: The strength uniformity of the silicon wafer is greater than or equal to 90%.

6. The silicon wafer according to claim 1, characterized in that: The mechanical strength of the silicon wafer is greater than or equal to 2N.

7. The silicon wafer according to any one of claims 1 to 5, characterized in that: The groove depth of the groove is 0.3 mm to 1 mm.

8. The silicon wafer according to any one of claims 1 to 5, characterized in that: The total groove width of the groove is 5% to 15% of the side length of the side where the groove is located.

9. The silicon wafer according to any one of claims 1 to 5, characterized in that: The groove width of the groove is 0.5 mm to 2 mm.

10. The silicon wafer according to claim 1, characterized in that: The distance between two adjacent grooves is 8 mm to 13 mm.

11. A method for processing a silicon wafer, characterized in that: include: Providing a silicon rod, wherein the silicon rod has two opposite surfaces, at least one of the surfaces is provided with a groove; Bonding the silicon rod to a carrier plate so that a surface of the silicon rod having the groove or a surface opposite to the groove is close to the carrier plate; The silicon rod is cut along the direction from the surface of the silicon rod opposite to the supporting plate to the surface bonded to the supporting plate to obtain a plurality of silicon wafers, wherein at least one side of the silicon wafer has the groove, the cutting line marks obtained by cutting extend along a group of opposite sides of the silicon wafer, and the groove is located on at least one side of the other group of opposite sides of the silicon wafer.

12. The method for processing a silicon wafer according to claim 11, characterized in that: The cutting of the silicon rod to obtain a plurality of silicon wafers includes adjusting the tension of the cutting wire mesh to 2N-5N so that the distance between the arc bottom and the arc top of the cutting line mark is less than 17mm and greater than 1mm.

13. The method for processing a silicon wafer according to claim 11, characterized in that: The method comprises machining a plurality of grooves which are parallel to each other and arranged at intervals by a grinding wheel assembly, and specifically comprising: A plurality of coarse grinding grooves which are parallel to each other and arranged at intervals are processed by a coarse grinding wheel assembly; And / or, a plurality of mutually parallel and spaced fine grinding grooves are processed by a fine grinding wheel assembly.

14. The method for processing a silicon wafer according to claim 13, characterized in that: Before or after machining the plurality of grooves that are parallel to each other and arranged at intervals by the grinding wheel assembly, the machining method further comprises: grinding the surface.

15. A solar cell comprising a silicon wafer, characterized in that: The silicon wafer is the silicon wafer as described in any one of claims 1 to 10.

16. A photovoltaic module, comprising at least two cells and a conductive interconnector connecting adjacent cells, characterized in that: The cell is the solar cell according to claim 15, the conductive interconnect passes through the groove of the solar cell, and two ends of the conductive interconnect are respectively connected to the front component and the back component of the adjacent solar cell.

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