Accelerator state control device, accelerator state control system, accelerator state control method, and program

Abstract

An accelerator state control device (100) is provided with: an input amount acquisition / prediction unit (110) that predicts the amount of throughput to be unloaded to an accelerator (12) and outputs the prediction result as the traffic volume and the fluctuation range thereof; a processing capability setting recording unit (150) that stores information on the type and model of the accelerator and setting information corresponding to the processing performance as list information, extracts the information from the list information in response to the inquiry, and responds to the extracted information; an ACC processing capability / power consumption setting determination unit (120) that determines setting information about the processing capability and the fluctuation time of the accelerator on the basis of the traffic volume, the fluctuation range, and the list information; and an ACC processing capability / power consumption setting input unit (130) that reflects the setting information to the accelerator (12) on the basis of the setting information to the accelerator (12) determined by the ACC processing capability / power consumption setting determination unit (120).

Description

Technical Field

[0001] The present invention relates to an accelerator state control device, an accelerator state control system, an accelerator state control method and a program. Background Art

[0002] Depending on the type of processor, the workloads that the processor is good at (with high processing power) are different. Compared with the highly versatile CPU (Central Processing Unit), there are accelerators (hereinafter appropriately referred to as ACC) such as FPGA (Field Programmable Gate Array) / (in the following description, " / " means "or") GPU (Graphics Processing Unit) / ASIC (Application Specific Integrated Circuit) that can quickly and efficiently calculate high-parallel workloads that the CPU is not good at (with low processing power). By combining these different types of processors, the workloads that the CPU is not good at are offloaded to the ACC for calculation, and the effective use of offloading technology to improve the overall calculation time and calculation efficiency is underway.

[0003] In vRAN (virtual Radio Access Network), when CPU performance alone is insufficient to meet requirements, part of the processing is offloaded to an accelerator capable of high-speed computing, such as an FPGA or a GPU.

[0004] Representative examples of specific workloads to be offloaded by ACC include encoding / decoding processing (FEC: Forward Error Correction processing) in vRAN, media processing of audio and video, and encryption / decryption processing.

[0005] In computer systems, sometimes hardware corresponding to general processing (CPU) and hardware dedicated to specific operations (accelerator) are installed on a computer (hereinafter referred to as an accelerator-equipped server), and part of the operation processing is offloaded from the general processor of the software operation to the accelerator.

[0006] Furthermore, with the development of cloud computing, it is becoming increasingly common to simplify the configuration of a client by offloading a portion of computationally intensive processing from a client at a user site to a server at a remote site (such as a data center located near the user) via a network (NW).

[0007] Fig.17 A diagram illustrating a computer system.

[0008] like Fig.17 As shown, in the server 50, the hardware 10 includes: a CPU 11; an accelerator 12 having an accelerator operation circuit / program 12a; an input / output unit 13 and a cooling mechanism (fan, etc.) 14, and an application program (hereinafter referred to as APL) 1 having software 20 that operates on the CPU 11 on the server 50. It should be noted that although the cooling mechanism (fan, etc.) 14 is shown to be mounted on Fig.17 This is an example of hardware 10, but it can also be installed on hardware different from hardware 10.

[0009] The server 50 receives input data from the outside, performs calculations on the data within the server, and then outputs the data to the outside.

[0010] The application 1 calls a set of functions (API) defined as a standard to offload a part of the processing to the accelerator 12 .

[0011] The accelerator 12 is a computing accelerator device such as FPGA / GPU. The accelerator 12 has an accelerator computing circuit / program 12a and performs computing using the accelerator computing circuit / program 12a.

[0012] It should be noted that the accelerator 12 may fail with a certain probability due to a failure of the cooling fan or the like.

[0013] The input / output unit 13 receives input data and outputs it.

[0014] Fig.18 This is a diagram for explaining fluctuations in the traffic volume of input data to the input / output unit 13 of the server 50 .

[0015] like Fig.18 As shown in FIG. 1 , the traffic volume of input data fluctuates in a time series. For example, the traffic volume in urban areas of RAN (Radio Access Network) is high during the day and low at night.

[0016] In the server 50 , the requirements for minimizing the power consumption related to the accelerator 12 and its cooling while maintaining responsiveness to input data within a certain period of time are as follows.

[0017] Requirement 1: [Electrical power efficiency]

[0018] The power consumption required for computing and cooling the accelerator 12 with respect to the input data of the server 50 is minimized.

[0019] Requirement 2: [Responsiveness]

[0020] The input data is processed by the server 50 within a certain time from the time of input.

[0021] Requirement 3: [Response to multiple accelerators]

[0022] Able to handle various accelerators such as FPGA, ASIC, GPU, etc.

[0023] Fig.19 It is a graph showing the processing capacity and surplus of the server during fluctuations in the traffic volume of input data. Fig.19 The solid line represents the business volume of input data. Fig.19 The dashed line represents the server processing power (≈ power consumption). Fig.19 As shown by the dashed line in , the processing power and power consumption of the server are fixed. Fig.19 As shown by the solid line, the processing capacity of the server is surplus with business fluctuations. Especially at night when the business volume is small, the server processing capacity (≈ power consumption) is too large, resulting in low efficiency in power consumption.

[0024] In an accelerator-mounted server, there is a conventional technology that achieves high responsiveness and high power efficiency for a certain amount of processing for each accelerator type.

[0025] Prior art 1: Power-saving circuit design technology corresponding to specific business volume

[0026] Non-patent document 1 describes a technique for optimizing the minimum required circuit scale to the minimum scale for each specific processing amount / model in the circuit design of FPGA / ASIC, thereby minimizing the power consumption of ACC.

[0027] Conventional technology 2: Changing the balance between processing power and power consumption by changing the clock frequency

[0028] Non-patent document 2 describes a technique for changing the balance between processing performance and electric power consumption (setting and shifting to a constant value) by changing the operating frequency.

[0029] Prior art 3: Output setting of cooling mechanism required for stable operation of accelerator

[0030] Non-Patent Document 3 describes a configuration in which a fan is always operated at maximum output in order to achieve stable operation regardless of operating circuit information.

[0031] Prior art literature

[0032] Non-patent literature

[0033] Non-Patent Document 1: “Power-aware FPGA Design White Paper”, [Online], [retrieved on July 6, 2019], Internet 〈URL: https: / / www.microsemi.com / document-portal / doc_download / 131579-power-aware-fpga-design-white-paper〉

[0034] Non-patent document 2: “FPGA Frequency Setting Change Command Guide (Intel OPAE Tool kit), [Online], [retrieved on July 6, 2019], Internet 〈URL: https: / / opae.github.io / latest / docs / fpga_tools / userclk / userclk.html〉

[0035] Non-patent document 3: "Intel N3000 Server Configuration Guide", [Online], [retrieved on July 6, 2019], Internet 〈URL: https: / / jp.fujitsu.com / platform / server / primergy / products / note / svsdvd / dvd / pdf / intelpac_n3000-qsg-1.1-jp.pdf〉 Summary of the invention

[0036] Problems to be solved by the invention

[0037] The prior art techniques described in Non-Patent Documents 1 to 3 can achieve a configuration with high electric power efficiency while maintaining responsiveness by preparing and setting settings corresponding to a certain amount of processing volume for each accelerator.

[0038] However, when the input amount fluctuates in a time series, excess processing capacity / power consumption is generated, and for fluctuating business, there is a problem that requirement 1: [electric power efficiency], requirement 2: [responsiveness], and requirement 3: [handling of multiple accelerators] cannot be satisfied simultaneously.

[0039] The present invention has been made in view of such a background, and an object of the present invention is to achieve high electric power efficiency of various accelerators while ensuring responsiveness according to a fluctuating amount of input data.

[0040] Solutions for solving problems

[0041] In order to solve the above-mentioned problems, the present invention adopts an accelerator state control device, which controls the state of the accelerator when the specific processing of the application is offloaded to the accelerator for calculation processing, and is characterized in that it comprises: a prediction unit, which predicts the fluctuation of the input data volume based on the acquired input data volume, and outputs the prediction result as the business volume and its fluctuation range; a processing capacity setting recording unit, which saves the information of the accelerator type and model and the setting information corresponding to the processing performance as overview information, and retrieves and responds from the overview information according to the query; a judgment unit, which judges the setting information of the processing capacity and fluctuation time of the accelerator based on the business volume and fluctuation range output from the prediction unit and the overview information read from the processing capacity setting recording unit; and a setting input unit, which reflects the setting information to the accelerator based on the setting information to the accelerator judged by the judgment unit.

[0042] Effects of the Invention

[0043] According to the present invention, high electric power efficiency of various accelerators can be achieved while ensuring responsiveness according to the fluctuating amount of input data. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a schematic configuration diagram of an accelerator state control system according to an embodiment of the present invention.

[0045] Figure 2 It is a schematic configuration diagram showing a variation of the arrangement of an accelerator state control device of the accelerator state control system according to the embodiment of the present invention.

[0046] Figure 3 This is a diagram showing list information for explaining an electric power reduction method of an accelerator state control device of an accelerator state control system according to an embodiment of the present invention.

[0047] Figure 4 This is a diagram showing an example of circuit information by processing capacity stored in an ACC circuit information recording unit by processing capacity of an accelerator state control device of an accelerator state control system according to an embodiment of the present invention.

[0048] Figure 5 It is a diagram showing a processing performance estimation table based on the traffic volume stored in the ACC circuit information recording unit for each processing capacity of the accelerator state control device of the accelerator state control system according to the embodiment of the present invention.

[0049] Figure 6 It is a diagram showing an accelerator mounting relationship management table stored in an ACC circuit information recording unit for each processing capacity of an accelerator state control device of an accelerator state control system according to an embodiment of the present invention.

[0050] Figure 7 It is a diagram showing an accelerator list management table stored in an ACC circuit information recording unit for each processing capacity of an accelerator state control device of an accelerator state control system according to an embodiment of the present invention.

[0051] Figure 8 It is a diagram showing an accelerator type management table stored in an ACC circuit information recording unit for each processing capability of an accelerator state control device of an accelerator state control system according to an embodiment of the present invention.

[0052] Fig. 9 This is a flowchart showing <operation sequence 1> in a case where the power saving control of the accelerator state control device of the accelerator state control system according to the embodiment of the present invention is started from the prediction of the input amount of function 1.

[0053] Fig.10 This is a flowchart showing <Operation Sequence 2> in the case where the power saving control of the accelerator state control device of the accelerator state control system according to the embodiment of the present invention is started from the periodic execution.

[0054] Fig.11 This is a diagram showing details of the list information of the electric power reduction method of the accelerator state control device of the accelerator state control system according to the embodiment of the present invention.

[0055] Fig. 12A This is a flowchart showing an example of a setting sequence of an electric power reduction method of an accelerator state control device of an accelerator state control system according to an embodiment of the present invention.

[0056] Fig. 12B This is a flowchart showing an example of a setting sequence of an electric power reduction method of an accelerator state control device of an accelerator state control system according to an embodiment of the present invention.

[0057] Fig. 12C This is a flowchart showing an example of a setting sequence of an electric power reduction method of an accelerator state control device of an accelerator state control system according to an embodiment of the present invention.

[0058] Fig.13 This is a flowchart showing an operation sequence 1 of the bypass type accelerator state control device of the accelerator state control system according to the embodiment of the present invention.

[0059] Fig.14 This is a flowchart showing an operation sequence 1 of an inline type accelerator state control device of the accelerator state control system according to the embodiment of the present invention.

[0060] Fig.15It is a diagram for explaining the processing capacity / power consumption and surplus achieved by the accelerator state control device of the accelerator state control system according to the embodiment of the present invention.

[0061] Fig.16 This is a hardware configuration diagram showing an example of a computer that realizes the function of the accelerator state control device of the accelerator state control system according to the embodiment of the present invention.

[0062] Fig.17 is a diagram illustrating a computer system.

[0063] Fig.18 This is a diagram for explaining fluctuations in the volume of input data traffic to the input / output unit of the server.

[0064] Fig.19 This is a diagram showing the processing capacity and surplus of the server during fluctuations in the volume of input data traffic. DETAILED DESCRIPTION

[0065] Hereinafter, an accelerator state control system and the like in a mode for carrying out the present invention (hereinafter referred to as “this embodiment”) will be described with reference to the drawings.

[0066] (Implementation Method)

[0067] [summary]

[0068] Figure 1 It is a schematic configuration diagram of an accelerator state control system according to an embodiment of the present invention.

[0069] like Figure 1 As shown, the accelerator state control system 1000 includes a server 200 , an antenna device 210 , and a post-processing device 220 .

[0070] The accelerator state control system 1000 includes: an accelerator state control device 100 for controlling the state of the accelerator 12 when offloading specific processing of the application 1 to the accelerator 12 for computing; and a cooling mechanism 14 for cooling the computing device including the accelerator 12 .

[0071] [Server 200]

[0072] Server 200 is a distributed unit (Distributed Unit) in 5G signal processing.

[0073] The server 200 includes hardware (HW) 10 and software 20 .

[0074] Hardware 10

[0075] The hardware 10 includes a CPU (Central Processing Unit) 11 , an accelerator 12 , an input / output unit 13 , and a cooling mechanism (a fan, etc.) 14 .

[0076] <cpu11>

[0077] The CPU 11 executes processing of the application program 1 and also executes software of each functional unit in the server 200 .

[0078] <Accelerator 12>

[0079] The accelerator 12 is a computing accelerator device such as FPGA / GPU.

[0080] The accelerator 12 is a computer dedicated to specific processing and mounted on the server 200. As a method of connecting to the CPU 11 via a bus, there are methods such as an ASIC-mounted accelerator, an FPGA-mounted accelerator, and a GPU.

[0081] The data processed by the accelerator 12 is a look-aside method except for the data input from the CPU 11 (Sequence 2-1: Fig.13 ) can also be an inline method directly input from the input / output unit 13 such as a NIC (Sequence 2-2: Fig.14 ). Figure 1 The signal line with an arrow pointing from the CPU 11 to the accelerator 12 is (sequence 2-1: Fig.13 ) is shown in the bypass type ACC unloading case. In addition, the connection Figure 1 The bidirectional signal line between the input-output unit 13 and the accelerator 12 is (sequence 2-2: Fig.14 ) exists in the case of inline ACC unloading as shown in the example.

[0082] The accelerator 12 has an accelerator operation circuit / program 12a. The accelerator operation circuit / program 12a is a circuit or program loaded on the accelerator 12. The accelerator operation circuit / program 12a refers to FPGA circuit information when the accelerator 12 is an FPGA, and refers to a program for the GPU when the accelerator 12 is a GPU.

[0083] It should be noted that the accelerator 12 may fail with a certain probability due to a failure of the cooling mechanism (fan, etc.) 14 or the like.

[0084] <Input / Output Section 13>

[0085] The input / output unit 13 is an input / output mechanism such as a NIC (Network Interface Card) and performs data input / output with external devices (antenna device 210, post-processing device 220). The input / output unit 13 has an interface for notifying the application 1 of the current data input amount.

[0086] <Cooling mechanism 14>

[0087] The cooling mechanism 14 is a mechanism for cooling the entire computing devices (CPU 11, accelerator 12) of the server 200. The cooling mechanism 14 can change the cooling performance, and the power consumption changes accordingly. The cooling mechanism 14 receives the setting of the cooling performance as an input.

[0088] The cooling mechanism 14 is a mechanism that cools the entire server including the CPU and the accelerator, but may be an independent cooling mechanism that cools only the CPU or only the accelerator.

[0089] Software 20

[0090] The software 20 includes an application program 1 and an accelerator state control device 100 for controlling an accelerator state.

[0091] <Application 1>

[0092] The application 1 is a program for signal processing and runs on the CPU 11. Some special processing such as parallel computing processing that is not suitable for the CPU is offloaded to the accelerator 12. For example, the application 1 calls a function group (API) defined as a standard to offload part of the processing to the accelerator 12.

[0093] Here, when the setting of the accelerator is changed and the corresponding accelerator is temporarily unavailable, the processing continuing unit 160 performs unloading when switching to ACC.

[0094] The application program 1 receives processing target data as input from the input / output unit 13 and passes calculated data to the input / output unit 13 as output.

[0095] [Accelerator state control device 100]

[0096] The accelerator state control device 100 includes: an input amount acquisition / prediction unit 110 (prediction unit, prediction process), an ACC processing capacity / power consumption setting judgment unit 120 (judgment unit, judgment process), an ACC processing capacity / power consumption setting input unit 130 (setting input unit, setting input process), an ACC circuit information recording unit 140 according to processing capacity, an ACC information / processing capacity setting recording unit 150 (processing capacity setting recording unit, processing capacity setting recording process) and an ACC switching processing continuation unit 160 (processing continuation unit).

[0097] <Input Amount Acquisition / Prediction Unit 110>

[0098] The input amount acquisition / prediction unit 110 predicts the amount of processing to be offloaded to the accelerator, and outputs the prediction result as the business volume and its fluctuation range. In this embodiment, the fluctuation of the input data volume is predicted as a scheme for predicting (estimating) the amount of processing to be offloaded to the accelerator. As long as the amount of processing to be offloaded to the accelerator can be predicted (estimated), any scheme can be used.

[0099] The input volume acquisition / prediction unit 110 predicts the fluctuation of the input data volume based on the acquired input data volume, and outputs the prediction result as the business volume and its fluctuation amplitude. Specifically, the input volume acquisition / prediction unit 110 acquires the input data volume of the server and predicts the subsequent fluctuation of the input data volume. The input volume acquisition / prediction unit 110 receives the input data volume of the server as input, and outputs the business volume and the unit of fluctuation time after a certain period of time as the prediction result of the future data volume.

[0100] Example 1 of prediction function

[0101] It is possible to consider predicting future changes based on past changes in business volume. For example, based on the business volume of the past five times acquired at a certain period, determine whether the business volume is on an increasing trend. Linearly approximate the five business volumes, and if the slope obtained is above a certain value, it is considered to be an increase, and if it is below a certain value, it is considered to be a decrease, to predict the business volume after a certain period of time. Moreover, based on the variance of each business volume, the unit of fluctuation time is output. Specifically, in the case of a large variance, it is assumed that there will be business volume fluctuations in a short period of time, so the "second level" is output, and in the case of a small variance, the "minute" level is output.

[0102] Example 2 of prediction function

[0103] Alternatively, the traffic volume of each week / time period of the corresponding device is recorded in advance and traffic forecast is performed based on this. For example, in the traffic volume in the wireless access network of mobile phones, the time transition of the traffic volume at each location is different. For example, the traffic volume in the city center is large during the day and small at night. In addition, the traffic volume along the railway line is extremely small outside the tram operation time. Such results can be used to predict the traffic volume every hour. It should be noted that in the case of the method of Example 2 using the prediction function, the unit of the fluctuation time of the traffic volume is longer, becoming a "minute, hour" unit.

[0104] In the prediction of traffic volume, other factors that determine the traffic volume of the corresponding server device can also be used. For example, in the case of the traffic volume in the radio access network of a mobile phone, the number of people traveling fluctuates according to the weather, and the traffic volume of the device connected to the antenna device near a crowded outdoor area fluctuates accordingly. In such an application example, the fluctuation of the traffic volume can also be predicted based on the prediction result of the weather. It should be noted that when using this method, the unit of the fluctuation time of the traffic volume is relatively long, being in the units of "minutes, hours".

[0105] Prediction function regarding the input data size

[0106] In addition to the method of estimating according to the time period, the prediction function of the input data size can also be configured to estimate according to other factors. For example, the fluctuations in traffic volume caused by weather, events, etc. that are possessed by the RIC (RAN Intelligent Controller) in the RAN (Radio Access Network) can also be used as information sources.

[0107] Examples of fluctuations in the time series of the input data volume

[0108] In vRAN, the input data volume to the server depends on the number and traffic volume of mobile phone terminals in the area responsible for the server. The number and traffic volume of mobile phone terminals depend on human activities. The traffic volume increases during the time period / area where people gather, and conversely, the traffic volume decreases during the time period / area where people do not gather. For example, the traffic volume during the daytime on weekdays in the central business district is large, while the traffic volume at night and on holidays is small. In addition, regarding the suburban residential area, the traffic volume on holidays is larger than that on weekdays during the daytime.

[0109] <ACC processing capacity / power consumption setting judgment unit 120>

[0110] The ACC processing capacity / power consumption setting judgment unit 120 is based on the traffic volume and the fluctuation amplitude output from the input volume acquisition / prediction unit 110 and the list information read from the ACC information / processing capacity setting record unit 150 ( Figure 3 ), to judge the setting of the processing capacity and the fluctuation time of the accelerator.

[0111] Specifically, the ACC processing capacity / power consumption setting judgment unit 120 judges the setting of the processing capacity and the fluctuation time of the accelerator according to the prediction result of the traffic volume output from the input volume acquisition / prediction unit 110 and the assumed fluctuation amplitude.

[0112] The ACC processing capacity / power consumption setting determination unit 120 inputs the traffic volume to the ACC information / processing capacity setting recording unit 150, and obtains a list of applicable accelerators and settings ( Figure 3 ). From this list of settings, it selects the accelerator settings and the settings of the cooling mechanism 14 that are suitable for the processing capacity and the fluctuation time, and notifies them to the ACC processing capacity / power consumption setting input unit 130.

[0113] The ACC processing capacity / power consumption setting determination unit 120 receives the prediction of the traffic volume and the fluctuation range as inputs from the input volume acquisition / prediction unit 110. The ACC processing capacity / power consumption setting determination unit 120 transmits the ACC setting information as an output to the ACC processing capacity / power consumption setting input unit 130.

[0114] <ACC processing capacity / power consumption setting input unit 130>

[0115] The ACC processing capacity / power consumption setting input unit 130 reflects the setting information on the accelerator 12 according to the setting information on the accelerator 12 determined by the ACC processing capacity / power consumption setting determination unit 120.

[0116] Specifically, the ACC processing capacity / power consumption setting input unit 130 reflects the input settings for the accelerator 12 and the cooling mechanism 14 on the accelerator 12 and the cooling mechanism 14 respectively. The ACC processing capacity / power consumption setting input unit 130 receives the setting information for the accelerator 12 and the cooling mechanism 14 from the ACC processing capacity / power consumption setting determination unit 120 as inputs. The ACC processing capacity / power consumption setting input unit 130 reflects the setting information on the accelerator 12 and the cooling mechanism 14 respectively as outputs.

[0117] In addition, for the ACC processing capacity / power consumption setting input unit 130, the accelerator generally reflects the setting information through frequency change and / or power-off, and in the case of FPGA, it reflects the setting information through circuit rewriting, and in the case of GPU, it reflects the setting information through sleep.

[0118] <ACC circuit information recording unit 140 according to processing capacity>

[0119] The ACC circuit information recording unit 140 according to processing capacity stores the FPGA circuit information corresponding to the processing performance and the information of the FPGA category for each FPGA category, and responds with the FPGA circuit information and the FPGA category information according to the inquiry. In this case, the ACC circuit information recording unit 140 according to processing capacity responds to the ACC processing capacity / power consumption setting determination unit 120 via the ACC information / processing capacity setting recording unit 150 or directly.

[0120] The ACC circuit information recording unit 140 according to processing capabilities saves multiple pieces of FPGA circuit information corresponding to processing performance for each FPGA category, and issues the FPGA circuit information in response to an inquiry. The inquiry includes information on the FPGA category ( Figure 4 ).

[0121] The ACC circuit information recording unit 140 according to processing capabilities receives the information on the FPGA model as input from the ACC information / processing capability setting recording unit 150. The ACC circuit information recording unit 140 according to processing capabilities responds with multiple pieces of FPGA circuit information to the ACC information / processing capability setting recording unit 150 as output.

[0122] Alternatively, "required processing performance" can be added to the above inquiry, and the ACC circuit information recording unit 140 according to processing capabilities responds with only one optimal FPGA circuit information based on this information. Regarding the response of the FPGA circuit information, it can also be not the actual data of the FPGA circuit information itself, but an identifier such as a file path or pointer required for access that can uniquely identify the circuit information.

[0123] <ACC information / processing capability setting recording unit 150>

[0124] The ACC information / processing capability setting recording unit 150 saves information on the accelerator category and model; and setting information corresponding to processing performance as list information 170( Figure 3 ), and extracts and responds from the list information 170 according to an inquiry. Here, the above information on the accelerator category and model is the information on the accelerator held by the host on which the accelerator can be usefully mounted.

[0125] The ACC information / processing capability setting recording unit 150 receives the accelerator category and model, and the application name as input from the ACC processing capability / power consumption setting judgment unit 120. The ACC information / processing capability setting recording unit 150 responds with a list of setting methods applicable to the corresponding accelerator to the ACC processing capability / power consumption setting judgment unit 120 as output. In addition, when the input accelerator category is FPGA, the ACC information / processing capability setting recording unit 150 makes an inquiry to the ACC circuit information recording unit 140 according to processing capabilities based on the model information, and obtains a list of corresponding suitable FPGA circuit information.

[0126] <ACC processing continuation unit 160 during switching>

[0127] The ACC switching processing continuation unit 160 temporarily continues the processing in the CPU 11 or another accelerator in order to continue the service when the calculation function of the accelerator 12 is temporarily stopped due to the input of the setting information of the ACC processing capacity / power consumption setting input unit 130. When the setting of the accelerator 12 is changed, it is activated when the calculation in the corresponding accelerator 12 is temporarily stopped.

[0128] Regarding the ACC switching processing continuing unit 160 , when this functional unit is activated, the calculation offload from the application 1 is accepted by this functional unit, and the calculation is performed using the calculation resources other than the setting change target.

[0129] It should be noted that, in addition to continuing the calculation using the CPU, another method of temporarily using another accelerator to continue the calculation may also be adopted.

[0130] [Antenna device 210]

[0131] The antenna device 210 is an antenna and a transceiver unit (hereinafter, the antenna, the transceiver unit, and its power supply unit are collectively referred to as "antenna device") for wireless communication with a terminal (UE: User Equipment). Transmitted data is connected to a signal processing device (server 200) of a base station (BBU: Base Band Unit) through a dedicated cable, for example.

[0132] The antenna device 210 includes an antenna device data input / output unit 211. The antenna device data input / output unit 211 is a functional unit that transmits a signal generated by the antenna device 210 to the server 200, and is implemented by a NIC or the like.

[0133] [Post-processing device 220]

[0134] The post-processing device 220 is a centralized unit in 5G signal processing.

[0135] The post-processing device 220 includes a post-processing device data input / output unit 221. The post-processing device data input / output unit 221 is a functional unit that receives a signal processing result processed by the server 200, and is implemented by a NIC or the like.

[0136] <Other Implementation Methods>

[0137] In the present embodiment, the input / output unit 13, the CPU 11, and the accelerator 12 are configured as separate hardware. However, the CPU 11, the accelerator 12, and the accelerator operation circuit / program 12a may be integrated as dedicated hardware.

[0138] In other words, if Figure 1 As shown, in addition to the so-called bypass-type accelerator application method of "explicitly unloading the data obtained via the input and output unit 13 such as NIC from the CPU 11 to the accelerator 12", it can also be the so-called inline-type accelerator application method of "NIC / accelerator / CPU" integrated hardware, completing the processing within the same hardware after receiving the data from the NIC".

[0139] Alternatively, the CPU 11 and the accelerator 12 may be mounted on a single chip, such as in a SoC (System on Chip) system.

[0140] [Configuration of accelerator state control device]

[0141] A modification of the arrangement of the accelerator state control device of the accelerator state control system will be described.

[0142] Figure 1 The accelerator state control system 1000 is an example of the software 20 in which the accelerator state control device 100 is disposed on the server 200. The accelerator state control device 100 may also include a part of its functions in another frame outside the server 200, which is exemplified below.

[0143] Figure 2 FIG. 1 is a schematic diagram showing a variation of the configuration of the accelerator state control device of the accelerator state control system. Figure 1 The same components are denoted by the same reference numerals, and description of overlapping parts will be omitted.

[0144] Figure 2 The variation shown is an example of a case where the controller functional unit composed of the input amount acquisition / prediction unit 110, the ACC processing capacity / power consumption setting determination unit 120, the ACC circuit information recording unit 140 for each processing capacity, and the ACC information / processing capacity setting recording unit 150 is set as another frame.

[0145] like Figure 2 As shown, the accelerator state control system 1000A includes an accelerator state control device 100A provided in a separate housing outside the server 200 .

[0146] The software 20 of the server 200 includes the application program 1 , an ACC processing capacity / power consumption setting input unit 130 , and an ACC switching processing continuing unit 160 .

[0147] The controller function unit of the accelerator state control device 100A is disposed outside the server 200 and has Figure 1 The accelerator state control device 100 has the same function.

[0148] The above Figure 2 As shown, by independently configuring part or all of the functions of the accelerator state control device in other frames outside the server 200, it is possible to correspond to the function configuration of the RIC (RAN Intelligent Controller) in the RAN (Radio Access Network).

[0149] Furthermore, by configuring the controller function unit externally, the input volume can be predicted based on the input volume acquisition (function 1) from a plurality of server devices, thereby having the advantage of improving the prediction accuracy of the traffic volume of function 1. For example, in a mobile phone wireless system, when the traffic volume of a processing area in charge of a certain server device increases, it is assumed that the input volume of a nearby processing area will also fluctuate with a lag.

[0150] In addition, a single accelerator state control device can be used for multiple servers 200. This can reduce costs and improve the maintainability of the accelerator state control device. In addition, changes on the server side can be eliminated or reduced, and can be universally applied.

[0151] [Accelerator data structure]

[0152] An overview and characteristics of electric power reduction methods are explained.

[0153] Figure 3 This is a diagram for explaining the list information of the electric power reduction method.

[0154] like Figure 3 As shown in the figure, the power reduction method is divided into: 1. Circuit scale change, 2. Clock control, 3. Power supply control, and 4. Other. Then, for each of the four categories, the power reduction method, ACC processing capacity, power consumption reduction range (difference from the maximum configuration), time required for transition / recovery, application possibility by ACC, and remarks are set. The application possibility of ACC is divided into FPGA, GPU, and ASIC.

[0155] There are four types of methods for controlling the processing capacity and power consumption of the accelerator. The four types of electric power reduction methods differ in the following aspects: the fluctuation range of the ACC processing capacity, the power consumption reduction range, the time required for transition / recovery, and the application possibility of each ACC. In the accelerator state control method, the predicted result of the load and the accelerator of the control object are set separately.

[0156] For example, in "Partial Reconfiguration" of "Electric Power Reduction Method" of "Classification" 1. Circuit Scale Change, the ACC processing capacity is "Small to Large (Regression)", the power consumption reduction range (difference from the maximum configuration) is "~60W", the time required for transition / recovery is "seconds", and the application possibility of ACC is "FPGA". Then, it has the feature of "preparing the optimal circuit information for each performance in advance and rewriting it appropriately according to the load."

[0157] In addition, in 4-2. "ACC switching" of "Classification" 4. Other "Electric Power Reduction Methods", the ACC processing capacity is "small to large (fallback)", the power consumption reduction range (difference from the maximum configuration) is "~60W", the time required for transition / recovery is "seconds", and the application possibilities of ACC are "FPGA, GPU, ASIC". Then, it has the characteristics of "preparing multiple optimal circuits / ACCs for each performance in advance and switching appropriately according to the load amount".

[0158] [Circuit information by processing capability]

[0159] The circuit information by processing capability of the ACC circuit information recording unit 140 by processing capability will be described.

[0160] Figure 4 1 is a diagram showing an example of a database of circuit information by processing capability stored in the ACC circuit information recording unit 140 by processing capability.

[0161] like Figure 4 As shown, the circuit information by processing capability includes FPGA function category, application name, performance, and circuit information file name.

[0162] The ACC circuit information recording unit 140 stores a plurality of FPGA circuit information corresponding to the processing performance for each FPGA type. Figure 4 The circuit information according to processing capability is shown in the figure), and the FPGA circuit information is issued according to the inquiry (hereinafter "issued" means to retrieve the information and respond).

[0163] [Processing volume estimation table]

[0164] The processing performance estimation table (processing volume estimation table) based on the traffic volume stored in the ACC circuit information recording unit 140 for each processing capacity will be described.

[0165] Figure 5 1 is a diagram showing a processing performance estimation table (processing volume estimation table) based on the traffic volume stored in the ACC circuit information recording unit 140 for each processing capacity.

[0166] like Figure 5 As shown, the processing volume estimation table specifies the required processing performance based on the traffic volume. For example, when the traffic volume is "0 bps or more and less than 10 Mbps", the required processing performance is "small".

[0167] [Accelerator loading relationship management table]

[0168] The accelerator mounting relationship management table stored in the ACC circuit information recording unit 140 for each processing capability will be described.

[0169] Figure 6 1 is a diagram showing an accelerator installation relationship management table stored in the ACC circuit information recording unit 140 for each processing capability.

[0170] like Figure 6 As shown, the accelerator-mounted relationship management table stores the corresponding relationship between the mounted host ID and the mounted accelerator ID. Figure 6 In the example, the host Host-1 is equipped with accelerator IDs "1", "2", and "3".

[0171] [Accelerator list management table]

[0172] The accelerator list management table stored in the processing capacity-based ACC circuit information recording unit 140 will be described.

[0173] Figure 7 1 is a diagram showing an accelerator list management table stored in the ACC circuit information recording unit 140 for each processing capability.

[0174] like Figure 7 As shown in FIG. 1 , the accelerator list management table stores the correspondence between the accelerator ID and the accelerator category ID. Figure 7 In the example, accelerator ID "1" specifies accelerator category ID "A", accelerator ID "2" specifies accelerator category ID "B", accelerator ID "3" specifies accelerator category ID "C", and accelerator ID "4" specifies accelerator category ID "D". Accelerator category IDs "A" to "D" are specifically described below. Figure 8 The accelerator category management table is shown.

[0175] [Accelerator category management table]

[0176] The accelerator type management table stored in the ACC circuit information recording unit 140 for each processing capability will be described.

[0177] Figure 8 2 is a diagram showing an accelerator type management table stored in the ACC circuit information recording unit 140 for each processing capability.

[0178] like Figure 8 As shown, the accelerator category management table stores the accelerator category (remarks), performance, and power consumption of each accelerator category ID. For example, accelerator category ID "A" is an accelerator category of "FPGA-small performance", performance of "small~large", and power consumption of "75W". Accelerator category ID "B" is an accelerator category of "FPGA-large performance", performance of "small~large", and power consumption of "200W". Therefore, when the performance of the accelerator category "FPGA" is emphasized, accelerator category ID "B" is selected. In addition, when the performance required is "medium~large", in addition to the accelerator category "FPGA", accelerator category "GPU" of accelerator category ID "C" and accelerator category "ASIC" of accelerator category ID "D" can also be selected. It should be noted that items other than performance and power consumption (for example, application category) can also be managed. For example, when an application performs parallel processing, even if the power consumption is the same, the accelerator category "GPU" is selected.

[0179] The operation of the accelerator state control system 1000 configured as described above will be described below.

[0180] The operation sequence of this embodiment is a power saving control sequence, which includes an operation sequence 1 in which the power saving control starts from the prediction of the input amount of function 1, and an operation sequence 2 in which the power saving control starts from the periodic execution.

[0181] [Action sequence 1]

[0182] Fig. 9 This is a flowchart showing <operation sequence 1> in the case where the power saving control is started from the prediction of the input amount of function 1.

[0183] In step S11 , the input amount acquisition / prediction unit 110 receives the input data amount of the server as input, and outputs the business volume and the unit of fluctuation time after a certain period of time as the prediction result of the future data amount.

[0184] In step S12, the ACC processing capacity / power consumption setting determination unit 120 determines the processing capacity / power consumption setting based on the traffic volume and fluctuation range output from the input volume acquisition / prediction unit 110 and the list information ( Figure 3 ) to determine the processing capability of the accelerator and the setting of the fluctuation time.

[0185] In step S13, the ACC information / processing capacity setting recording unit 150 is installed to save the information of the accelerator type / model installed in each host and an overview of the setting information corresponding to the processing performance, and is issued in response to an inquiry. The ACC information / processing capacity setting recording unit 150 receives the accelerator type and model, and the application name as input from the ACC processing capacity / power consumption setting judgment unit 120. The ACC information / processing capacity setting recording unit 150 responds to the ACC processing capacity / power consumption setting judgment unit with an overview of the setting methods that can be applied to the corresponding accelerator 12 as output. In addition, when the input accelerator type is FPGA, the ACC information / processing capacity setting recording unit 150 inquires the ACC circuit information recording unit 140 by processing capacity based on the model information to obtain an overview of the corresponding suitable FPGA circuit information.

[0186] In step S14, the ACC processing capacity / power consumption setting determination unit 120 determines whether the mounted accelerator 12 is an FPGA. If the mounted accelerator 12 is not an FPGA (S14: No), the process proceeds to step S16.

[0187] When the mounted accelerator 12 is an FPGA (S14: Yes), in step S15, the ACC circuit information recording unit 140 for each processing capability stores the FPGA circuit information and the FPGA type information corresponding to the processing performance for each FPGA type, and responds to the query with the FPGA circuit information and the FPGA type information. In this case, the ACC circuit information recording unit 140 for each processing capability responds to the ACC processing capability / power consumption setting determination unit 120 via the ACC information / processing capability setting recording unit 150 or directly.

[0188] In step S16, the ACC processing capacity / power consumption setting input unit 130 reflects the input settings for the accelerator 12 and the cooling mechanism 14 to the accelerator 12 and the cooling mechanism 14, respectively. The ACC processing capacity / power consumption setting input unit 130 receives the settings for the accelerator 12 and the setting information for the cooling mechanism 14 from the ACC processing capacity / power consumption setting determination unit 120 as input. The ACC processing capacity / power consumption setting input unit 130 reflects the setting information to the accelerator 12 and the cooling mechanism 14, respectively, as output.

[0189] In step S17 the accelerator 12 executes operations dedicated to the specific processing.

[0190] In step S18, the accelerator operation circuit / program 12a loads the accelerator circuit or program and ends the processing of this flowchart. If the accelerator 12 is an FPGA, it is FPGA circuit information, and if the accelerator 12 is a GPU, it is GPU.

[0191] On the other hand, in step S19 , the cooling mechanism 14 cools down all of the computing devices (CPU 11 , accelerator 12 ) of the server and ends the processing of this flowchart.

[0192] [Action Sequence 2]

[0193] Fig.10 This is a flowchart showing <Operation sequence 2> when the power saving control is started from the periodic execution. Fig. 9 The steps that perform the same processing in the process of <Action Sequence 1> are marked with the same symbols and the description is omitted.

[0194] In step S21, the ACC processing capacity / power consumption setting determination unit 120 is activated at regular intervals to determine the accelerator setting corresponding to the processing capacity and fluctuation time of the accelerator 12 based on the predicted result of the traffic volume input from the input volume acquisition / prediction unit 110 and the assumed fluctuation range.

[0195] After step S15, in step S22, the ACC switching processing continuation unit 160 temporarily continues the processing in the CPU 11 or other accelerators in order to continue the service when the calculation function of the accelerator 12 is temporarily stopped with the input of the setting information. Thus, when the setting of the accelerator 12 is changed, it is activated when the calculation in the corresponding accelerator 12 is temporarily stopped.

[0196] After step S18 , in step S23 , the ACC switching processing continuation unit 160 temporarily stops the calculation of the corresponding accelerator when the accelerator setting is changed, and ends the processing of this flowchart.

[0197] In the above, the <operation sequence 1> in which the power saving control is started from the prediction of the input amount of the function 1 and the <operation sequence 2> in which the power saving control is started from the periodic execution are described.

[0198] [Setting sequence of electric power reduction method]

[0199] The accelerator state control device 100 selects an electric power reduction method to be applied according to the traffic volume and the time width of the fluctuation. An example of the electric power reduction method and an example of a load pattern suitable for the electric power reduction method will be described.

[0200] Fig.11 This is a detailed diagram showing the summary information of the electric power reduction method.

[0201] like Fig.11 As shown, for each of the four categories, there are divisions: power reduction method, ACC processing capacity, power reduction range (difference from the maximum configuration), time required for transition / recovery, and suitable load mode. The above four categories are: 1. Circuit scale change, 2. Clock control, 3. Power supply control, and 4. Others. The power reduction range is a calculated value based on a specific configuration (for example, Dell R740 2socket + FPGA N3000).

[0202] For example, when the classification is "1. Circuit scale change" and the power reduction method is "1-1. Write empty design", the appropriate load pattern is "a situation where load fluctuations of the order of minutes occur in a small load". In other words, when "a small load and load fluctuations of the order of minutes" can be allowed, "1-1. Write empty design" is appropriate.

[0203] In particular, when the classification is "4. Others" and the power reduction method is "4-2. ACC switching", the appropriate load pattern becomes "set according to ACC processing capacity in all cases".

[0204] [An example of a setting sequence of the electric power reduction method]

[0205] An example of the setting of the accelerator 12 and the cooling mechanism 14 (fan, etc.) and the determination logic thereof will be described with reference to the flowchart. Each setting amount is an example and changes according to each setting item.

[0206] Figures 12A to 12C This is a flowchart showing an example of a setting sequence of the electric power reduction method. Figures 12A to 12C This is a process, but for the sake of illustration, [A], [B], and [C] are connected as connectors. In addition, the dotted lines that frame each step of the process represent each functional unit that executes the step.

[0207] like Fig. 12A As shown, in step S31 , the ACC processing capacity / power consumption setting determination unit 120 obtains the traffic volume.

[0208] In step S32, the ACC processing capacity / power consumption setting determination unit 120 determines whether the traffic volume has increased or decreased continuously for a certain number of times or more. If the traffic volume has not increased or decreased continuously for a certain number of times or more (S32: No), the process returns to step S31.

[0209] When the traffic volume increases or decreases continuously for a certain number of times or more (S32: Yes), the ACC processing capacity / power consumption setting determination unit 120 is skipped and the process proceeds to step S33.

[0210] In step S33, the ACC information / processing capacity setting recording unit 150 refers to Figure 5 The processing performance estimation table shown is used to estimate the processing performance according to the business volume.

[0211] In step S34, the ACC information / processing capacity setting recording unit 150 refers to Figure 6 The accelerator-mounted relationship management table shown is used to obtain the list of ACCs mounted and their performance.

[0212] Fig. 12B Each step shown in the dotted-line frame is a process in the ACC processing capacity / power consumption setting determination unit 120.

[0213] In step S35 , the ACC processing capacity / power consumption setting determination unit 120 determines which type of ACC satisfies the processing performance.

[0214] When the ACC satisfying the processing performance is the FPGA, it is determined in step S36 which of the following the processing performance matches.

[0215] If the processing performance is "very small", "3. Power control 3-1. ACC card power off" is selected in step S37 ( Fig.11 ), select "4. Other 4-1. Fan control fan setting [minimum]" in step S38 ( Fig.11 ) and proceed to step S48.

[0216] If the processing performance is "small", "1. Circuit scale change 1-2. Partial reconfiguration small scale circuit selection" is selected in step S39 ( Fig.11 ), in step S40, select "2. Clock control 2-1. Operation unit clock control medium frequency [small]" ( Fig.11 ), select "4. Other 4-1. Fan control fan setting [small]" in step S41 ( Fig.11 ) and proceed to step S48.

[0217] If the processing performance is "medium", in step S42, "1. Circuit scale change 1-2. Medium scale circuit selection in partial reconfiguration" is selected. Figure 3 ), in step S43, select "2. Clock control 2-1. Operation unit clock control medium frequency [medium]" ( Fig.11 ), select "4. Others 4-1. Fan control fan setting [medium]" in step S44 ( Fig.11 ) and proceed to step S48.

[0218] If the processing performance is "large", in step S45, "1. Circuit scale change 1-2. Large-scale circuit selection in partial reconstruction" is selected. Figure 3 ), in step S46, select "2. Clock control 2-1. Operation unit clock control frequency [large]" ( Fig.11 ), select "4. Other 4-1. Fan control fan setting [large]" in step S47 ( Fig.11 ) and proceed to step S48.

[0219] In step S48, when the calculation function of the accelerator 12 is temporarily stopped with the input of the setting information, the ACC switching processing continuing unit 160 temporarily continues (activates) the processing in the CPU 11 or other accelerators in order to continue the service and proceeds to step S58. Thus, when the setting of the accelerator is changed, the calculation in the corresponding accelerator is activated when it is temporarily stopped.

[0220] When the ACC processing capacity / power consumption setting determination unit 120 determines in step S35 that the ACC that satisfies the processing performance is a GPU or an ASIC, it determines in step S49 which of the following the processing performance matches.

[0221] If the processing performance is "very small", "3. Power control 3-1. ACC card power off" is selected in step S50 ( Fig.11 ), select "4. Other 4-1. Fan control fan setting [minimum]" in step S51 ( Fig.11 ) and proceed to step S58.

[0222] If the processing performance is "small", "2. Clock control 2-1. Operation unit clock control frequency [small]" is selected in step S52 ( Fig.11 ), in step S53, select "4. Other 4-1. Fan control fan setting [small]" ( Fig.11 ) and proceed to step S58.

[0223] If the processing performance is "medium", "2. Clock control 2-1. Calculation unit clock control medium frequency [medium]" is selected in step S54. Fig.11 ), select "4. Others 4-1. Fan control fan setting [medium]" in step S55 ( Figure 3 ) and proceed to step S58.

[0224] If the processing performance is "high", "2. Clock control 2-1. Operation unit clock control frequency [high]" is selected in step S56. Figure 3 ), select "4. Other 4-1. Fan control fan setting [large]" in step S57 ( Figure 3 ) and proceed to step S58.

[0225] exist Fig. 12C In step S58 shown, the ACC processing capacity / power consumption setting input unit 130 inputs the setting to the ACC / fan.

[0226] In step S59, the ACC switching process continuing unit 160 determines whether the ACC switching process continuing function is executed. If the ACC switching process continuing function is not executed (S59: No), the process of this flow is terminated.

[0227] When the ACC switching process continuation function is executed ( S59 : YES), in step S60 , the ACC switching process continuation unit 160 disables the operation of the corresponding accelerator to be temporarily stopped when the accelerator setting is changed and ends the process of this flow.

[0228] Based on the above Fig.11 and FIG. 12A to FIG. 12C , the setting sequence of the electric power reduction method is explained.

[0229] [Data processing sequence of action sequence 1]

[0230] The data processing sequence of action sequence 1 will be described. The data processing sequence of action sequence 2 is the same.

[0231] The data processing sequences of action sequence 1 are divided into "bypass type (CPU actively unloads the processing data of ACC to ACC)" and "inline type (CPU actively unloads the processing data of ACC to ACC)". They are explained below in turn.

[0232] Fig.13 This is a flowchart showing a data processing sequence of a bypass type action sequence 1.

[0233] In step S61 , the antenna device data input / output unit 211 transmits a signal generated by the antenna device 210 to the server 200 .

[0234] In step S62 , the input / output unit 13 performs data input / output with external devices (antenna device 210 , post-processing device 220 ).

[0235] In step S63, the application 1 is operated by the CPU 11 and performs signal processing. The application 1 offloads to the accelerator 12 some special processing that is not suitable for the CPU 11, such as some parallel computing processing.

[0236] In step S64 the accelerator 12 performs operations dedicated to the specific processing.

[0237] In step S65, the application 1 receives the processing target data from the input / output unit 13 and transmits the calculated data to the input / output unit 13. When the accelerator 12 is temporarily unavailable when the setting of the accelerator 12 is changed, the application 1 is unloaded by the processing continuing unit 160 when switching to ACC.

[0238] In step S66 , the input / output unit 13 performs data input / output with the external device (antenna device 210 , post-processing device 220 ).

[0239] In step S67, the post-processing device data input / output section 221 receives the signal processing result processed by the server 200 and ends the processing of this flowchart.

[0240] Fig.14 This is a flowchart showing a data processing sequence of an inline-type action sequence 1.

[0241] In step S71 , the antenna device data input / output unit 211 transmits the signal generated by the antenna device 210 to the server 200 .

[0242] In step S72 , the input / output unit 13 performs data input / output with external devices (the antenna device 210 , the post-processing device 220 ).

[0243] In step S73, the accelerator 12 performs operations dedicated to the specific processing.

[0244] In step S74, the application 1 receives the processing target data from the input / output unit 13 and transmits the calculated data to the input / output unit 13. When the accelerator 12 is temporarily unavailable when the setting of the accelerator 12 is changed, the application 1 is unloaded by the processing continuation unit 160 when switching to ACC.

[0245] In step S75 , the input / output unit 13 performs data input / output with external devices (antenna device 210 , post-processing device 220 ).

[0246] In step S76, the post-processing device data input / output section 221 receives the signal processing result processed by the server 200 and ends the processing of this flowchart.

[0247] [Processing power / power consumption and remaining capacity]

[0248] The processing capacity / power consumption and margin achieved by the accelerator state control device 100 will be described.

[0249] The ACC processing capacity / power consumption setting determination unit 120 determines the accelerator setting corresponding to the processing capacity and fluctuation time of the accelerator based on the predicted result of the business volume input from the input volume acquisition / prediction unit 110 and the assumed fluctuation range. The ACC processing capacity / power consumption setting input unit 130 receives the setting information to the accelerator 12 and the setting information to the cooling mechanism 14 from the ACC processing capacity / power consumption setting determination unit 120, and reflects the setting information to the accelerator 12 and the cooling mechanism 14, respectively. The ACC processing capacity / power consumption setting input unit 130 automatically performs the accelerator setting (circuit information / frequency / fan output, etc.) suitable for each input data volume, thereby dynamically changing the processing capacity / power consumption.

[0250] Fig.15 1 is a diagram illustrating the processing capability / power consumption and surplus achieved by the accelerator state control device 100 . Fig.15 The solid line represents the amount of input data. Fig.15 The dotted line represents the server processing power (≈ power consumption).

[0251] The ACC processing capacity / power consumption setting determination unit 120 and the ACC processing capacity / power consumption setting input unit 130 perform accelerator settings suitable for each input data volume, and dynamically change the processing capacity / power consumption. Fig.15 As shown by the arrow, the amount that can be processed by the server 200 fluctuates by changing the settings, and the power efficiency is improved.

[0252] [Hardware Configuration]

[0253] The accelerator state control system 1000, 1000A ( Figure 1 , Figure 2 ) of the accelerator state control device 100 ( Figure 1 ) For example, Fig.16 The illustrated configuration is implemented by a computer 900 .

[0254] Fig.16 1 is a diagram showing a hardware configuration of an example of a computer 900 that realizes the functions of the accelerator state control device 100 .

[0255] The accelerator state control device 100 includes a CPU 901, a RAM 902, a ROM 903, a HDD 904, an accelerator 905, an input / output interface (I / F) 906, a media interface (I / F) 907, and a communication interface (I / F: Interface) 908. The accelerator 905 corresponds to Figure 1 and Figure 2 The accelerator 12 in.

[0256] The accelerator 905 is an accelerator (device) 12 ( Figure 1 , Figure 2 ). It should be noted that, as the accelerator 905, a type (bypass type) that returns the execution result to the CPU 901 or RAM 902 after executing the processing from the CPU 901 or RAM 902 may also be used. On the other hand, as the accelerator 905, a type (inline type) that enters between the communication I / F 908 and the CPU 901 or between the communication I / F 908 and the RAM 902 and performs processing may also be used.

[0257] The accelerator 905 is connected to an external device 915 via a communication I / F 908. The input / output I / F 906 is connected to an input / output device 916. The media I / F 907 reads and writes data from a recording medium 917.

[0258] The CPU 901 operates based on the program stored in the ROM 903 or the HDD 904, and performs operations by executing a program (also referred to as an application program or its abbreviation) loaded into the RAM 902. Figure 1 and Figure 2 The program can be distributed via a communication line or recorded in a recording medium 917 such as a CD-ROM.

[0259] The ROM 903 stores a boot program executed by the CPU 901 when the computer 900 is activated, a program depending on the hardware of the computer 900 , and the like.

[0260] The CPU 901 controls an input / output device 916 composed of an input unit such as a mouse and a keyboard, and an output unit such as a display and a printer, via an input / output I / F 906. The CPU 901 obtains data from the input / output device 916 via the input / output I / F 906, and outputs generated data to the input / output device 916. It should be noted that a GPU (Graphics Processing Unit: graphics processor) or the like may be used as a processor together with the CPU 901.

[0261] HDD 904 stores programs executed by CPU 901 and data used by the programs, etc. Communication I / F 908 receives data from other devices via a communication network (eg, NW (Network)) and outputs it to CPU 901 , and also transmits data generated by CPU 901 to other devices via the communication network.

[0262] The media I / F 907 reads the program or data stored in the recording medium 917 and outputs it to the CPU 901 via the RAM 902. The CPU 901 loads the target processing program from the recording medium 917 to the RAM 902 via the media I / F 907, and executes the loaded program. The recording medium 917 is an optical recording medium such as a DVD (Digital Versatile Disc) or a PD (Phasechange rewritable disk), an optical magnetic recording medium such as an MO (Magneto Optical disk), a magnetic recording medium, a conductive memory tape medium, or a semiconductor memory.

[0263] For example, in the computer 900 as the accelerator state control device 100 ( Figure 1 ) functions, the CPU 901 of the computer 900 implements the functions of the accelerator state control device 100 by executing the program loaded on the RAM 902. In addition, the HDD 904 stores the data in the RAM 902. The CPU 901 reads the program involved in the target processing from the recording medium 917 and executes it. In addition, the CPU 901 can also read the program involved in the target processing from other devices via the communication network.

[0264] It should be noted that in Figure 2 When the controller function unit shown in FIG. 1 is provided outside the server 200, the accelerator state control device 100A is also similarly controlled by Fig.16 The configuration shown is implemented by a computer 900.

[0265] [Effect]

[0266] As described above, the accelerator state control device 100 controls the state of the accelerator when offloading specific processing of the application 1 to the accelerator 12 for calculation processing. The accelerator state control device 100 includes: an input amount acquisition / prediction unit 110, which predicts the processing amount offloaded to the accelerator 12 and outputs the prediction result as the business volume and its fluctuation range; a processing capacity setting recording unit 150, which saves information on the accelerator type and model and setting information corresponding to the processing performance as overview information, and extracts and responds from the overview information according to an inquiry; an ACC processing capacity / power consumption setting judgment unit 120, which judges the setting information of the processing capacity and fluctuation time of the accelerator based on the business volume and fluctuation range output from the input amount acquisition / prediction unit 110 and the overview information read from the processing capacity setting recording unit 150; and an ACC processing capacity / power consumption setting input unit 130, which reflects the setting information to the accelerator 12 based on the setting information to the accelerator 12 judged by the ACC processing capacity / power consumption setting judgment unit 120.

[0267] As a result, the accelerator settings (circuit information / frequency / fan output, etc.) suitable for each input data volume are automatically performed, thereby dynamically changing the processing capacity and power consumption, and it is possible to achieve high power efficiency of various accelerators while ensuring responsiveness according to the fluctuating input data volume. In this way, it is possible to take into account both <Requirement 1: Power efficiency> and <Requirement 2: Responsiveness>.

[0268] In the accelerator state control device 100, 100A ( Figure 1 , Figure 2 ) is provided with an ACC switching processing continuation unit 160, which temporarily continues the processing in the CPU 11 or other accelerators when the calculation function of the accelerator 12 is temporarily stopped due to the input of setting information performed by the ACC processing capacity / power consumption setting input unit 130.

[0269] Thus, when the calculation is stopped when the accelerator is put into operation, the calculation can be continued by the CPU 11 and other accelerators, thereby maintaining the usability.

[0270] In the accelerator state control device 100, 100A ( Figure 1 , Figure 2 ), the accelerator 12 has an FPGA, and the accelerator state control device 100, 100A has an ACC circuit information recording unit 140 according to processing capacity, which stores FPGA circuit information and FPGA category information corresponding to the processing performance for each FPGA category, and responds to the FPGA circuit information and FPGA category information according to the query. The ACC circuit information recording unit 140 according to processing capacity responds to the ACC processing capacity / power consumption setting judgment unit 120 via the ACC information / processing capacity setting recording unit 150 or directly. The ACC processing capacity / power consumption setting judgment unit 120 determines the accelerator setting information corresponding to the processing capacity and fluctuation time of the accelerator based on the FPGA circuit information and FPGA category information from the ACC circuit information recording unit 140 according to processing capacity.

[0271] Thus, the ACC circuit information recording unit 140 records and manages the power saving settings for each accelerator type. The ACC processing capacity / power consumption setting determination unit 120 can respond to various accelerators by selecting a processing method for each ACC information (<Requirement 3: Response to various accelerators>). For example, in the case of FPGA, it is circuit selection + frequency setting, and in the case of ASIC, it is frequency setting.

[0272] In the accelerator state control device 100, 100A ( Figure 1 , Figure 2 ), the accelerator 12 has an FPGA and a GPU, and as for the ACC processing capability / power consumption setting input unit 130, the accelerator generally reflects the setting information by frequency change and / or power off, and reflects the setting information by circuit rewriting in the case of the FPGA, and reflects the setting information by sleep in the case of the GPU.

[0273] Therefore, when determining the power saving setting, by determining the parameters that can be set for each accelerator installed, it is possible to cope with multiple accelerators (<Requirement 3: Coping with Multiple Accelerators>). For example, in the case of FPGA, it is circuit rewriting, in the case of GPU, it is sleep, and as a general method, frequency change and power off are used.

[0274] Accelerator state control system 1000, 1000A ( Figure 1 , Figure 2 ) comprises: an accelerator state control device 100, 100A ( Figure 1 , Figure 2 ), when the specific processing of the application 1 is offloaded to the accelerator 12 for computing processing, the state of the accelerator is controlled; and the cooling mechanism 14 is used to cool the computing device including the accelerator. The accelerator state control system 1000, 1000A comprises: an input amount acquisition / prediction unit 110, which predicts the processing amount offloaded to the accelerator 12 and outputs the prediction result as the business volume and its fluctuation range; a processing capacity setting recording unit 150, which saves the information of the accelerator type and model and the setting information corresponding to the processing performance as overview information, and extracts and responds from the overview information according to the query; an ACC processing capacity / power consumption setting judgment unit 120, which judges the setting information of the processing capacity and fluctuation time of the accelerator based on the business volume and fluctuation range output from the input amount acquisition / prediction unit 110 and the overview information read from the processing capacity setting recording unit 150; and an ACC processing capacity / power consumption setting input unit 130, which reflects the setting information to the accelerator 12 and the cooling mechanism 14 based on the setting information to the accelerator 12 and the cooling mechanism 14 judged by the ACC processing capacity / power consumption setting judgment unit 120.

[0275] As a result, it is possible to achieve high power efficiency (<Requirement 1: Power Efficiency>) for various accelerators while ensuring responsiveness (<Requirement 2: Responsiveness>) according to the fluctuating amount of input data. In addition, when determining the power saving setting, by determining the parameters that can be set for each accelerator installed, it is possible to cope with multiple accelerators (<Requirement 3: Coping with Multiple Accelerators>). For example, in the case of FPGA, it is circuit rewriting, and in the case of GPU, it is sleep. As a general method, frequency change and power off are used. In addition, for the cooling mechanism 14, the output corresponding to each accelerator and the workload is set.

[0276] In addition, in each process described in the above-mentioned embodiments and modified examples, all or part of the processes described as automatic execution may be manually executed, or all or part of the processes described as manual execution may be automatically executed by a known method. In addition, the processing process, control process, specific name, and information including various data and parameters shown in the above-mentioned documents and drawings may be changed arbitrarily except for the cases specifically recorded.

[0277] In addition, the components of each device shown in the figure are conceptual functions and do not necessarily need to be physically configured as shown in the figure. That is, the specific method of distributing and integrating each device is not limited to the method shown in the figure, and all or part of them can be functionally or physically distributed and integrated in arbitrary units according to various loads, usage conditions, etc.

[0278] In addition, the above-mentioned structures, functions, processing units, processing methods, etc. can also be implemented by hardware, such as designing a part or all of them with integrated circuits. In addition, the above-mentioned structures, functions, etc. can also be implemented by software for a processor to interpret and execute programs that implement each function. Information such as programs, tables, files, etc. that implement each function can be stored in a recording device such as a memory, a hard disk, an SSD (Solid State Drive), or an IC (Integrated Circuit) card, an SD (Secure Digital) card, an optical disk, etc., or a recording medium such as an optical disk.

[0279] Description of Reference Numerals

[0280] 1: Application program (APL); 10: Hardware; 11: CPU; 12: Accelerator; 12a: Accelerator operation circuit / program; 13: Input / output unit; 14: Cooling mechanism; 20: Software; 100, 100A: Accelerator state control device; 110: Input quantity acquisition / prediction unit (prediction unit, prediction process); 120: ACC processing capacity / power consumption setting judgment unit (judgment unit, judgment process); 130: ACC processing capacity / power consumption setting input unit (setting input unit, setting input process); 140: ACC circuit information recording unit according to processing capacity; 150: ACC information / processing capacity setting recording unit (processing capacity setting recording unit, processing capacity setting recording process); 160: ACC switching processing continuation unit (processing continuation unit); 170: Overview information; 200: Server (accelerator-mounted server); 210: Antenna device; 220: Post-processing device; 1000, 1000A: Accelerator state control system.

Claims

1. An accelerator state control device, which controls the state of an accelerator when offloading specific processing of an application to an accelerator for computing processing, characterized in that: have: A prediction unit, which predicts the processing volume offloaded to the accelerator and outputs the prediction result as the business volume and its fluctuation range; a processing capability setting recording unit that stores information on accelerator types and models and setting information corresponding to processing performance as summary information, and retrieves and responds to inquiries from the summary information; a determination unit that determines the setting information of the processing capacity and fluctuation time of the accelerator based on the traffic volume and fluctuation range thereof outputted from the prediction unit and the overview information read out from the processing capacity setting recording unit; as well as The setting input unit reflects the setting information to the accelerator based on the setting information to the accelerator determined by the determination unit.

2. The accelerator state control device according to claim 1, characterized in that: A processing continuing unit is provided for temporarily continuing the processing in a central processing unit CPU or another accelerator when the calculation function of the accelerator is temporarily stopped due to the input of the setting information by the setting input unit.

3. The accelerator state control device according to claim 1, characterized in that: The accelerator has a field programmable gate array FPGA, The accelerator state control device includes a circuit information recording unit, which stores FPGA circuit information and FPGA category information corresponding to processing performance for each FPGA category, and responds to the FPGA circuit information and FPGA category information according to the query. The circuit information recording unit responds to the determination unit via the processing capacity setting recording unit or directly. The determination unit determines setting information of the processing capability and fluctuation time of the accelerator based on the FPGA circuit information and the information of the FPGA type from the circuit information recording unit.

4. The accelerator state control device according to claim 1, characterized in that: The accelerator has a field programmable gate array FPGA and a graphics processor GPU. As for the setting input unit, The accelerator generally reflects the setting information by frequency change and / or power off, And in the case of the FPGA, the setting information is reflected by circuit rewriting, and in the case of the GPU, the setting information is reflected by sleep.

5. An accelerator state control system, comprising: an accelerator state control device for controlling the state of the accelerator when offloading specific processing of an application to an accelerator for computing processing; and a cooling mechanism for cooling the computing device including the accelerator, wherein the accelerator state control system is characterized in that it comprises: A prediction unit, which predicts the processing volume offloaded to the accelerator and outputs the prediction result as the business volume and its fluctuation range; a processing capacity setting recording unit that stores information on the type and model of the accelerator, setting information corresponding to the processing performance, and setting information of the cooling mechanism as a list of information, and retrieves and responds to inquiries from the list of information; a determination unit that determines setting information of the processing capacity and fluctuation time of the accelerator based on the traffic volume and fluctuation range outputted from the prediction unit and the overview information read out from the processing capacity setting recording unit; as well as The setting input unit reflects the setting information to the accelerator and the cooling mechanism based on the setting information to the accelerator and the cooling mechanism determined by the determination unit.

6. An accelerator state control method, which is an accelerator state control method of an accelerator state control device, wherein the accelerator state control device controls the state of the accelerator when offloading specific processing of an application to an accelerator for computing processing, wherein the accelerator state control method is characterized in that: The accelerator state control device performs the following steps: The step of predicting the processing volume offloaded to the accelerator and outputting the prediction result as the business volume and its fluctuation range; The step of storing information on the type and model of the accelerator and setting information corresponding to the processing performance as summary information, and taking out and responding to the query from the summary information; The step of determining the processing capacity of the accelerator and setting information of the fluctuation time based on the business volume, the fluctuation amplitude and the overview information; as well as A step of reflecting the setting information to the accelerator based on the setting information to the accelerator.

7. An accelerator state control method, which is an accelerator state control method of an accelerator state control system, the accelerator state control system comprising: an accelerator state control device, which controls the state of the accelerator when unloading specific processing of an application to the accelerator for computing processing; and a cooling mechanism, which cools the computing device including the accelerator, wherein the accelerator state control method is characterized in that: The accelerator state control device performs the following steps: The step of predicting the processing volume offloaded to the accelerator and outputting the prediction result as the business volume and its fluctuation range; The step of storing information on the type and model of the accelerator, setting information corresponding to the processing performance, and setting information of the cooling mechanism as a list of information, and taking out and responding to the query from the list of information; The step of determining the processing capacity of the accelerator and setting information of the fluctuation time based on the business volume, the fluctuation amplitude and the overview information; as well as A step of reflecting the setting information to the accelerator and the cooling mechanism based on the setting information to the accelerator and the cooling mechanism.

8. A program for causing a computer to execute the following process as an accelerator state control device for controlling the state of an accelerator when offloading specific processing of an application to an accelerator for computing processing: A prediction process, predicting the processing volume offloaded to the accelerator, and outputting the prediction result as the business volume and its fluctuation range; The processing capability setting recording process saves the information of the accelerator type and model and the setting information corresponding to the processing performance as summary information, and retrieves and responds to the query from the summary information; A determination process, based on the business volume and fluctuation range output from the prediction process and the overview information read from the processing capacity setting recording process, determines the setting information of the processing capacity and fluctuation time of the accelerator; as well as The setting input process reflects the setting information to the accelerator based on the setting information to the accelerator determined in the determination process.

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