GaN integrated power chip throw load test system and method

Abstract

The invention relates to the technical field of power electronics, in particular to a load throwing test system and method for a GaN integrated power chip, and the system comprises a test module which carries out the electrical characteristic measurement of the GaN integrated power chip; the stress module is used for applying stress and simulating a working environment and a stress condition of the GaN integrated power chip under an actual working condition; the power supply module is used for supplying power to the double-pulse dynamic on-resistance testing device by being connected with the double-pulse dynamic on-resistance testing device; and the control module is connected with the double-pulse dynamic on-resistance testing device to provide double-pulse signals for the double-pulse dynamic on-resistance testing device. And the oscilloscope module is used for monitoring the electrical characteristics of the GaN integrated power chip. Stress is applied to the GaN integrated power chip through the stress module and the power module. Therefore, the performance of the GaN integrated power chip in different working modes is detected, and the influence of internal crosstalk of the GaN integrated power chip on the electrical performance is explored.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and more specifically, to a GaN integrated power chip load dump testing system and method. Background Art

[0002] With the increasing demand for high-efficiency power electronic devices in fields such as electric vehicles (EVs) and hybrid electric vehicles (HEVs), gallium nitride (GaN) integrated power chips have become important devices in high-power and high-frequency applications due to their excellent switching characteristics, low on-resistance and high-frequency response. However, GaN integrated power chips often face some extreme working conditions in actual applications, such as load disconnection, voltage transients and internal crosstalk, which may affect their electrical performance and reliability, especially in complex environments such as automobiles. At present, the test methods and evaluation technologies for GaN integrated power chips under load dump conditions in automotive applications are still relatively limited. Traditional test methods cannot fully simulate the performance of chips under stress applied in actual working conditions, affecting the test results.

[0003] The prior art discloses a GaN-based semiconductor laser chip detection device and method, the device includes: a chip loading module, a power module, a microscopic imaging module and a laser marking module; the power module applies a certain current to the chip to be detected so that the chip to be detected emits two beams of fluorescence from the p-face and the front cavity surface respectively, and the microscopic imaging module receives the two beams of fluorescence to perform fluorescence imaging on the p-face and the front cavity surface of the chip to be detected, and judges whether there is a failure area in the active area of ​​the chip to be detected and whether there is a catastrophic optical damage point on the front cavity surface, and finally the laser marking module is used to mark the p-face directly above the failure area of ​​the active area of ​​the chip to be detected for subsequent processing. This test method still cannot fully simulate the performance of the chip under stress under actual working conditions, which affects the test effect. Summary of the invention

[0004] The purpose of the present invention is to disclose a GaN integrated power chip load dump test system and method with higher accuracy.

[0005] In order to achieve the above object, the present invention provides a GaN integrated power chip load dump test system, including: a test module, a control module, a stress module, a power module, and an oscilloscope module;

[0006] Test module: measure the electrical characteristics of GaN integrated power chips;

[0007] Stress module: connected with the test module to apply stress to the GaN integrated power chip, simulating the working environment and stress conditions of the GaN integrated power chip under actual working conditions;

[0008] Power supply module: including high voltage power supply and low voltage power supply, which is connected to the test module to provide power for it;

[0009] Control module: Provides a double pulse signal to the test module by connecting it;

[0010] Oscilloscope module: monitors the electrical characteristics of GaN integrated power chips by connecting to the test module.

[0011] Furthermore, the test module includes: a power device analyzer, a semiconductor characteristic analyzer and a double-pulse dynamic on-resistance test device.

[0012] Further, the stress module is a load dump device.

[0013] Furthermore, the control module is an FPGA microcontroller, and the FPGA microcontroller is connected to a double-pulse dynamic on-resistance test device.

[0014] In addition, the present invention also provides a test method for a GaN integrated power chip load dump test system, comprising:

[0015] The GaN integrated power chip is measured by the test module to obtain the initial electrical characteristic parameters of the GaN integrated power chip, and the measurement data waveform is obtained by the oscilloscope module;

[0016] Stress is applied to the GaN integrated power chip through the stress module and the power module, and the electrical characteristic parameters under stress are obtained through the test module;

[0017] The reliability results of the GaN integrated power chip are obtained by visually comparing and analyzing the measured data waveform, the initial electrical characteristic parameters obtained by the test module, and the electrical characteristic parameters under pressure.

[0018] Furthermore, the initial electrical characteristic parameters of the GaN integrated power chip obtained by measuring the GaN integrated power chip through the test module include:

[0019] Set the measurement parameters of the power device analyzer and semiconductor characteristic analyzer according to the data of GaN integrated power chip;

[0020] The six pins sequentially led out of the GaN integrated power chip are used as the gate test points, source test points and drain test points of the upper and lower GaN integrated power chips respectively; the gate test points, source test points and drain test points of the upper and lower GaN integrated power chips are connected to the power device analyzer and the semiconductor characteristic analyzer in the test module, and the initial electrical characteristics of the upper and lower GaN devices are measured respectively, so as to obtain the initial electrical characteristic parameters of the GaN integrated power chip.

[0021] Furthermore, the initial electrical characteristic parameters include at least one of the following: threshold voltage, drain current, and gate current.

[0022] Furthermore, the GaN integrated power chip is measured by the test module and the measurement data waveform is obtained by the oscilloscope module, including:

[0023] The dual-pulse dynamic on-resistance test device in the test module is connected to the GaN integrated power chip to obtain the voltage signal Vm between the drain and source of the GaN integrated power chip and its drain current signal ID, and the measurement data waveform is obtained through the oscilloscope module according to the voltage signal Vm between the drain and source of the GaN integrated power chip and its drain current signal ID.

[0024] Furthermore, stress is applied to the GaN integrated power chip through the stress module and the power module, and the electrical characteristic parameters under stress are obtained through the test module, including: using a low-voltage power supply in the power module to connect to the gate of the upper GaN integrated power chip, so that the GaN integrated power chip is respectively in a floating state, a closed state, and a semi-open state, and stress is applied by setting different load dumping voltage levels on the stress module, and the electrical characteristic parameters of the GaN integrated power chip under different stresses in the floating state, the closed state, and the semi-open state are obtained through the test module, and the electrical characteristic parameters of the GaN integrated power chip under different stresses in the floating state, the closed state, and the semi-open state are used as the electrical characteristic parameters under pressure.

[0025] Furthermore, the data stored in the oscilloscope module and the test module are transmitted to the host computer, the dynamic on-resistance of the GaN integrated power chip is extracted, the initial electrical characteristic parameters, electrical characteristic parameters under pressure and dynamic on-resistance value of the GaN integrated power chip are visualized, and the impact of crosstalk on the GaN integrated power chip is observed.

[0026] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0027] The present invention measures the GaN integrated power chip through a test module to obtain the initial electrical characteristic parameters of the GaN integrated power chip, and obtains the measurement data waveform through an oscilloscope module; then applies stress to the GaN integrated power chip through a stress module and a power module, and obtains the electrical characteristic parameters under pressure through a test module; and obtains the reliability result of the GaN integrated power chip through a visual comparative analysis of the measurement data waveform, the initial electrical characteristic parameters obtained by the test module, and the electrical characteristic parameters under pressure. Thus, the performance of the GaN integrated power chip under different working modes is detected, and the influence of the internal crosstalk of the GaN integrated power chip on the electrical performance is explored. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A GaN integrated power chip load dump test system as described in Example 1;

[0029] Figure 2 This is a flow chart of a GaN integrated power chip load dump test method described in Example 2; DETAILED DESCRIPTION

[0030] The drawings are for illustrative purposes only and should not be construed as limiting the present patent;

[0031] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0032] Embodiment 1:

[0033] This embodiment provides Figure 1 A GaN integrated power chip load dump test system is shown, comprising: a test module, a control module, a stress module, a power module, and an oscilloscope module;

[0034] Test module: measure the electrical characteristics of GaN integrated power chips;

[0035] Stress module: connected with the test module to apply stress to the GaN integrated power chip, simulating the working environment and stress conditions of the GaN integrated power chip under actual working conditions;

[0036] Power supply module: including high voltage power supply and low voltage power supply, which is connected to the test module to provide power for it;

[0037] Control module: Provides a double pulse signal to the test module by connecting it;

[0038] Oscilloscope module: monitors the electrical characteristics of GaN integrated power chips by connecting to the test module.

[0039] In this embodiment, the GaN integrated power chip is measured by the test module to obtain the initial electrical characteristic parameters of the GaN integrated power chip, and the measurement data waveform is obtained by the oscilloscope module; then the stress is applied to the GaN integrated power chip by the stress module and the power module, and the electrical characteristic parameters under pressure are obtained by the test module; the reliability results of the GaN integrated power chip are obtained by visually comparing and analyzing the measurement data waveform, the initial electrical characteristic parameters obtained by the test module, and the electrical characteristic parameters under pressure. In this way, the performance of the GaN integrated power chip in different working modes is detected, and the influence of the internal crosstalk of the GaN integrated power chip on the electrical performance is explored.

[0040] Embodiment 2:

[0041] This embodiment further discloses on the basis of the first embodiment:

[0042] The test module includes: a power device analyzer, a semiconductor characteristic analyzer and a double-pulse dynamic on-resistance tester.

[0043] Further, it includes: the stress module is a load dumping device.

[0044] Furthermore, it includes: the control module is an FPGA microcontroller, and the FPGA microcontroller is connected to the double-pulse dynamic on-resistance test device.

[0045] In this embodiment, the GaN integrated power chip is measured by the test module to obtain the initial electrical characteristic parameters of the GaN integrated power chip, and the measurement data waveform is obtained by the oscilloscope module; then the stress is applied to the GaN integrated power chip by the stress module and the power module, and the electrical characteristic parameters under pressure are obtained by the test module; the reliability results of the GaN integrated power chip are obtained by visually comparing and analyzing the measurement data waveform, the initial electrical characteristic parameters obtained by the test module, and the electrical characteristic parameters under pressure. In this way, the performance of the GaN integrated power chip in different working modes is detected, and the influence of the internal crosstalk of the GaN integrated power chip on the electrical performance is explored.

[0046] Embodiment three:

[0047] This embodiment provides Figure 2 A test method for a GaN integrated power chip load dump test system is shown, comprising:

[0048] S1: measuring the GaN integrated power chip through the test module to obtain the initial electrical characteristic parameters of the GaN integrated power chip, and obtaining the measurement data waveform through the oscilloscope module;

[0049] S2: applying stress to the GaN integrated power chip through the stress module and the power module, and obtaining electrical characteristic parameters under stress through the test module;

[0050] S3: The reliability results of the GaN integrated power chip are obtained by visually comparing and analyzing the measured data waveform, the initial electrical characteristic parameters obtained by the test module, and the electrical characteristic parameters under pressure.

[0051] In this embodiment, the GaN integrated power chip is measured by the test module to obtain the initial electrical characteristic parameters of the GaN integrated power chip, and the measurement data waveform is obtained by the oscilloscope module; then the stress is applied to the GaN integrated power chip by the stress module and the power module, and the electrical characteristic parameters under pressure are obtained by the test module; the reliability results of the GaN integrated power chip are obtained by visually comparing and analyzing the measurement data waveform, the initial electrical characteristic parameters obtained by the test module, and the electrical characteristic parameters under pressure. In this way, the performance of the GaN integrated power chip in different working modes is detected, and the influence of the internal crosstalk of the GaN integrated power chip on the electrical performance is explored.

[0052] Embodiment 4:

[0053] This embodiment further discloses on the basis of the third embodiment:

[0054] Furthermore, the initial electrical characteristic parameters of the GaN integrated power chip obtained by measuring the GaN integrated power chip through the test module include:

[0055] Set the measurement parameters of the power device analyzer and semiconductor characteristic analyzer according to the data of GaN integrated power chip;

[0056] The six pins sequentially led out of the GaN integrated power chip are used as the gate test points, source test points and drain test points of the upper and lower GaN integrated power chips respectively; the gate test points, source test points and drain test points of the upper and lower GaN integrated power chips are connected to the power device analyzer and the semiconductor characteristic analyzer in the test module, and the initial electrical characteristics of the upper and lower GaN devices are measured respectively, so as to obtain the initial electrical characteristic parameters of the GaN integrated power chip.

[0057] Furthermore, the initial electrical characteristic parameters include at least one of the following: threshold voltage, drain current, and gate current.

[0058] Furthermore, the GaN integrated power chip is measured by the test module and the measurement data waveform is obtained by the oscilloscope module, including:

[0059] The dual-pulse dynamic on-resistance test device in the test module is connected to the GaN integrated power chip to obtain the voltage signal Vm between the drain and source of the GaN integrated power chip and its drain current signal ID, and the measurement data waveform is obtained through the oscilloscope module according to the voltage signal Vm between the drain and source of the GaN integrated power chip and its drain current signal ID.

[0060] Furthermore, stress is applied to the GaN integrated power chip through the stress module and the power module, and the electrical characteristic parameters under stress are obtained through the test module, including: using a low-voltage power supply in the power module to connect to the gate of the upper GaN integrated power chip, so that the GaN integrated power chip is respectively in a floating state, a closed state, and a semi-open state, and stress is applied by setting different load dumping voltage levels on the stress module, and the electrical characteristic parameters of the GaN integrated power chip under different stresses in the floating state, the closed state, and the semi-open state are obtained through the test module, and the electrical characteristic parameters of the GaN integrated power chip under different stresses in the floating state, the closed state, and the semi-open state are used as the electrical characteristic parameters under pressure.

[0061] The floating state means that the device is not connected to an external power supply so that its gate remains in a floating state; the off state means that the device is connected to an external low-voltage power supply and outputs a voltage of 0V to keep its gate in an off state; the semi-open state means that the device is connected to an external low-voltage power supply and outputs a voltage between 0-6V to keep its gate in an incompletely open state; the open state means that the device is connected to an external low-voltage power supply and outputs a voltage of 6V to keep its gate in a fully open state; under this condition, different load dumping voltage levels are set on the 3C-Test LDS200N load dumping device to simulate actual working conditions, so that the crosstalk effect of different load dumping voltage levels of GaN integrated power chips in different gate states on the electrical characteristics and dynamic on-resistance of GaN integrated power chips (GaN integrated power chips) can be explored.

[0062] Floating mode: When the gate of the upper GaN integrated power chip does not use an external low-voltage power supply and the gate of the lower GaN integrated power chip remains floating, the drain and source of the upper GaN integrated power chip in the GaN integrated power chip are connected to the 3C-Test LDS 200N load dump device through external test hooks. After the connection is completed, load dump stresses of different voltage levels are applied to the upper GaN integrated power chip. After the stress is completed, the electrical characteristics of the upper and lower GaN integrated power chips in the GaN integrated power chip are immediately tested using the Keysight B1506A power device analyzer, 4200-SCS semiconductor characteristic analyzer and double-pulse dynamic on-resistance test device.

[0063] Shutdown mode: When the gate of the upper GaN integrated power chip uses an external low-voltage power supply and the gate of the lower GaN integrated power chip remains floating, the low-voltage power supply outputs a 0V shutdown voltage to the gate of the upper GaN integrated power chip. At the same time, the drain and source of the upper GaN integrated power chip in the GaN integrated power chip are connected to the 3C-Test LDS200N load dump device through external test hooks. After the connection is completed, different levels of voltage dump load stress are applied to the upper GaN integrated power chip. After the stress is completed, the electrical characteristics of the upper and lower GaN integrated power chips in the GaN integrated power chip are immediately tested using the Keysight B1506A power device analyzer, 4200-SCS semiconductor characteristic analyzer and double pulse dynamic on-resistance test device.

[0064] Half-open mode: When the gate of the upper GaN integrated power chip uses an external low-voltage power supply and the gate of the lower GaN integrated power chip remains floating, the low-voltage power supply outputs a 0-6V voltage to the gate of the upper GaN integrated power chip. At the same time, the drain and source of the upper GaN integrated power chip in the GaN integrated power chip are connected to the 3C-Test LDS200N load dump device through external test hooks. After the connection is completed, different levels of voltage dump load stress are applied to the upper GaN integrated power chip. After the stress is completed, the electrical characteristics of the upper and lower GaN integrated power chips in the GaN integrated power chip are immediately tested using the Keysight B1506A power device analyzer, 4200-SCS semiconductor characteristic analyzer and double pulse dynamic on-resistance test device.

[0065] Turn-on mode: When the gate of the upper GaN integrated power chip uses an external low-voltage power supply and the gate of the lower GaN integrated power chip remains floating, the low-voltage power supply outputs a 6V voltage to the gate of the upper GaN integrated power chip. At the same time, the drain and source of the upper GaN integrated power chip in the GaN integrated power chip are connected to the 3C-Test LDS200N load dump device through external test hooks. After the connection is completed, different levels of voltage dump load stress are applied to the upper GaN integrated power chip. After the stress is completed, the electrical characteristics of the upper and lower GaN integrated power chips in the GaN integrated power chip are immediately tested using the Keysight B1506A power device analyzer, 4200-SCS semiconductor characteristic analyzer and double pulse dynamic on-resistance test device.

[0066] Furthermore, the data stored in the oscilloscope module and the test module are transmitted to the host computer, the dynamic on-resistance of the GaN integrated power chip is extracted, the initial electrical characteristic parameters, electrical characteristic parameters under pressure and dynamic on-resistance value of the GaN integrated power chip are visualized, and the impact of crosstalk on the GaN integrated power chip is observed.

[0067] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A GaN integrated power chip load dump test system, characterized in that: include: Test module, control module, stress module, power module, oscilloscope module; Test module: measure the electrical characteristics of GaN integrated power chips; Stress module: connected with the test module to apply stress to the GaN integrated power chip, simulating the working environment and stress conditions of the GaN integrated power chip under actual working conditions; Power supply module: including high voltage power supply and low voltage power supply, which is connected to the test module to provide power for it; Control module: Provides a double pulse signal to the test module by connecting it; Oscilloscope module: monitors the electrical characteristics of GaN integrated power chips by connecting to the test module.

2. A GaN integrated power chip load dump test method according to claim 1, characterized in that: The test module includes: a power device analyzer, a semiconductor characteristic analyzer and a double-pulse dynamic on-resistance tester.

3. A GaN integrated power chip load dump test method according to claim 2, characterized in that: The stress module is a load dump device.

4. A GaN integrated power chip load dump test method according to claim 3, characterized in that: The control module is an FPGA microcontroller, and the FPGA microcontroller is connected to a double-pulse dynamic on-resistance test device.

5. A test method for a GaN integrated power chip load dump test system according to claim 4, characterized in that: include: The GaN integrated power chip is measured by the test module to obtain the initial electrical characteristic parameters of the GaN integrated power chip, and the measurement data waveform is obtained by the oscilloscope module; Stress is applied to the GaN integrated power chip through the stress module and the power module, and the electrical characteristic parameters under stress are obtained through the test module; The reliability results of the GaN integrated power chip are obtained by visually comparing and analyzing the measured data waveform, the initial electrical characteristic parameters obtained by the test module, and the electrical characteristic parameters under pressure.

6. The test method of a GaN integrated power chip load dump test system according to claim 5, characterized in that: The initial electrical characteristic parameters of the GaN integrated power chip obtained by measuring the GaN integrated power chip through the test module include: Set the measurement parameters of the power device analyzer and semiconductor characteristic analyzer according to the data of GaN integrated power chip; The six pins sequentially led out of the GaN integrated power chip are used as the gate test points, source test points and drain test points of the upper and lower GaN integrated power chips respectively; the gate test points, source test points and drain test points of the upper and lower GaN integrated power chips are connected to the power device analyzer and the semiconductor characteristic analyzer in the test module, and the initial electrical characteristics of the upper and lower GaN devices are measured respectively, so as to obtain the initial electrical characteristic parameters of the GaN integrated power chip.

7. The test method of a GaN integrated power chip load dump test system according to claim 6, characterized in that: The initial electrical characteristic parameters include at least one of the following: threshold voltage, drain current, and gate current.

8. The test method of a GaN integrated power chip load dump test system according to claim 5, characterized in that: The GaN integrated power chip is measured through the test module and the measurement data waveform obtained through the oscilloscope module includes: The dual-pulse dynamic on-resistance test device in the test module is connected to the GaN integrated power chip to obtain the voltage signal Vm between the drain and source of the GaN integrated power chip and its drain current signal ID, and the measurement data waveform is obtained through the oscilloscope module according to the voltage signal Vm between the drain and source of the GaN integrated power chip and its drain current signal ID.

9. The test method of a GaN integrated power chip load dump test system according to claim 5, characterized in that: Applying stress to the GaN integrated power chip through the stress module and the power module, and obtaining the electrical characteristic parameters under stress through the test module include: using the low-voltage power supply in the power module to connect with the gate of the upper GaN integrated power chip, so that the GaN integrated power chip is in a floating state, a closed state, and a semi-open state, and applying stress by setting different load dumping voltage levels on the stress module, and obtaining the electrical characteristic parameters of the GaN integrated power chip in different stresses in the floating state, the closed state, and the semi-open state through the test module, and using the electrical characteristic parameters of the GaN integrated power chip in different stresses in the floating state, the closed state, and the semi-open state as the electrical characteristic parameters under stress.

10. The test method of a GaN integrated power chip load dump test system according to claim 5, characterized in that: The data stored in the oscilloscope module and the test module are transmitted to the host computer, the dynamic on-resistance of the GaN integrated power chip is extracted, the initial electrical characteristic parameters, electrical characteristic parameters under pressure and dynamic on-resistance value of the GaN integrated power chip are visualized, and the impact of crosstalk on the GaN integrated power chip is observed.

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