Resource fool-proof method and device for chip testing and chip testing system

Abstract

The invention discloses a resource fool-proof method and device for chip testing and a chip testing system, and the method comprises the steps: numbering testing stations in a testing group, and sequentially setting asymmetric resources corresponding to the testing stations, thereby enabling a testing machine to test a to-be-tested chip according to the asymmetric resources, and determining whether a connection error exists or not. Correspondingly, all the chips to be tested in the test group are sequentially placed on the corresponding test stations of the test board, and after the machine test resources are connected to the interfaces of the test stations, the chips to be tested are tested according to the set asymmetric resources; and if the test result of the test station is fixed and invalid, a connection error is determined, so that a worker can correct the corresponding connection error in time, a test result error caused by an operation error is avoided, and the smooth test is ensured. By utilizing the scheme of the invention, the resource fool-proof of the chip test can be simply and effectively realized, so that the accuracy of the test result is ensured, and the chip is effectively prevented from being mistakenly killed or mistakenly placed.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit automated testing, and in particular to a resource fool-proofing method and device for chip testing, and a chip testing system. Background Art

[0002] In the semiconductor chip production process, chip mass production automatic test equipment (ATE) testing is a key link to ensure chip quality. However, in actual operation, human factors, equipment errors or unstable test environment and other factors can easily lead to some test errors, such as reverse chip insertion, improper or incorrect test interface docking, etc. These errors will not only affect the accuracy of the test results, but also cause chip overkill (i.e. misjudging a good chip as bad) or misplacement, and even damage the chip or test equipment.

[0003] At present, there are some fool-proofing devices in the chip testing industry, but most of them have complex structures and inconvenient operations, such as requiring additional hardware devices or software operations. Summary of the invention

[0004] The embodiments of the present invention provide a resource fool-proofing method and device for chip testing, and a chip testing system to solve the problems of complex structure, inconvenient operation, and poor fool-proofing effect of existing fool-proofing devices.

[0005] To this end, the embodiment of the present invention provides the following technical solutions:

[0006] On the one hand, an embodiment of the present invention provides a resource error-proofing method for chip testing, the method comprising: numbering the test stations in the test group, and sequentially setting asymmetric resources corresponding to each test station, so that the test machine tests the chip to be tested according to the asymmetric resources to determine whether there is a connection error.

[0007] Optionally, sequentially setting asymmetric resources corresponding to each test station includes: allocating different test resources to each test station in a staggered manner according to the order of the test resources and the numbers of the test stations.

[0008] Optionally, sequentially allocating different test resources to each test station in a staggered manner includes: sequentially allocating the same number of channels to each test station in a staggered manner.

[0009] Optionally, the sequentially staggering and allocating different test resources to each test station includes: sequentially allocating a set number of channels after staggering one or more channels to each test station.

[0010] Optionally, sequentially setting asymmetric resources corresponding to each test station includes: designing different peripheral circuits for different test stations.

[0011] Optionally, resistors with different resistance values ​​are connected in series to interfaces of the same pins of different test stations.

[0012] Optionally, according to the serial numbers of the test stations, the resistance values ​​of the resistors connected in series increase or decrease in sequence.

[0013] Optionally, the method further comprises:

[0014] After placing all the chips to be tested in the test group on the corresponding test stations of the test board in sequence and connecting the machine test resources to the interfaces of each test station, testing the chips to be tested according to the set asymmetric resources;

[0015] If the test results of a test station are always invalid, it is determined that there is a connection error.

[0016] Optionally, the machine channel is arranged on one or more boards.

[0017] Optionally, the method further comprises: indicating the serial number of the test station where the test result is fixedly invalid.

[0018] On the other hand, an embodiment of the present invention further provides a resource foolproof device for chip testing, the device comprising: a resource allocation module, and a plurality of test stations;

[0019] The test station is used to sequentially place the chips to be tested in the test group;

[0020] The resource allocation module is used to number the test stations in the test group and sequentially set asymmetric resources corresponding to each test station, so that the test machine tests the chip to be tested according to the asymmetric resources to determine whether there is a connection error.

[0021] On the other hand, an embodiment of the present invention further provides a chip testing system, the system comprising: a testing machine, and the resource foolproofing device for chip testing; the testing machine comprises: a testing module and an inspection module;

[0022] The test module is used to test the chips to be tested after placing all the chips to be tested on the corresponding test stations in sequence and connecting the test lines of the test machine to the interfaces of each test station;

[0023] The checking module is used to determine that there is a connection error when the test result of a test station is fixedly invalid.

[0024] Optionally, the test machine further comprises: a display module for indicating the serial number of the test station where the test result is fixedly invalid.

[0025] On the other hand, an embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the resource fool-proofing method for chip testing are executed.

[0026] On the other hand, an embodiment of the present invention further provides a computer program product, including a computer program / instruction, which implements the steps of the resource fool-proofing method for chip testing when executed by a processor.

[0027] The chip test resource error prevention method and device, and chip test system provided by the embodiment of the present invention only need to define the hardware ATE test machine resources during hardware design, and sequentially set the asymmetric resources corresponding to each chip to be tested; perform a connection test, and determine whether there is a connection error based on the test results, thereby achieving an error prevention effect. After determining that there is a connection error, the staff can correct the corresponding connection error in time to avoid test result errors caused by operation errors, thereby ensuring the smooth progress of the test.

[0028] The solution of the present invention does not require additional hardware devices and additional software processing, has a simple structure, is easy to operate, and has a good fool-proofing effect. It can automatically locate the test station where the test interface is incorrectly docked, and then determine the chip at the test station, thereby ensuring the accuracy of the test results and effectively avoiding the misplacement or misplacing of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a flow chart of a resource fool-proofing method for chip testing provided by an embodiment of the present invention;

[0030] Figure 2 It is a schematic diagram of resource allocation method during chip testing in the prior art;

[0031] Figure 3 This is a specific example diagram of channel allocation during chip testing in the prior art;

[0032] Figure 4 is based on Figure 3 An example diagram of channel allocation when a connection error occurs is shown;

[0033] Figure 5 This is a specific example diagram of channel resource allocation using the method of the present invention;

[0034] Figure 6 is based on Figure 5 An example diagram of channel allocation when a connection error occurs is shown;

[0035] Figure 7 is another specific example diagram of channel resource allocation using the method of the present invention;

[0036] Figure 8 is based on Figure 7 An example diagram of channel allocation when a connection error occurs is shown;

[0037] Fig. 9 is another specific example diagram of setting asymmetric resources corresponding to each chip to be tested in an embodiment of the present invention;

[0038] Fig.10 is based on Fig. 9 An example diagram of an asymmetric resource when a connection error occurs;

[0039] Fig.11 It is a structural schematic diagram of a resource fool-proof device for chip testing provided by an embodiment of the present invention;

[0040] Fig.12 It is a structural schematic diagram of a chip testing system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] The chip manufacturing process goes through a variety of process steps. For example, a single-crystal silicon wafer goes through deposition / lithography / etching / implantation / interconnection process steps in a wafer factory to manufacture integrated circuits in a wafer, which includes multiple chips (dies). Wafer testing CP (Chip Probing), that is, wafer-level testing, marks good and bad dies separately and sends them to the packaging factory for good die packaging operations, that is, packaging them into chips. The chips will also undergo final product testing (Final Test, FT) and system-level testing (System Level Test, SLT) to distinguish good and bad chips (FT is code-level testing, SLT is system-level testing, which is closer to real customer applications).

[0043] Chip ATE is a device used for automated testing in chip testing. It is a device used to perform various tests on chips, such as functional testing, electrical performance testing, reliability testing, etc. It can automatically execute test procedures and make judgments and records based on test results.

[0044] Chip ATE is mainly composed of a test host, a test head, a test program, a test fixture, etc. Among them, the test head is an interface device that connects the chip and the test host. It has a built-in test board and a test channel interface, which can provide a reliable electrical connection and provide test point switching and signal processing functions; the test fixture is a device used to support and fix the chip and the test head, which can provide a stable electrical connection and mechanical support to ensure the accuracy and reliability of the test. During the test, the chip needs to be placed in the adapter, which is part of the test fixture and can ensure a stable electrical connection between the chip and the test head. Therefore, the test head is fixed to the adapter and connected to the test host to establish the entire test system.

[0045] For chip testing, batch testing is usually used, which requires a group of chips to be installed on an adapter and connected to a test head. The number of resources required for a group of chips to be tested simultaneously is the same. Moreover, corresponding resources, such as channel resources, are usually allocated to each chip in sequence.

[0046] In order to prevent some operational errors (such as wiring connection errors) that occur during the process from having adverse effects on the test results, an embodiment of the present invention provides a resource error-proofing method and device for chip testing, which numbers the chips to be tested in the test group, and sets asymmetric resources corresponding to each chip to be tested in sequence, and performs connectivity tests on the chips to be tested on the test station based on the set asymmetric resources; if the test results of a test station are fixedly invalid, it can be determined that there is a connection error.

[0047] like Figure 1 FIG. 1 is a flow chart of a resource fool-proofing method for chip testing provided by an embodiment of the present invention, comprising the following steps:

[0048] Step 101, numbering the test stations in the test group, and sequentially setting asymmetric resources corresponding to each test station, so that the test machine tests the chip to be tested according to the asymmetric resources to determine whether there is a connection error.

[0049] The asymmetric resources refer to that the resources allocated to each test station are not arranged in a regular sequence, but have certain intervals or different sequences.

[0050] In a specific implementation, the asymmetric resource may be in various specific forms, such as:

[0051] In some embodiments, different test resources may be staggered and allocated to each test station in sequence according to the sequence of the test resources and the number of the test station. For example, the same number of channels may be staggered and allocated to each test station in sequence, one or more channels may be staggered, the staggering may be in an increasing or decreasing manner, or in a disordered order, or in a staggering manner of exchanging two resources, etc.

[0052] In other embodiments, different peripheral circuits may be designed for different test stations, for example, resistors with different resistance values ​​may be connected in series to the interfaces of the same pins of different test stations. For example, the resistance values ​​of the resistors connected in series may increase or decrease in sequence according to the sequence number of the test stations.

[0053] Accordingly, when conducting the test, the following steps may also be included:

[0054] Step 102, after placing all the chips to be tested in the test group on corresponding test stations of the test board in sequence and connecting machine test resources to interfaces of each test station, the chips to be tested are tested according to the set asymmetric resources.

[0055] Step 103: If the test result of a test station is fixedly invalid, it is determined that there is a connection error.

[0056] The fixed failure means that the test results of multiple chips under test placed in the test station are all failed. This situation indicates that the connection of the test station is wrong, rather than the failure of the chip under test.

[0057] In other non-limiting embodiments, the serial number of the test station where the test result is fixed and invalid can also be indicated so that the staff can correct the corresponding connection error in time to avoid the test result error caused by the operation error.

[0058] The following example illustrates the principle of implementing fool-proofing by allocating asymmetric resources to each chip under test.

[0059] Example 1: According to the order of test resources and the number of test stations, different test resources are staggeredly allocated to each test station.

[0060] like Figure 2 As shown in the figure, the total number of channel resources of the selected machine is N, and there are m test sites, N>m, each site needs N / m ATE test machine channel resources, and m chips are tested at the same time each time, that is, there are m chips in each test group. Assume that each cable has N / m resources, and take N as an example that is divisible by m.

[0061] In the prior art, channel resources of an ATE test machine are usually allocated to each site in sequence, that is, cable 1 corresponds to site 1, cable 2 corresponds to site 2, and so on, that is, each cable corresponds to a different site.

[0062] According to the above resource allocation method, the channel (CH) resources of site1 are from channel 1 to channel N / m, the channel resources of site2 are from N / m+1 to channel 2×(N / m), the channel resources of site3 are from 2×(N / m)+1 to channel 3×(N / m), and so on.

[0063] Taking the 4-site hardware based on a certain machine as an example, a digital board has 128 channel resources. Using two digital boards, each site can be allocated 64 channel resources. According to the normal ATE test machine resource allocation, each cable has 64 channel resources, such as Figure 3 shown.

[0064] If the operator makes a mistake in cable operation, for example, cable 1 and cable 2 are plugged in reverse, that is, cable 1 should be plugged into the interface of site 1, but it is actually plugged into the interface of site 2; and cable 2 should be plugged into the interface of site 2, but it is actually plugged into the interface of site 1. Figure 4 shown.

[0065] On the machine side, since the test result is determined based on the allocation of its channel resources, the corresponding site is determined, that is, the chip on the site is determined to be good or defective based on the test result.

[0066] If the wiring is correct, follow Figure 3 The connection relationship shown in the figure can accurately match the test results corresponding to each cable to the actual chip. For example, if the test result corresponding to cable 1 is abnormal and the test result corresponding to cable 2 is normal, it is determined that the chip on site 1 is defective and the chip on site 2 is good, then the tester will transfer the chip on site 1 to the defective column.

[0067] If the connection is incorrect, follow Figure 4 In the connection relationship shown, assuming that the test result corresponding to cable 1 is abnormal and the test result corresponding to cable 2 is normal, since the test machine cannot identify the connection error, it will still determine that the chip on site 1 is invalid and the chip on site 2 is valid. According to the test result, the chip on site 1 will be removed. However, due to the connection error, cable 1 actually corresponds to the chip on site 2, and cable 2 corresponds to the chip on site 1. The truly defective chip is the chip on site 2, while the chip on site 1 is a good product.

[0068] Obviously, according to the existing resource allocation method, the failed chips on site 1 will be mixed into the good products, causing mixing and misplacement, resulting in serious quality accidents.

[0069] By using the solution of the present invention, different test resources are sequentially allocated to each chip to be tested, for example, each resource is allocated sequentially by using an intermediate staggered method. Figure 3 The 4-site hardware based on a certain machine is shown as an example. A digital board has 128 channel resources. By using two digital boards, each site can be allocated 64 channel resources.

[0070] Example 2: According to the order of channels and the number of test stations, the same number of channels are staggered and allocated to each test station in sequence. The number of channels allocated in staggered manner can be decreasing or increasing in sequence, for example, decreasing or increasing one or more channels each time.

[0071] for example Figure 5 As shown in the figure, the channel resources allocated to site 1 are CH 0 to 63; then, one channel is separated, namely CH 64, and channel resources CH 65 to 127 are allocated to site 2; then, two channels are separated, namely CH 128 and CH 129, and channel resources CH 130 to 191 are allocated to site 3; then, three channels are separated, namely CH 192, CH 193 and CH 194, and channel resources CH 195 to 255 are allocated to site 4.

[0072] according to Figure 5 In the channel resource allocation method shown, when the chip is connected to the connectivity test, since the first ATE tester resource (i.e., CH 64) of cable2 is not connected to the chip, the pins connecting the chip on site2 and CH 64 cannot be tested.

[0073] If the connection is wrong, such as Figure 6 As shown, cable 1 and cable 2 are plugged in reverse, cable 1 is connected to site 2, and cable 2 is connected to site 1. Since the first ATE tester resource of cable 2 is not connected to the chip, during the connectivity test, the connectivity test of the pin of site 1 that was originally connected to the first resource of cable 1 fails. Therefore, it can be determined that there is a connection error, and the error can be located to site 1. The operator can correct the connection error based on the error location.

[0074] It should be noted that the unused resources can still be used normally. Figure 7As shown in the figure, the channel resources allocated to site 1 are CH 0 to 63; then one channel is separated, namely CH 64, and channel resources CH 65 to 127 and CH 64 are allocated to site 2; then two channels are separated, namely CH 128 and CH 129, and channel resources CH 130 to 191, CH 128, and CH 129 are allocated to site 3; then three channels are separated, namely CH 192, CH 193, and CH 194, and channel resources CH 195 to 255, CH 192, CH 193, and CH 194 are allocated to site 4. Therefore, each test station can use 64 resources, and the order of resource allocation can be disrupted.

[0075] according to Figure 7 The channel resource allocation method shown is that when performing specific tests on the chip, if the connection is correct, the chip pins corresponding to all channels can be tested.

[0076] If the connection is wrong, such as Figure 8 As shown, cable 1 and cable 2 are plugged in reverse, cable 1 is connected to site 2, and cable 2 is connected to site 1. When performing a specific test, the pin of site 1 that was originally connected to the first resource of cable 1 (actually connected to CH65) will fail the test, thereby confirming that there is a connection error and locating the error to site 1. The operator can correct the connection error based on the error location.

[0077] It should be noted that the specific test here is not limited to the connectivity test. For example, in some embodiments, specific signals, such as clock signals and data signals, can be sent to the chip to enable the chip to implement specific functions and detect whether the corresponding pins of the chip correctly output the expected signals, so as to determine whether there is a plug-in error.

[0078] In addition, setting asymmetric resources corresponding to each chip under test is not limited to the above-mentioned channel resources, and other resources can also be used. This is explained with reference to Example 3 below.

[0079] Example 3: Channel resources are allocated in sequence, and resistors of different resistance values ​​are connected in series to the interfaces of the same pins at different test stations.

[0080] Since the interfaces with the same pins at different test stations are connected in series with resistors of different resistance values, when the chip is tested, the voltage signals corresponding to the interfaces with the same pins at different test stations will be different, which can also be used to determine whether there is a plug-in error.

[0081] According to the serial numbers of the test stations, the resistance values ​​of the resistors connected in series may increase or decrease in sequence, or may change randomly, which is not limited in this embodiment of the present invention.

[0082] like Fig. 9 As shown, it is assumed that the chips on three test stations site1 to site3 are tested at the same time. Each chip needs to test two ports. One port of site1 is connected in series with a resistor R11, the corresponding port of site2 is connected in series with a resistor R21, and the corresponding port of site3 is connected in series with a resistor R31. <R21<R31。

[0083] When plugged in correctly, Fig. 9 As shown, the same current is applied to the ports of each site at the same time, then the port voltage of the CH1 channel detected by the test machine should be smaller than the port voltage of the CH3 channel, and the port voltage of the CH3 channel should be smaller than the port voltage of the CH5 channel.

[0084] If the connection is wrong, such as cable 1 and cable 2 are plugged in reverse, Fig.10 As shown, at this time, the port voltage of the CH1 channel detected by the test machine is greater than the port voltage of the CH3 channel, so it can be determined that there is a connection error, and the error can be located to site1 and site2. The operator can correct the connection error based on the error location.

[0085] The resource error-proofing method for chip testing provided in the embodiment of the present invention only requires the hardware ATE test machine resource definition to be completed during hardware design, and the asymmetric resources corresponding to each chip to be tested are set in sequence. By performing corresponding tests on the chip to be tested, it can be determined whether there are connection errors, thereby achieving an error-proofing effect.

[0086] Accordingly, an embodiment of the present invention also provides a resource foolproof device for chip testing, such as Fig.11 Shown is a structural schematic diagram of the device.

[0087] The chip test resource foolproof device 110 includes a resource allocation module 111 and a plurality of test stations, such as Fig.11 The test stations 1 to n shown in FIG. Where:

[0088] The test station is used to sequentially place the chips to be tested in the test group;

[0089] The resource allocation module 111 is used to number the test stations in the test group and sequentially set asymmetric resources corresponding to each test station, so that the test machine tests the chip to be tested according to the asymmetric resources to determine whether there is a connection error.

[0090] Among them, there can be many ways for the resource allocation module 111 to allocate asymmetric resources to each chip to be tested. For example, the same number of channels can be staggered and allocated to each chip to be tested in sequence according to the order of the channels and the numbers of the chips to be tested. For details, please refer to the description in the embodiment of the resource fool-proofing method for chip testing of the previous invention, which will not be repeated here.

[0091] Accordingly, an embodiment of the present invention further provides a chip testing system, such as Fig.12 As shown, the system includes: a testing machine 120 and the resource foolproofing device 110 .

[0092] The resource foolproof device 110 is used to sequentially place the chips to be tested in the test group, number the test stations in the test group, and sequentially set asymmetric resources corresponding to each test station.

[0093] The testing machine 120 includes a testing module 1201 and an inspection module 1202 .

[0094] In addition, the test machine 120 may have multiple test interfaces, each test interface is connected to a test line, and each test line corresponds to multiple channels.

[0095] When testing a chip to be tested, a chip to be tested is placed in each test station, and the interface of each test station can be connected to one or more test lines. Fig.12 The dotted lines in the figure represent interfaces for connecting the test lines of the test machine 120 to each test station according to the asymmetric resources set by the resource foolproofing device 110 .

[0096] The test module 1201 is used to test the chips to be tested after placing all the chips to be tested on the corresponding test stations in sequence and connecting the test lines of the machine to the interfaces of each test station. The test module 1201 may test the chips to be tested by a connectivity test or a test of controlling the chip to achieve a specific output, which is not limited in the embodiment of the present invention.

[0097] The checking module 1202 is used to determine whether there is a connection error when the test result of a test station is fixedly invalid.

[0098] In some embodiments, the test machine 120 may further include: a display module for indicating the serial number of the test station whose test result is fixedly invalid.

[0099] Using this chip testing system, not only can you easily and conveniently determine whether there is a connection error, but you can also automatically locate the test station where the test interface is incorrectly connected, thereby ensuring the accuracy of the test results and effectively avoiding the misplacement or misplacement of the chip.

[0100] The chip testing system does not require additional hardware devices and additional software processing, and can simply and conveniently automatically locate the chip with the wrong test interface docking, thereby ensuring the accuracy of the test results and effectively avoiding the misplacement or misplacement of the chip.

[0101] The embodiment of the present invention further discloses a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is run, the steps of the method shown in the above embodiment can be executed. The storage medium may include a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc. The storage medium may also include a non-volatile memory (non-volatile) or a non-transitory memory, etc.

[0102] Regarding the various modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, or hardware modules / units, or they can be partially software modules / units and partially hardware modules / units. For example, for various devices and products applied to or integrated in a chip, the various modules / units included therein can all be implemented in the form of hardware such as circuits, or at least some of the modules / units can be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in a chip module, the various modules / units included therein can all be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component of the chip module (such as a chip, circuit module, etc.) or in different components, or at least some of the modules / units can be implemented in the form of software programs. It is implemented in the form of a software program, which runs on a processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in hardware such as circuits; for various devices and products applied to or integrated in the terminal equipment, the various modules / units contained therein can be implemented in hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or in different components in the terminal equipment, or, at least some modules / units can be implemented in the form of a software program, which runs on a processor integrated inside the terminal equipment, and the remaining (if any) modules / units can be implemented in hardware such as circuits.

[0103] It should be noted that the “plurality” appearing in the embodiments of the present application refers to two or more than two.

[0104] The first, second, etc. descriptions appearing in the embodiments of the present application are only used for illustration and distinction of the description objects. There is no order, nor do they indicate any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0105] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination thereof. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means.

[0106] In the several embodiments provided in the present application, it should be understood that the disclosed devices and systems can be implemented in other ways. For example, the device embodiments described above are merely schematic; for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0107] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0108] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0109] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform some steps of the method described in each embodiment of the present application.

[0110] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so the protection scope of the present application shall be subject to the scope defined by the claims.

Claims

1. A resource foolproof method for chip testing, characterized in that: The method comprises: The test stations in the test group are numbered, and asymmetric resources corresponding to each test station are sequentially set, so that the test machine tests the chip to be tested according to the asymmetric resources to determine whether there is a connection error.

2. The method according to claim 1, characterized in that The sequentially setting of asymmetric resources corresponding to each test station includes: According to the order of test resources and the number of test stations, different test resources are staggeredly allocated to each test station.

3. The method according to claim 2, characterized in that The staggered allocation of different test resources to each test station in turn includes: The same number of channels are allocated to each test station in sequence.

4. The method according to claim 2, characterized in that: The staggered allocation of different test resources to each test station in turn includes: After shifting one or more channels for each test station in turn, a set number of channels are allocated.

5. The method according to claim 1, characterized in that The sequentially setting of asymmetric resources corresponding to each test station includes: Design different peripheral circuits for different test stations.

6. The method according to claim 5, characterized in that Resistors of different resistance values ​​are connected in series to the interfaces of the same pins at different test stations.

7. The method according to claim 6, characterized in that According to the serial numbers of the test stations, the resistance values ​​of the resistors connected in series increase or decrease in sequence.

8. The method according to any one of claims 1 to 7, characterized in that: The method further comprises: After placing all the chips to be tested in the test group on the corresponding test stations of the test board in sequence and connecting the machine test resources to the interfaces of each test station, testing the chips to be tested according to the set asymmetric resources; If the test results of a test station are always invalid, it is determined that there is a connection error.

9. The method according to claim 8, characterized in that The machine channel is arranged on one or more boards.

10. The method according to claim 8, characterized in that The method further comprises: Indicates the serial number of the test station where the test result is fixed invalid.

11. A resource foolproof device for chip testing, characterized in that: The device comprises: a resource allocation module and a plurality of test stations; The test station is used to sequentially place the chips to be tested in the test group; The resource allocation module is used to number the test stations in the test group and sequentially set asymmetric resources corresponding to each test station, so that the test machine tests the chip to be tested according to the asymmetric resources to determine whether there is a connection error.

12. A chip testing system, characterized in that: The system comprises: a test machine, and a resource foolproof device for chip testing as claimed in claim 11; the test machine comprises: a test module and an inspection module; the test module is used to test the chips to be tested after placing all the chips to be tested in sequence on corresponding test stations and connecting the test lines of the test machine to the interfaces of each test station; The checking module is used to determine that there is a connection error when the test result of a test station is fixedly invalid.

13. The chip testing system according to claim 12, characterized in that: The test machine also includes: The display module is used to indicate the serial number of the test station whose test result is fixedly invalid.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the resource fool-proofing method for chip testing according to any one of claims 1 to 10 are executed.

15. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the resource fool-proofing method for chip testing described in any one of claims 1 to 10 are implemented.

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