Reverse connection prevention test method based on SiP chip real-installation system
By designing specific pin position and control logic in the substrate and the implementation system board of the SiP chip, and realizing anti-reverse test items in the upper computer, the challenges in SiP-level chip testing and yield are solved, and a more efficient and economical testing process is achieved.
Patent Information
- Application Number
- CN202411860456.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2025-03-11
AI Technical Summary
SiP-grade chips have challenges in testing and yield, including loss of measurability, increased testing time and cost, and loss of yield.
An anti-reverse test method based on SiP chip implementation system is adopted. By selecting the location of specific ground pins and empty pins in the substrate design of the SiP chip, and controlling the pull-up resistor and enable pins in the implementation system board design, combined with the judgment of the anti-reverse test items in the upper computer design, fully automated testing is achieved.
Reduces the loss of chip damage caused by human reasons, reduces the pressure on testers, improves the efficiency of chip testing, reduces costs, and increases production capacity.
Smart Images
Figure CN119596115A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of SiP testing, and in particular to a reverse connection prevention testing method based on a SiP chip mounting system. Background Art
[0002] SiP packaging is a packaging solution that integrates multiple functional wafers, including processors, memories and other functional wafers, into one package to achieve a basically complete functional package. It corresponds to SOC (system on aChip). SiP packaging is a packaging method that places different bare chips side by side or stacked, while SOC highly integrates the components required by the system into one chip. SiP-level chips can effectively combine the devices required for each function into one, achieving a higher level of integration, thereby realizing a basically complete functional device; at the same time, relying on efficient production processes and testing capabilities, it can greatly reduce product development time and save costs during use.
[0003] Since SiP integrates multiple chips, it poses great challenges in testing and yield. In terms of testing, since the bare chips are integrated together, the interconnection of the pins will lead to some loss of testability; in addition, from the perspective of testing time and cost, it is impossible to ensure that every chip can be tested. The testing process will also change. In the past, the packaged chips were tested, but now they are tested while being sealed to ensure the yield. In terms of yield, SiP integrates many chips and devices, and the yield loss in the packaging and testing of each chip / device will be added to the final SiP module. The cost of SiP modules is much higher than the cost of packaging a single chip, and the importance of yield is extremely critical.
[0004] Currently, in the production process of SiP-level chips, Final test is divided into two steps: ATE (automatic test equipment) and SLT (system level test). The installed system-level test equipment is dedicated to a single board, and it takes a long time and cost to repair or re-invest after damage. Summary of the invention
[0005] The purpose of the present invention is to provide a reverse connection prevention test method based on a SiP chip mounting system to solve the problems in the background technology.
[0006] In order to solve the above technical problems, the present invention provides a method for testing reverse connection of a SiP chip mounting system, comprising:
[0007] Step A: When designing the substrate of the SiP chip, select three ground pins and one empty pin on the SiP chip, place the empty pin at the SiP chip 1 pin mark, and the other three ground pins at the other three corners of the SiP chip;
[0008] Step B: When implementing the system board design, the SiP chip pin 1 is left floating, pulled up to the board voltage VCC, and connected to the enable pin of the power supply chip;
[0009] Step C: When designing the host computer, add an anti-reverse connection test item to the test items. The first test item is the anti-reverse connection test. After the test is normal, subsequent parameter tests are performed to achieve fully automated testing.
[0010] In one embodiment, in step A, the SiP chip has multiple empty pins and ground pins, and their positions are not fixed. The empty pins are selected to be symmetrical with the ground pins. Through experimental verification, it is found that the positions of the empty pins and the ground pins are taken into consideration in the substrate design stage, and the experimental verification effect is better when the socket layout is designed in the subsequent actual mounting board.
[0011] In one embodiment, in step B, when the hardware test board is designed, when the SiP chip is placed correctly, the power pin on the power supply chip is pulled up to VCC, the power supply chip enables a high level, the power chip starts normally, and the power supply is normal; when the SiP chip is placed incorrectly, the power supply chip is powered on, the power supply chip enable is connected to GND, the power chip enable is low level, the power supply chip cannot start, and the power-on fails.
[0012] In one embodiment, in step C, the anti-reverse connection test item is placed first, and whether the SiP chip is placed correctly is judged by whether the power-on is successful. After the power-on is successful, subsequent function and parameter tests are started, and the entire test process is automated.
[0013] In one embodiment, the power supply chip has an enable pin, which controls the working state of the power supply chip and enables the startup and shutdown of the control. By applying a high level or low level signal to the enable pin, the power supply chip can be controlled to be turned on or off.
[0014] In one embodiment, when designing the substrate of the SiP chip, the arrangement of the bare cores on the substrate follows the following rules: the signal path length shortens the transmission path of high-frequency signals; bare cores that need to interact frequently are placed close to each other; power distribution, reasonable planning of power line and ground line layout; use of multi-layer board design to separate the power layer and the ground layer to reduce the power loop area; high-power bare cores are placed in locations that are convenient for heat dissipation; shielding materials or shielding covers are used to isolate sensitive areas; bare cores are evenly distributed, and for large substrates, support points are added to enhance structural stability.
[0015] The present invention provides a reverse connection prevention test method based on a SiP chip installation system, which is upgraded on the basis of a traditional chip test solution and adds reverse connection prevention judgment, thereby greatly reducing the loss of chips damaged by human factors. At the same time, it also reduces the pressure on testers, who need to repeatedly confirm whether the chip is placed correctly. Through hardware reverse connection prevention, the pressure in this regard can be reduced. Even if the chip is placed reversely, the test board will not power on the chip and will not cause chip damage. This method can also improve the efficiency of chip testing, reduce costs, and increase production capacity. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is the block diagram of the SiP chip installation system-level test platform.
[0017] Figure 2 This is a schematic diagram of the connection of the SiP chip's reverse connection protection mounting board.
[0018] Figure 3 This is a schematic diagram of the pin layout of the SiP chip substrate design.
[0019] Figure 4 It is the flow chart of the SiP chip installation system-level test platform.
[0020] Figure 5 This is a schematic diagram of the bare die layout in the SiP chip substrate design.
[0021] Figure 6 It is a schematic diagram of the upper computer interface display layout.
[0022] Figure 7 It is a principle block diagram of the actual installation test of the chip under test. DETAILED DESCRIPTION
[0023] The following is a further detailed description of a method for testing reverse connection based on a SiP chip installation system proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0024] Figure 1 This is the block diagram of the SiP chip installation system-level test platform. It is necessary to consider different components and the connection methods between them. The SiP chip installation system-level test platform mainly includes power supply, signal source clock, input signal, which is connected to the installation system test bench through the KGD socket. The host computer and the installation system test bench exchange data through the RS485 interface. The functions of each part and the connection methods between them are explained in detail below.
[0025] The host computer controls the entire test process and communicates with the installed system test bench through different interfaces, using the RS485 interface. The installed system test bench includes power supply, signal source, clock source, etc., and provides necessary test signals and power to the device under test (SiP chip). The installed test system is connected to the SiP chip through the KGD socket. The device under test, i.e. the SiP chip, receives the power and signal provided by the installed system test bench and generates a response. The installed system test bench transmits power, signal, clock, etc. to the SiP chip. The power supply is output to the installed system test bench, and the internal test board of the installed system test bench converts different voltages through the power conversion chip to provide power to the SiP chip. The required test signal and clock signal generated by the signal source and the clock source are provided to the SiP chip through the installed system test bench. For the SiP chip under test, external power, clock, and tested signal are required so that the SiP chip can work normally. After working normally, the SiP chip transmits data to the host computer through RS485, and the host computer analyzes the data to determine whether the SiP chip is normal. The present invention mainly describes the part where the installed system test bench provides power to the SiP chip.
[0026] Figure 2This is a schematic diagram of the connection of the SiP chip to the mounting board for reverse connection prevention. The SiP chip pin 1 is NC (empty) and is connected to the enable pin of the power chip on the mounting board through a pull-up resistor. When the SiP chip is placed correctly during the mounting test, the enable pin of the power supply chip is completely determined by the external power supply because the SiP chip pin 1 is empty. In electronic devices, DC-DC power chips are circuits used to convert one DC voltage level to another DC voltage level. They are widely used in various devices that require different voltage levels. DC-DC power chips usually have an enable pin, through which the working state of the DC-DC power chip can be controlled. Enable controls startup and shutdown. By applying a high or low level signal to the enable pin, the DC-DC power chip can be controlled to be turned on or off, which provides a flexible power management method for the system. The external power supply provided by the actual installation system test bench is high level by default, so the enable pin of the DC-DC power supply chip provides a high level, the DC-DC power supply chip is turned on, and the normal voltage is output to supply power to the SiP chip normally; when the SiP chip is placed incorrectly, because the other three direction pins of the SiP chip are all GND, when placed incorrectly, the enable pin of the DC-DC power supply chip is directly connected to GND, but when the enable (Enable) is low level, the DC-DC power supply chip is turned off, and the SiP chip will not be powered on. Through this kind of control on the hardware architecture, the actual installation system test bench will not power on the product under test and burn the product under test due to incorrect placement of the SiP chip, which protects the product under test to a certain extent, reduces the burning of the product due to the tester's misoperation, and greatly reduces the loss.
[0027] Figure 3A pin layout diagram is designed for a SiP chip substrate. The design of a SiP chip substrate is a complex and precise process, especially in terms of pin layout. A reasonable pin layout can not only improve the performance of the product, but also ensure the integrity and reliability of the signal. The present invention is mainly aimed at the layout and signal definition settings of the four pins around the chip, and the layout and signal definition settings of other pins inside the SiP chip are no longer repeated. In chip design and application, sometimes some pins (such as pin 1) need to be left floating. A floating pin refers to a pin that is not connected to any external circuit or internal circuit. Although floating pins are allowed in some cases, in most cases, in order to ensure the stability and reliability of the SiP chip, special attention needs to be paid to the handling of floating pins. Since the reliability of the later test is taken into consideration when designing the SiP chip, no internal or external connection is made to pin 1 to avoid reliability problems. When pin 1 is suspended, the position of pin 1 of the chip can be clearly judged to reduce the chance of misplacement. At the same time, the other three pins around the SiP chip are defined as GND when designing the SiP chip. No matter how the SiP chip rotates, there will only be two situations: one is that when it is placed correctly, the pin at the pin 1 mark is suspended, the power supply chip of the actual system test bench is turned on, and the power supply is normal; the other is that when it is placed incorrectly, the pin at the pin 1 mark is GND, the power supply chip of the actual system test bench is turned off, and the power supply cannot be supplied. When laying out the product pins, select the three ground pins and one NC on the SiP chip, and place the NC at the pin 1 mark of the SiP chip. The other three ground pins are respectively located at the other three corners of the SiP chip. In this arrangement, the NC pin and GND are symmetrical, which is conducive to judging right and wrong after misplacement. The anti-reverse connection problem is considered in the design stage, which is conducive to the design of the actual board.
[0028] Figure 4 Flowchart of the system-level test platform for SiP chip installation. Designing and implementing a system-level test platform for SiP chip installation is a complex engineering task involving multiple steps and stages. Figure 4 It is a detailed flow chart. First, install the chip under test, start the host computer software, anti-reverse connection detection, FPGA program loading, DSP program burning, DSP reset and interrupt function test, EMIF port function test, SDRAM data read and write function test, Mcbsp interface function test, FPGA reserved I / O function test, PROM function test, QSPI FLASH function test, 1553B interface function test, SiP chip function test, print test results, power off, and take out the chip under test.
[0029] The present invention mainly describes the anti-reverse connection detection part, and other chip function tests are not repeated. The chip is installed according to the SiP chip 1 pin mark, and the host computer detects the above Figure 3The content of the test flow is interpreted. If the voltage of the enable (Enable) is detected to be 3.3V, the anti-reverse connection indicator light of the host computer interface will turn green, indicating that the chip is installed normally, and the subsequent test will be performed to power on the SiP chip. When the voltage of the enable (Enable) is detected to be 0V, the anti-reverse connection indicator light of the host computer interface will turn red, and the subsequent test flow will be stopped, and the host computer will stop running. The above test flow can ensure that the design of the SiP chip's actual system-level test platform is scientific and reasonable, and the test results are accurate and reliable.
[0030] Figure 5 Design a bare die layout diagram for the SiP chip substrate. In the design of SiP chips, the bare die arrangement on the substrate is a key link, which directly affects the overall performance, reliability and manufacturing cost of the SiP chip. Reasonable bare die arrangement can improve signal integrity, reduce electromagnetic interference, simplify heat dissipation design, and help improve production efficiency. The following are some factors and steps that need to be considered when designing the arrangement of bare cores on the SiP chip substrate. The first is the signal path length. Try to shorten the transmission path of high-frequency signals to reduce signal loss and delay. For bare cores that need to interact frequently, try to place them closer; secondly, power distribution, reasonably plan the layout of power lines and ground lines to avoid power noise interference, use multi-layer board design, separate the power layer and ground layer, and reduce the power loop area; then, the overall thermal management of the SiP chip, high-power bare cores should be placed in a position with good heat dissipation, such as the edge of the substrate or near the heat sink, consider using heat pipes or other heat dissipation structures to help dissipate heat; thirdly, EMI / EMC (electromagnetic interference / electromagnetic compatibility), reduce the parallel length of high-speed signal lines, reduce the risk of crosstalk, and use shielding materials or shielding covers to isolate sensitive areas; finally, mechanical strength, the distribution of bare cores should be even, avoid local excessive force causing deformation of the substrate, and for large substrates, increase support points to enhance structural stability.
[0031] The SiP chip under test consists of DSP, FPGA, SDRAM, configuration chip PROM, 1553B transceiver and QSPI-FLASH. The bare core layout is reasonably designed in full reference to the above design rules. During the layout design process, full consideration is given to future scalability and maintainability, and relevant industry standards and specifications are followed to ensure product safety and compliance.
[0032] Figure 6It is a schematic diagram of the upper computer interface display layout. The upper computer interface is designed to display and control various parameters and states of the SiP chip. The intuitiveness of the upper computer display directly affects the user experience and the overall performance of the system. A good upper computer interface should be intuitive, easy to use, and fully functional. The upper computer is mainly divided into the following steps: First, the main interface layout is divided into a navigation bar, which provides buttons for quick access to various functional modules; a status bar that displays the current system status and important information; and a work area that displays the main charts, tables, and controls. Second, the upper computer control selection uses buttons to trigger specific operations, such as starting a test, stopping a test, etc. Third, real-time data displays the real-time values of key parameters, such as voltage, current, IO status, SDRAM status, and displays specific values for the external interface status. At the same time, the anti-reverse connection test item judgment is added to the test items. This test item is used first to determine whether the chip is placed correctly as to whether the power-on is successful; after the power-on is successful, the subsequent function and parameter tests are started, and the entire test process is automated.
[0033] Figure 7 This is the principle diagram of the SiP chip installation test under test, including hardware components: the system consists of three parts: the installation test board, the KGD socket, and the SiP chip. SiP chip installation test is an important step in the electronic manufacturing process, which is used to detect whether the components and connections on the circuit board are correct. The principle diagram of the installation test can help understand and design the test system. Figure 7 This is a detailed description of the principle block diagram of the actual installation test of the present invention and its components: the actual installation test board is responsible for testing all external interfaces of the SiP chip, data collection and analysis, and user interface display, test program management: loading and running test programs, and controlling the test process.
[0034] Data collection and analysis: Collect test data, analyze and process it. User interface: Provide a graphical interface to facilitate user operation and viewing of test results. The test mainly includes the following steps:
[0035] 1. Test interface
[0036] Test fixture: used to fix and contact the chip under test to ensure reliable transmission of test signals.
[0037] Contact point: Contacts with the test point on the chip under test to transmit the test signal.
[0038] Test socket: connects the test fixture and test instrument to ensure signal transmission.
[0039] 2. Test equipment
[0040] Power supply: Provides stable power to the chip under test.
[0041] Oscilloscope: used to observe and analyze signal waveforms.
[0042] Digital multimeter: measures voltage, current, resistance and other parameters.
[0043] Signal generator: Generates the signals required for testing.
[0044] 3. Test preparation stage:
[0045] Fix the chip under test on the test fixture.
[0046] Connect the test fixture and test instrument.
[0047] 4. Test initialization:
[0048] The test host loads the test program.
[0049] Test instrument initialization and reverse connection detection.
[0050] 5. Test execution:
[0051] The test host sends test signals to the chip under test through the test fixture.
[0052] The test instrument collects the response signal of the chip under test.
[0053] The test software analyzes and processes the collected data.
[0054] 6. Result output:
[0055] The test software displays the test results, including pass / fail status, specific parameter values, etc.
[0056] Generate test reports to record test data and results.
[0057] Through the above principle block diagram and test step description, the test composition of the actual test system can be clearly understood.
[0058] The actual installation test software consists of: host computer software, SiP chip software (FPGA software, DSP software). Designing and implementing SiP chip software and actual installation test software, especially software related to FPGA and DSP, is a complex but crucial process. These software not only need to realize functions, but also need to optimize performance, ensure reliability and easy maintenance. At the same time, the host computer software also needs to increase emergency warnings during various tests, as well as test protection. The present invention is mainly designed for the protection part of the chip under test, and double protection is performed through hardware anti-reverse and software anti-reverse, so as to achieve a real anti-reverse design.
[0059] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for testing reverse connection based on SiP chip installation system, characterized in that: The following steps are involved: Step A: When designing the substrate of the SiP chip, select three ground pins and one empty pin on the SiP chip, place the empty pin at the SiP chip 1 pin mark, and the other three ground pins at the other three corners of the SiP chip; Step B: When implementing the system board design, the SiP chip pin 1 is left floating, pulled up to the board voltage VCC, and connected to the enable pin of the power supply chip; Step C: When designing the host computer, add an anti-reverse connection test item to the test items. The first test item is the anti-reverse connection test. After the test is normal, subsequent parameter tests are performed to achieve fully automated testing.
2. The method for anti-reverse connection test based on SiP chip installation system according to claim 1, characterized in that: In step A, the SiP chip has multiple empty pins and ground pins, and the distribution positions are not fixed. The empty pins are selected to be symmetrical with the ground pins. Through experimental verification, it is found that the positions of the empty pins and the ground pins are taken into consideration in the substrate design stage, and the experimental verification effect is better when the socket layout is designed in the subsequent actual mounting board.
3. The anti-reverse connection test method based on SiP chip installation system according to claim 1, characterized in that: In the step B, when the hardware test board is designed, when the SiP chip is placed correctly, the power pin on the power supply chip is pulled up to VCC, the power supply chip enables the high level power chip to start normally, and the power supply is normal; When the SiP chip is placed incorrectly, the power supply chip is powered on, the power supply chip enable is connected to GND, the power supply chip enable is at a low level, the power supply chip cannot start, and the power-on fails.
4. The method for anti-reverse connection test based on SiP chip installation system according to claim 1, characterized in that: In step C, the anti-reverse connection test item is placed first, and whether the SiP chip is placed correctly is judged by whether the power-on is successful. After the power-on is successful, the subsequent function and parameter tests are started, and the entire test process is automated.
5. The method for anti-reverse connection test based on SiP chip installation system according to claim 3, characterized in that: The power supply chip has an enable pin, through which the working state of the power supply chip is controlled, enabling control startup and shutdown. By applying a high level or low level signal to the enable pin, the power supply chip can be controlled to be turned on or off.
6. The method for anti-reverse connection test based on SiP chip installation system according to claim 1, characterized in that: When designing the substrate of the SiP chip, the arrangement of the bare cores on the substrate follows the following rules: the signal path length shortens the transmission path of high-frequency signals; bare cores that need to interact frequently are placed close together; Power distribution, reasonable planning of power line and ground line layout; Use a multi-layer board design to separate the power layer and the ground layer to reduce the power loop area; place high-power bare cores in locations that facilitate heat dissipation; use shielding materials or shielding covers to isolate sensitive areas; the bare cores should be evenly distributed, and for large substrates, add support points to enhance structural stability.