Control method of voltage source array and voltage source array

Abstract

The invention relates to a control method of a voltage source array and the voltage source array, the control method is applied to a voltage source array circuit, the voltage source array circuit comprises a plurality of DAC chips and a plurality of amplifiers, each DAC chip comprises a digital signal input interface and a plurality of voltage output interfaces, and each voltage output interface is connected with the input end of one amplifier; the method comprises the following steps: controlling at least one DAC chip to convert a received digital signal into an analog voltage signal, and outputting an analog voltage through a target voltage output interface; and controlling a target amplifier corresponding to the target voltage output interface to be connected, and amplifying the analog voltage signal, so that the output end of the target amplifier outputs target power.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuit design, and in particular to a control method of a voltage source array and a voltage source array. Background Art

[0002] Currently, in applications of precision signal control and multi-channel analog signal output, digital-to-analog converters (DACs) are widely used to provide high-precision voltage outputs.

[0003] As modern electronics has an increasing demand for high-precision analog voltage devices, especially in optical sensors, precision instruments, and power management systems, traditional low-precision voltage sources cannot meet these requirements for high accuracy, stability, and driving power generation. In order to meet these requirements, existing technologies require the use of DAC chips to achieve precise voltage output.

[0004] However, existing DAC chips have certain limitations in output power and signal amplification. Especially in scenarios with high channel counts and multiple signal outputs, the power output and output accuracy of DAC chips are often insufficient. Summary of the invention

[0005] Based on this, it is necessary to provide a control method and a voltage source array for the above-mentioned technical problems, which can at least improve the driving capability, output power and output accuracy of the voltage source array while realizing large-scale, multi-channel voltage input.

[0006] In a first aspect, the present application provides a control method for a voltage source array, which is applied to a voltage source array circuit, wherein the voltage source array circuit includes multiple DAC chips and multiple amplifiers, each DAC chip includes a digital signal input interface and multiple voltage output interfaces, and each voltage output interface is connected to the input end of an amplifier; wherein the method includes: controlling at least one DAC chip to convert a received digital signal into an analog voltage signal, and outputting the analog voltage through a target voltage output interface; controlling the connection with a target amplifier corresponding to the target voltage output interface, and amplifying the analog voltage signal so that the output end of the target amplifier outputs a target power.

[0007] In one of the embodiments, the at least one DAC chip further performs the following steps: obtaining an amplified analog voltage signal; determining whether the absolute value of the voltage difference between the amplified analog voltage signal and the target voltage signal is greater than a preset error value; if the absolute value of the voltage difference between the amplified analog voltage signal and the target voltage signal is greater than the preset error value, calibrating the analog voltage signal according to the voltage difference between the amplified analog voltage signal and the target voltage signal until the absolute value of the voltage difference between the amplified analog voltage signal and the target voltage signal is less than or equal to the preset error value.

[0008] In one embodiment, the target power is greater than 300 mW.

[0009] In one embodiment, the amplified analog voltage signal is between -10V and 10V.

[0010] In one embodiment, the digital signal output range of each DAC chip is 0-65535.

[0011] In a second aspect, the present application further provides a voltage source array, the voltage source array comprising a plurality of DAC chips and a plurality of amplifiers;

[0012] Among them, each DAC chip includes a digital signal input interface and multiple voltage output interfaces, each voltage output interface is connected to the input end of an amplifier, the digital signal input interface of each DAC chip is a serial communication interface for receiving digital signals, and the output end of each amplifier is used to output the target power corresponding to the digital signal.

[0013] In one of the embodiments, the output end of each amplifier is also connected to a voltage feedback interface of a DAC chip corresponding to the amplifier to amplify the voltage output by the DAC chip.

[0014] In one of the embodiments, a power supply module is further included, and the power supply module is used to supply power to multiple DAC chips and multiple amplifiers.

[0015] In one of the embodiments, the voltage source array further includes a plurality of filter capacitor modules, and the plurality of filter capacitor modules are formed between the output end of the power module and the plurality of DAC chips and / or between the output end of the power module and the plurality of amplifiers.

[0016] In one embodiment, the plurality of DAC chips, the power supply module, the plurality of filter capacitor modules and the plurality of amplifiers are integrated on a printed circuit board.

[0017] In the third aspect, the present application also provides a control device for a voltage source array, which is applied to a voltage source array circuit, wherein the voltage source array circuit includes multiple DAC chips and multiple amplifiers, each DAC chip includes a digital signal input interface and multiple voltage output interfaces, and each voltage output interface is connected to the input end of an amplifier; wherein the device includes an analog voltage output module and a target power output module, the analog voltage output module is used to control at least one DAC chip to convert the received digital signal into an analog voltage signal, and output the analog voltage through the target voltage output interface; the target power output module is used to control the connection with the target amplifier corresponding to the target voltage output interface, and amplify the analog voltage signal so that the output end of the target amplifier outputs the target power.

[0018] In a fourth aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0019] Controlling at least one DAC chip to convert the received digital signal into an analog voltage signal, and outputting the analog voltage through a target voltage output interface;

[0020] The target amplifier corresponding to the target voltage output interface is controlled to be connected, and the analog voltage signal is amplified so that the output end of the target amplifier outputs the target power.

[0021] In a fifth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the following steps are implemented:

[0022] Controlling at least one DAC chip to convert the received digital signal into an analog voltage signal, and outputting the analog voltage through a target voltage output interface;

[0023] The target amplifier corresponding to the target voltage output interface is controlled to be connected, and the analog voltage signal is amplified so that the output end of the target amplifier outputs the target power.

[0024] In a sixth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0025] Controlling at least one DAC chip to convert the received digital signal into an analog voltage signal, and outputting the analog voltage through a target voltage output interface;

[0026] The target amplifier corresponding to the target voltage output interface is controlled to be connected, and the analog voltage signal is amplified so that the output end of the target amplifier outputs the target power.

[0027] The control method and voltage source array of the above-mentioned voltage source array meet the large-scale and multi-channel requirements of the voltage source array by forming a voltage source array circuit, and improve the driving power and output power through devices such as amplifiers in the voltage source array circuit, and improve the output accuracy by controlling the voltage source array. At least, it can improve the driving capability, output power and output accuracy of the voltage source array while achieving large-scale and multi-channel voltage input. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 is a flow chart of a control method of a voltage source array in one embodiment;

[0030] Figure 2 is a flow chart of a control method of a voltage source array in another embodiment;

[0031] Figure 3 is a circuit diagram of a power module in one embodiment;

[0032] Figure 4 A circuit diagram of a DAC chip in one embodiment;

[0033] Figure 5 is a circuit diagram of an amplifier in one embodiment;

[0034] Figure 6 is a structural block diagram of control of a voltage source array in one embodiment;

[0035] Figure 7 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment.

[0036] Reference numerals and descriptions:

[0037] Q1, field effect transistor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; C1, first inductor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; C5, fifth capacitor; C6, sixth capacitor; C7, seventh capacitor; C8, eighth capacitor; C9, ninth capacitor; C10, tenth capacitor; C11, eleventh capacitor; C12, twelfth capacitor; LED, light emitting diode; D1, first Shockwave The first and second Schottky diodes are as follows: D1, D2, the second Schottky diode; D3, the third Schottky diode; D4, the fourth Schottky diode; U1, the first boost converter chip; U2, the first voltage regulator integrated chip; U3, the second voltage regulator integrated chip; DAC, DAC chip; R6, the sixth resistor; U4, amplifier; R8, the eighth resistor; R9, the ninth resistor; R10, the tenth resistor; R11, the eleventh resistor; R12, the twelfth resistor; C13, the thirteenth capacitor; C14, the fourteenth capacitor. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0039] The control method of the voltage source array and the voltage source array provided in the embodiments of the present application can be applied to the technical field of electronic circuit design.

[0040] Please refer to Figure 1 In an exemplary embodiment, a control method for a voltage source array is provided, comprising the following steps S101 to S102.

[0041] Specifically, the control method of the voltage source array is applied to a voltage source array circuit, wherein the voltage source array circuit includes multiple DAC chips DAC and multiple amplifiers U4, each DAC chip DAC includes a digital signal input interface and multiple voltage output interfaces, and each voltage output interface is connected to the input end of an amplifier U4.

[0042] in:

[0043] Step S101, controlling at least one DAC chip DAC to convert a received digital signal into an analog voltage signal, and outputting the analog voltage through a target voltage output interface.

[0044] Step S102, controlling the target amplifier U4 corresponding to the target voltage output interface to be connected, and amplifying the analog voltage signal, so that the output end of the target amplifier U4 outputs the target power.

[0045] Specifically, the at least one DAC chip DAC also performs the following steps: obtaining the amplified analog voltage signal; determining whether the absolute value of the voltage difference between the amplified analog voltage signal and the target voltage signal is greater than a preset error value; if the absolute value of the voltage difference between the amplified analog voltage signal and the target voltage signal is greater than the preset error value, calibrating the analog voltage signal according to the voltage difference between the amplified analog voltage signal and the target voltage signal until the absolute value of the voltage difference between the amplified analog voltage signal and the target voltage signal is less than or equal to the preset error value.

[0046] For example, see Figure 2 In an exemplary embodiment, another control method of a voltage source array is provided, comprising the following steps S201 to S206. Wherein:

[0047] Step S201, data input: input digital signal through SPI interface.

[0048] Step S202, DAC signal conversion: DAC converts the digital signal into an analog voltage.

[0049] Step S203, signal amplification: the amplifier U4 amplifies the voltage output by the DAC to -10V to 10V.

[0050] Step S204: determine the calibration voltage value.

[0051] If it is determined that the calibration voltage value is normal, step S205 is executed, output power: each channel can provide a power output of more than 300mW.

[0052] If it is determined that the calibration voltage value is abnormal, step S206 is executed to adjust the digital signal, and after executing S206, step S202 is re-executed until the voltage value is normal.

[0053] Wherein, the target power is greater than 300mW.

[0054] As an example, the target power may be 301 mW, 310 mW, 350 mW, 400 mW, 500 mW, and so on.

[0055] The amplified analog voltage signal is between -10V and 10V.

[0056] As an example, the amplified analog voltage signal may be -10V, -7V, -3V, 2V, 5V, 7V, 10V, etc.

[0057] Among them, the digital signal output range of each DAC chip DAC is 0-65535.

[0058] As an example, the digital signal of each DAC chip DAC can output a digital signal of 0, 1302, 27500, 52733, 65535, etc.

[0059] Specifically, the control method of the voltage source array is applied to a voltage source array circuit, wherein the voltage source array circuit includes multiple DAC chips DAC and multiple amplifiers U4, each DAC chip DAC includes a digital signal input interface and multiple voltage output interfaces, and each voltage output interface is connected to the input end of an amplifier U4.

[0060] Among them, each DAC chip DAC includes a digital signal input interface and multiple voltage output interfaces, each voltage output interface is connected to the input end of an amplifier U4, the digital signal input interface of each DAC chip DAC is a serial communication interface for receiving digital signals, and the output end of each amplifier U4 is used to output the target power corresponding to the digital signal.

[0061] The output end of each amplifier U4 is also connected to a voltage feedback interface of a DAC chip DAC corresponding to the amplifier U4 to amplify the voltage output by the DAC chip DAC.

[0062] The voltage source array further includes a power supply module, which is used to supply power to multiple DAC chips DAC and multiple amplifiers U4.

[0063] The voltage source array further includes a plurality of filter capacitor modules, and the plurality of filter capacitor modules are formed between the output end of the power module and a plurality of DAC chips DAC and / or between the output end of the power module and the plurality of amplifiers U4.

[0064] Among them, the multiple DAC chips DAC, the power supply module, the multiple filter capacitor modules and the multiple amplifiers U4 are integrated on a printed circuit board.

[0065] As an example, see Figure 3 , Figure 3The circuit diagram of the power module in one embodiment is shown in FIG. 1 , wherein the circuit of the power module includes a field effect transistor Q1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first inductor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a light emitting diode LED, a first Schottky diode D1, a second Schottky diode D2, a third Schottky diode D3, a fourth Schottky diode D4, a first boost converter chip U1, a first voltage stabilizing integrated chip, a second voltage stabilizing integrated chip U2, and a first voltage stabilizing integrated chip U3.

[0066] Among them, the model of the field effect transistor Q1 can be WPM2015-3 / TR, the model of the first boost converter chip U1 can be MT3540, the model of the first voltage stabilizing integrated chip can be 79L12, and the model of the second voltage stabilizing integrated chip U2 and the first voltage stabilizing integrated chip U3 can be 79L13.

[0067] Among them, the G pole of the field effect tube Q1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is grounded, the D pole of the field effect tube Q1 is connected to the power supply end, the S pole of the field effect tube Q1 is connected to the vin pin of the first boost chip, one end of the second resistor R2 is connected to the S pole of the field effect tube Q1, the other end of the second resistor R2 is connected to one end of the first resistor R1, one end of the first capacitor is connected to one end of the first resistor R1, the other end of the first capacitor is grounded, one end of the second capacitor C2 is connected to one end of the first resistor R1, and the other end of the second capacitor C2 is connected to one end of the first resistor R1. grounded, one end of the third capacitor C3 is connected to one end of the first resistor R1, the other end of the third capacitor C3 is grounded, one end of the third resistor R3 is connected to one end of the first resistor R1, the other end of the third resistor R3 is connected to the positive electrode of the light-emitting diode, the negative electrode of the light-emitting diode is grounded, the EN pin of the first boost chip is connected to the vin pin of the first boost chip, the FB pin of the first boost chip is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to the GND pin of the first boost chip, the GND pin of the first boost chip is grounded, and the first boost chip The FB end of the chip is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the second voltage stabilizing integrated chip U2 and the first voltage stabilizing integrated chip; the input end of U3 is connected, and the second voltage stabilizing integrated chip U2 and the first voltage stabilizing integrated chip; the output end of U3 outputs the second target voltage, one end of the fourth capacitor C4 is connected to the other end of the fifth resistor R5, and the other end of the fourth capacitor C4 is grounded, one end of the fifth capacitor C5 is connected to the other end of the fifth resistor R5, and the other end of the fifth capacitor C5 is grounded, one end of the sixth capacitor C6 is connected to the second voltage stabilizing integrated chip U2 and the first voltage stabilizing integrated chip; The output end of U3 is connected, the other end of the sixth capacitor C6 is grounded, one end of the seventh capacitor C7 is connected to the output ends of the second voltage stabilizing integrated chip U2 and the first voltage stabilizing integrated chip U3, the other end of the seventh capacitor C7 is grounded, one end of the first inductor C1 is connected to the vin pin of the first boost chip, the other end of the first inductor C1 is connected to the SW pin of the first boost chip, the SW pin of the first boost chip is also connected to the positive electrode of the first Schottky diode D1, and the negative electrode of the first Schottky diode D1 is connected to the second voltage stabilizing integrated chip U2 and the first voltage stabilizing integrated chip;The input end of U3 is connected, one end of the eighth capacitor C8 is connected to the other end of the first inductor C1, the other end of the eighth capacitor C8 is connected to the negative electrode of the second Schottky diode D2, the positive electrode of the second Schottky diode D2 is connected to the input end of the first voltage stabilizing integrated chip, the positive electrode of the third Schottky diode D3 is connected to the other end of the eighth capacitor C8, the negative electrode of the third Schottky diode D3 is connected to the negative electrode of the fourth Schottky diode D4, the positive electrode of the fourth Schottky diode D4 is connected to the input end of the first voltage stabilizing integrated chip, the negative electrode of the second Schottky diode D2 is grounded, one end of the ninth capacitor C9 is connected to the positive electrode of the fourth Schottky diode D4, the other end of the ninth capacitor C9 is grounded, one end of the tenth capacitor C10 is connected to one end of the ninth capacitor C9, the other end of the tenth capacitor C10 is grounded, one end of the eleventh capacitor C11 is connected to the output end of the first voltage stabilizing integrated chip, the other end of the eleventh capacitor C11 is grounded, one end of the twelfth capacitor C12 is connected to the output end of the first voltage stabilizing integrated chip, and the other end of the twelfth capacitor C12 is grounded. ;

[0068] For example, a +5V voltage may be input into a power module, and through voltage boosting and voltage stabilization of the power module, multiple voltage outputs such as +5V, +15V, and +12V may be obtained.

[0069] As an example, see Figure 4 , Figure 4 FIG. 1 is a circuit diagram of a DAC chip DAC in an embodiment. The circuit of the DAC chip DAC includes: a DAC chip DAC and a sixth resistor R6.

[0070] Among them, the model of the DAC chip DAC can be DAC8568.

[0071] Specifically, one end of the sixth resistor R6 serves as the input end of the DAC chip DAC for receiving digital signals, the other end of the sixth resistor R6 is connected to the serial data input pin (DIN) of the DAC chip DAC, the multiple voltage output ends of the DAC chip DAC are respectively connected to the input end of an amplifier U4, and the feedback pin (VREF) of the DAC chip DAC is connected to the output end of the amplifier U4 to calibrate the output voltage.

[0072] As an example, taking DAC8568 as an example, the DAC chip DAC also includes the following multiple pins: SYNC (synchronization signal) pin: low level is valid, level trigger control. This input is the frame synchronization signal of the input data. When SYNC is low, the input shift register in the DAC is enabled, and data is sampled on all subsequent clock edges. After the 32nd clock, the DAC updates the output. If SYNC is set high for less than 32 clocks (that is, a SYNC rising edge occurs), the write sequence is ignored 1; LDAC (load DACs) pin, used to control the loading of the DAC, in asynchronous reset mode, the LDAC falling edge triggers data update 1; CLR (asynchronous reset) pin, used for asynchronous reset function 1; DIN (serial data input) pin, data is synchronized to the 32-bit input shift register at each falling edge of the serial clock input 1; SCLK (serial clock) pin, up to 50MHz, used to synchronize data input 1; AVDD (power input) pin, power input, voltage range is 2.7V to 5.5V, etc.

[0073] Here, those skilled in the art can set the connection of the pins that make the DAC chip work normally or are not related to the invention of the present application based on experience, and will not be elaborated here.

[0074] As an example, see Figure 5 , Figure 5 : is a circuit diagram of an amplifier U4 in an embodiment. The circuit of the amplifier U4 includes: an amplifier U4, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth capacitor C13, and a fourteenth capacitor C14.

[0075] Among them, one end of the eighth resistor R8 is connected to one end of the ninth resistor R9, the other end of the ninth resistor R9 is grounded, one end of the eighth resistor R8 is also connected to a voltage output end of the DAC chip DAC as the input end of the amplifier U4 circuit, the other end of the eighth resistor R8 is connected to the + input pin of the amplifier U4, one end of the tenth resistor R10 is grounded, the other end of the tenth resistor R10 is connected to one end of the eleventh resistor R11, the other end of the eleventh resistor R11 is connected to the feedback pin of the DAC chip DAC, the other end of the eleventh resistor R11 is also connected to the - input pin of the amplifier U4, and the The other end of the eleventh resistor R11 is also connected to one end of the eleventh resistor R11, the other end of the eleventh resistor R11 is connected to the output end of the amplifier U4, one end of the thirteenth capacitor C13 is connected to one end of the eleventh resistor R11, the other end of the thirteenth capacitor C13 is connected to the other end of the eleventh resistor R11, one end of the twelfth resistor R12 is connected to the output end of the amplifier U4, the other end of the twelfth resistor R12 serves as the output end of the amplifier U4 circuit to output the target power, one end of the fourteenth capacitor C14 is connected to the other end of the twelfth resistor R12, and the other end of the twelfth resistor R12 is grounded.

[0076] The power supply end of the amplifier U4 is respectively connected to the output end of the first voltage stabilizing integrated chip and the output end of the second voltage stabilizing integrated chip U2; U3.

[0077] In one embodiment of the present application, a high-precision voltage source array of four DAC8568 chips can be integrated on a PCB board. By integrating multiple DAC chips DAC, power amplifier U4, power module and filter capacitor on a PCB board, up to 32 independent channels of high-precision voltage output can be achieved. After each channel is amplified by amplifier U4, it can provide a power output of more than 300mW, thereby meeting the application requirements for high-precision, high-power, multi-channel voltage output.

[0078] Each DAC output channel is connected to an amplifier U4 to improve the driving capability of the output voltage. Amplifier U4 is designed to amplify the low-power signal output by the DAC to a voltage source that meets the power requirement of more than 300mW. By optimizing the gain and bandwidth control of amplifier U4, the amplified signal is ensured to maintain high accuracy and low distortion.

[0079] In order to ensure the stable power supply of the DAC chip DAC and the amplifier U4, a power module is integrated on the PCB to provide a stable power supply voltage. The power module is designed with multiple outputs to provide different voltage levels for the DAC chip DAC and the power amplifier U4 to ensure that they work in the best state. By adopting an efficient regulator circuit, the power supply noise and ripple are reduced to ensure the power supply stability of the system.

[0080] At the same time, appropriate filter capacitors are designed between the power module and the DAC and amplifier U4 to filter high-frequency noise in the power supply and reduce the impact of power supply fluctuations on the DAC output accuracy. The addition of filter capacitors helps to improve the system's anti-interference ability and ensure the purity and stability of the output voltage.

[0081] Specifically, in PCB design, the signal interference between channels can be minimized by optimizing the component layout and routing structure. The reasonable layout and signal shielding design of the DAC chip DAC, amplifier U4 and power module reduce the crosstalk between channels and ensure signal integrity. The ground wire design adopts a multi-point grounding method to reduce noise coupling and further improve the stability of the system. It should be understood that although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless clearly stated in this article, the execution of these steps is not strictly restricted in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the various embodiments described above may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0082] Based on the same inventive concept, the embodiment of the present application also provides a voltage source array for implementing the control method of the voltage source array involved above. The implementation solution provided by the voltage source array to solve the problem is similar to the implementation solution recorded in the above method, so the specific limitations in the voltage source array embodiment provided below can refer to the limitations of the control method of the voltage source array above, and will not be repeated here.

[0083] Based on the same inventive concept, the embodiment of the present application also provides a control device for a voltage source array for implementing the control method of the voltage source array involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific definition in the embodiment of the control device for the voltage source array provided below can refer to the definition of the control method of the voltage source array above, and will not be repeated here.

[0084] Please refer to Figure 6In an exemplary embodiment, a control device for a voltage source array is provided, including: an analog voltage output module 31 and a target power output module 32, the analog voltage output module 31 is used to control at least one DAC chip to convert a received digital signal into an analog voltage signal, and output the analog voltage through a target voltage output interface, the target power output module 32 is used to control the connection with a target amplifier corresponding to the target voltage output interface, amplify the analog voltage signal, so that the output end of the target amplifier outputs the target power.

[0085] Each module in the control device of the voltage source array can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0086] In an exemplary embodiment, a computer device is provided, which may be a terminal. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, the memory, and the input / output interface are connected via a system bus, and the communication interface, the display unit, and the input device are connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (NFC) or other technologies. When the computer program is executed by the processor, a control method for a voltage source array is implemented. The display unit of the computer device is used to form a visually visible picture, which may be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0087] Those skilled in the art will understand that Figure 7The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0088] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0089] Controlling at least one DAC chip to convert the received digital signal into an analog voltage signal, and outputting the analog voltage through a target voltage output interface;

[0090] The target amplifier corresponding to the target voltage output interface is controlled to be connected, and the analog voltage signal is amplified so that the output end of the target amplifier outputs the target power.

[0091] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0092] Controlling at least one DAC chip to convert the received digital signal into an analog voltage signal, and outputting the analog voltage through a target voltage output interface;

[0093] The target amplifier corresponding to the target voltage output interface is controlled to be connected, and the analog voltage signal is amplified so that the output end of the target amplifier outputs the target power.

[0094] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0095] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0096] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A control method for a voltage source array, characterized in that: Applied to a voltage source array circuit, the voltage source array circuit includes a plurality of DAC chips and a plurality of amplifiers, each DAC chip includes a digital signal input interface and a plurality of voltage output interfaces, and each voltage output interface is connected to an input end of an amplifier; Wherein, the method comprises: Controlling at least one DAC chip to convert the received digital signal into an analog voltage signal, and outputting the analog voltage through a target voltage output interface; The target amplifier corresponding to the target voltage output interface is controlled to be connected, and the analog voltage signal is amplified so that the output end of the target amplifier outputs the target power.

2. The control method according to claim 1, characterized in that: The at least one DAC chip further performs the following steps: Obtaining the amplified analog voltage signal; Determine whether the absolute value of the voltage difference between the amplified analog voltage signal and the target voltage signal is greater than a preset error value; If the absolute value of the voltage difference between the amplified analog voltage signal and the target voltage signal is greater than a preset error value, the analog voltage signal is calibrated according to the voltage difference between the amplified analog voltage signal and the target voltage signal until the absolute value of the voltage difference between the amplified analog voltage signal and the target voltage signal is less than or equal to the preset error value.

3. The control method according to claim 1, characterized in that: The target power is greater than 300 mW.

4. The control method according to claim 2, characterized in that: The amplified analog voltage signal is between -10V and 10V.

5. The control method according to claim 1, characterized in that: The digital signal output range of each DAC chip is 0-65535.

6. A voltage source array, characterized in that: The voltage source array includes a plurality of DAC chips and a plurality of amplifiers; Among them, each DAC chip includes a digital signal input interface and multiple voltage output interfaces, each voltage output interface is connected to the input end of an amplifier, the digital signal input interface of each DAC chip is a serial communication interface for receiving digital signals, and the output end of each amplifier is used to output the target power corresponding to the digital signal.

7. The voltage source array according to claim 6, characterized in that: The output end of each amplifier is also connected to a voltage feedback interface of a DAC chip corresponding to the amplifier to amplify the voltage output by the DAC chip.

8. The voltage source array according to claim 7, characterized in that: It also includes a power supply module, which is used to supply power to multiple DAC chips and multiple amplifiers.

9. The voltage source array according to claim 8, characterized in that: The voltage source array further includes a plurality of filter capacitor modules, and the plurality of filter capacitor modules are formed between the output end of the power module and the plurality of DAC chips and / or between the output end of the power module and the plurality of amplifiers.

10. The voltage source array according to claim 9, characterized in that: The multiple DAC chips, the power supply module, the multiple filter capacitor modules and the multiple amplifiers are integrated on a printed circuit board.

Images