Memory chip access control method and device, storage medium and electronic equipment

Abstract

The invention discloses a memory chip access control method and device, a storage medium and electronic equipment. Comprising the steps that first delay time for responding to an activation command when a memory chip conducts data access is obtained, and the first delay time is used for representing the time interval between sending of the activation command to the memory chip and responding of the activation command by the memory chip; second delay time for responding to a target command except the activation command when the memory chip performs data access is obtained, and the second delay time is used for representing a time interval between sending of the target command to the memory chip and response of the memory chip to the target command; a first target timing parameter of the memory chip is adjusted based on the first delay time and the second delay time, and the first target timing parameter is used for determining the target time for accessing the memory chip. The technical problem that the data read-write efficiency of an operating system is low due to the fact that the time of the activation command is not adjusted when the line address is checked through the activation command in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory chip access control method, device, storage medium and electronic device. Background Art

[0002] At present, the widely used Double Data Rate Synchronous Dynamic Random Access Memory (SDRAM, also known as Dynamic Random Access Memory, DRAM) standard is used for DDR4 (Double Date Rate, Double Data Rate) and DDR5 memory, and provides a channel that can support dual-line memory module (Dual In-line Memory Module, DIMM) devices on rising and falling clock edges. Generally, DDR5 DRAM supports failed row address repair. Two methods are provided in DDR5, namely Hard Post Package Repair (hPPR) for permanent row repair and Soft Post Package Repair (sPPR) for temporary row repair. With hPPR, DDR5 can correct at least one row address for each BG (Bank Group), while with sPPR, DDR5 can repair one row address for each BG, where if the hPPR resources of a BG are exhausted, the BG will have no more sPPR resources available.

[0003] Due to the high density of DDR5, some memory array units may lose their memory capacity during the entire life cycle of DIMM. For this reason, relevant technicians have developed a faulty row replacement technology for the Register Clock Driver (RCD) chip to improve production. This technology reserves some addresses as redundant addresses in each BG and never accesses these redundant addresses, and enables the RCD (Registering Clock Driver) to record and report the errors that occur in the DRAM chip in the RDIMM (Registered DIMM, dual in-line memory module with registers) or LRDIMM (Load Reduced DIMM, low load dual in-line memory module) , including the address of the faulty row and other related information. Every time an ACT command occurs, the RCD will look up its wrong row table and replace the redundant row addresses. If the operating system has a patrol routine that checks the memory capacity of each row address, once it detects that some rows have lost their memory capacity, it notifies the RCD to dynamically update the wrong row address table.

[0004] However, for DDR5, the above ACT command is a 2UI command, so RCD must receive two UIs to check the row address. Considering the search time for finding the row table, RCD must set a time number greater than or equal to 2 to affect all other commands, especially read and write commands, but doing so will reduce the efficiency of the entire DDR5 system.

[0005] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0006] The embodiments of the present application provide a memory chip access control method, device, storage medium and electronic device to at least solve the technical problem that when the related technology checks the row address through the activation command, the activation command time is not adjusted, resulting in low data reading and writing efficiency of the operating system.

[0007] According to one aspect of an embodiment of the present application, a memory chip access control method is provided, including: obtaining a first delay time for a memory chip to respond to an activation command when performing data access, wherein the first delay time is used to characterize the time interval between sending the activation command to the memory chip and the memory chip responding to the activation command; obtaining a second delay time for the memory chip to respond to a target command other than the activation command when performing data access, wherein the second delay time is used to characterize the time interval between sending the target command to the memory chip and the memory chip responding to the target command; adjusting a first target timing parameter of the memory chip based on the first delay time and the second delay time, wherein the first target timing parameter is used to determine the target time for accessing the memory chip.

[0008] Optionally, obtaining a first delay time for a memory chip to respond to an activation command when accessing data includes: obtaining a first time for a central processing unit to send an activation command to a memory chip on a dynamic random access memory DRAM module, and obtaining a second time for the memory chip to respond to the activation command, wherein the activation command is used to activate a target row within a target bank group on the memory chip; determining the first delay time for the activation command based on the first time and the second time.

[0009] Optionally, obtaining a second delay time when the memory chip responds to a target command other than an activation command when accessing data includes: measuring, by an adder, a second delay time when the memory chip responds to a target command other than an activation command when accessing data, wherein the target command includes at least one of the following: a read request command, a write request command, a refresh command, and a precharge command.

[0010] Optionally, the type of the adder includes at least one of the following: a carry select adder, a ripple carry adder, and a carry skip adder.

[0011] Optionally, the first target timing parameter includes at least one of the following: a first timing parameter for characterizing the time interval between sending a column read request command or a column write request command and a previous activation command, a second timing parameter for characterizing the time interval between selecting a row address through an activation command and executing a precharge command, a third timing parameter for characterizing the time interval between executing two activation commands on the same bank group, and a fourth timing parameter for characterizing the time interval between an activation command and a target command.

[0012] Optionally, the first target timing parameter is stored to the serial presence detect device and / or the serial presence detect hub device.

[0013] Optionally, after adjusting the first target timing parameter of the memory chip based on the first delay time and the second delay time, the method further includes: adjusting the second target timing parameter of the memory chip based on the first target timing parameter, wherein the second target timing parameter includes at least one of the following: a fifth timing parameter for characterizing the time interval for sending activation commands to different bank groups at the same logical level, a sixth timing parameter for characterizing the time interval for sending activation commands to the same bank groups at different logical levels, and a seventh interval time for characterizing the permission to send activation commands for more than 4 rows at the same time.

[0014] According to another aspect of an embodiment of the present application, a memory chip access control device is also provided, including: a first acquisition module, used to obtain a first delay time for the memory chip to respond to an activation command when performing data access, wherein the first delay time is used to characterize the time interval between sending the activation command to the memory chip and the memory chip responding to the activation command; a second acquisition module, used to obtain a second delay time for the memory chip to respond to a target command other than the activation command when performing data access, wherein the second delay time is used to characterize the time interval between sending the target command to the memory chip and the memory chip responding to the target command; an adjustment module, used to adjust a first target timing parameter of the memory chip based on the first delay time and the second delay time, wherein the first target timing parameter is used to determine the target time for accessing the memory chip.

[0015] In an embodiment of the present application, a first delay time of a memory chip responding to an activation command when performing data access is obtained, wherein the first delay time is used to characterize the time interval between sending an activation command to the memory chip and the memory chip responding to the activation command; a second delay time of a memory chip responding to a target command other than an activation command when performing data access is obtained, wherein the second delay time is used to characterize the time interval between sending a target command to the memory chip and the memory chip responding to the target command; a first target timing parameter of the memory chip is adjusted based on the first delay time and the second delay time, wherein the first target timing parameter is used to determine the target time for accessing the memory chip. By adjusting the timing parameters of the memory chip according to the difference between the delay time of the activation command and the delay time of other commands, the purpose of improving the stability and reliability of the memory chip reading and writing data is achieved, data transmission errors and interference are avoided, and the technical effect of improving system efficiency is achieved, thereby solving the technical problem that the related technology does not adjust the time of the activation command when checking the row address through the activation command, resulting in low data reading and writing efficiency of the operating system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 is a flow chart of an optional memory chip access control method according to an embodiment of the present application;

[0018] Figure 2a is a timing diagram of an optional timing parameter without dedicated ACR delay setting according to an embodiment of the present application;

[0019] Figure 2b is a timing diagram of an optional timing parameter for setting a dedicated ACR delay setting according to an embodiment of the present application;

[0020] Figure 3 is a schematic diagram of a computer system running a memory chip read and write operation control method according to an embodiment of the present application;

[0021] Figure 4 is a schematic diagram of a computer system running another memory chip read and write operation control method according to an embodiment of the present application;

[0022] Figure 5 is a schematic diagram of a computer system running another memory chip read and write operation control method according to an embodiment of the present application;

[0023] Figure 6 is a schematic structural diagram of an optional memory chip access control device according to an embodiment of the present application;

[0024] Figure 7 It is a hardware structure block diagram of a computer terminal (or mobile device) for implementing a memory chip read and write operation control method according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] In addition, the relevant information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for display, data for analysis, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. For example, an interface is set up between this system and the relevant user or organization. Before obtaining relevant information, it is necessary to send an acquisition request to the aforementioned user or organization through the interface, and obtain relevant information after receiving the consent information fed back by the aforementioned user or organization.

[0028] In order to better understand the embodiments of the present application, the technical terms involved in the embodiments of the present application are explained as follows:

[0029] Register Clock Driver (RCD): A circuit or chip that drives the clock signal in the register. Register clock drivers are commonly used in digital systems, especially in central processing units and other processors. RCD is responsible for providing clock signals to synchronize and control the read and write operations of registers. RCD usually has multiple clock input ports that can receive clock signals from different sources. RCD also provides multiple clock output ports for passing clock signals to registers that require clock signals. These output ports can be configured with different clock frequencies and phases as needed. In addition to providing clock signals, register clock drivers may also provide other functions such as clock division, clock delay, clock phase adjustment, etc. These functions can help optimize system performance and timing requirements. Register clock drivers play an important role in digital systems, ensuring the synchronization and correctness of register operations. Proper selection and configuration of register clock drivers is critical to designing high-performance and reliable digital systems.

[0030] High Bandwidth Register Clock Driver (HBRCD): A circuit used to drive a high-speed register clock signal. The register clock signal is used to synchronize the data input and output operations to the register, and the high-bandwidth register clock driver can provide a high-speed, stable clock signal. The high-bandwidth register clock driver usually includes one or more clock generators, clock dividers, and clock buffers. The clock generator is used to generate a high-frequency clock signal, and the clock divider is used to divide the high-frequency clock signal into a lower frequency to meet different application requirements. The clock buffer is used to amplify and drive the clock signal to ensure that the clock signal can be accurately transmitted to the register. The design of the high-bandwidth register clock driver takes into account factors such as signal transmission delay, jitter, and power consumption. HBRCD usually uses low-latency, low-jitter clock generators and buffers to ensure that the clock signal can be accurately transmitted to the register and can meet the requirements of high-speed data input and output. In addition, the high-bandwidth register clock driver can also reduce power consumption and improve performance by optimizing the circuit structure and adopting advanced process technology.

[0031] Multi-Register Clock Driver (MRCD): A circuit or chip used to drive the clock signal of multiple registers. MRCD is often used in synchronous circuits, such as register files in microprocessors or digital signal processors. The main function of a multi-register clock driver is to provide a synchronized clock signal to each register to ensure that they operate in the same clock cycle. MRCD usually has multiple clock inputs and multiple clock outputs, and can distribute one clock signal to multiple registers. Multi-register clock drivers usually have the following features: 1. Clock distribution: One input clock signal can be distributed to multiple registers to ensure that they operate in the same clock cycle; 2. Clock delay: An adjustable clock delay can be provided for each register to meet the timing requirements between different registers; 3. Clock frequency: It can support different clock frequencies and provide different clock divisions as needed; 4. Power supply noise filtering: It usually has a power supply noise filtering function to reduce noise interference of the clock signal.

[0032] DIMM (Dual In-Line Memory Module): A native 64-bit computer memory that enables fast data transfer and consists of a series of dynamic random access memory integrated circuits. DIMMs store each data bit in a separate storage cell. DIMMs use a 64-bit data path because the processors used in personal computers have a 64-bit data width, so DIMMs are commonly used in personal computers, workstations, printers, servers, etc.

[0033] RDIMM (Registered DIMM, dual in-line memory module with register): It adds a register to the memory stick for data transmission. It is located between the computer's central processing unit and memory particles to reduce the distance of parallel transmission.

[0034] According to an embodiment of the present application, an embodiment of a memory chip access control method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0035] Figure 1 is a flow chart of an optional memory chip access control method according to an embodiment of the present application, such as Figure 1 As shown, the method at least includes steps S102-S106, wherein:

[0036] Step S102, obtaining a first delay time of the memory chip responding to an activation command when performing data access.

[0037] The first delay time is used to represent the time interval between sending the activation command to the memory chip and the memory chip responding to the activation command.

[0038] In the technical solution provided in step S102, the above-mentioned memory chip refers to a storage unit for storing data in a DRAM module. The activation command is usually used to open a certain Row in a certain Bank before accessing (referring to read and write operations) data, and the above-mentioned Bank is a two-dimensional storage matrix, including Row and Column, and a single Bank has several rows and columns. In addition, the address signal sent simultaneously with the activation command can be used to determine the Bank Group, Bank, and Row to be activated. This step is called a row address strobe (RAS).

[0039] As an optional implementation, in the technical solution provided in the above step S102, the method may include: obtaining a first time when the central processing unit sends an activation command to a memory chip on a dynamic random access memory DRAM module, and obtaining a second time when the memory chip responds to the activation command, wherein the activation command is used to activate a target row in a target bank group on the memory chip; determining a first delay time of the activation command based on the first time and the second time.

[0040] Usually, in order to buffer the memory pressure of the central processing unit (CPU), the instructions or commands from the central processing unit CPU are usually sent to the RCD to stay for one clock cycle, and then the instructions or commands are transferred from the RCD to the memory chip at the rising edge of the next clock cycle to play a mediation role. The main purpose of doing this is to maintain the same memory speed even when the workload is large, ensuring the continuous stability of the system. Therefore, in an embodiment of the present application, the activation command from the central processing unit CPU is first received by the RCD, and then the RCD communicates with the memory chip on the dynamic random access memory DRAM module to transmit the activation command. Therefore, the first time when the central processing unit CPU sends the activation command to the memory chip on the dynamic random access memory DRAM module can be obtained first, and then the second time when the memory chip responds to the activation command can be obtained, and the first delay time of the activation command is determined according to the time difference between the first time and the second time.

[0041] Step S104, obtaining a second delay time of the memory chip responding to a target command other than an activation command when performing data access.

[0042] The second delay time is used to represent the time interval between sending the target command to the memory chip and the memory chip responding to the target command.

[0043] In the technical solution provided in step S104, after the memory chip responds to the activation command, the memory chip can obtain the read and write commands at this time, and the address signal sent synchronously with the read and write commands is used to determine the starting column address of the burst transmission. This step is called a column address strobe (CAS), so that a unit in the two-dimensional storage matrix is ​​selected by row access and column access in the Bank to read and write data. In addition, since a single Bank has only one SenseAmplifier (sense amplifier), it can only cache the contents of a single row. Therefore, after activating a row by the activation command, before accessing other different rows in the same Bank, it is necessary to use the Precharge command to close the current activated row, wherein the row address cached in the current Sense Amplifier will be written back to the original address after the Precharge command is issued. Compared with directly using the Precharge command to close a row, the relevant technology can also use the RDA (Read with Auto-Precharge, read and automatically precharge) command or the WDA (Write with Auto-Precharge, write and automatically precharge) command, so as to automatically close the current row after the current row of data transmission is completed. Therefore, the target commands in the embodiments of the present application include but are not limited to: a read request command, a write request command, a refresh command, a precharge command, a read and automatic precharge command, and a write and automatic precharge command.

[0044] Among them, the above-mentioned pre-charging can be understood as an operation on the current working row to prepare to open a new working row, so the operation is irregular, while the refresh is an operation performed on all rows at a fixed cycle to retain the data of the storage body that has not been rewritten.

[0045] As an optional implementation, in the technical solution provided in the above step S104, the method may include: measuring, by an adder, a second delay time of the memory chip responding to a target command other than an activation command when performing data access.

[0046] In this embodiment, the delay time of each target command is measured by different types of high-speed adders, wherein the high-speed adders used in the embodiments of the present application include but are not limited to carry selection adders, ripple carry adders, carry skip adders, etc. The selection of the specific adder type can be determined in combination with the actual application scenario, and no specific restrictions are made here.

[0047] It should be noted that the above-mentioned high-speed adders are all existing adders, and their design compositions are disclosed in the relevant technologies, so this part of the content will not be elaborated in this application.

[0048] Step S106: adjusting a first target timing parameter of the memory chip based on the first delay time and the second delay time, wherein the first target timing parameter is used to determine a target time for accessing the memory chip.

[0049] In the technical solution provided in step S106, the first target timing parameter includes at least one of the following: a first timing parameter for characterizing the time interval between sending a column read request command or a column write request command and a previous activation command, a second timing parameter for characterizing the time interval between selecting a row address through an activation command and executing a precharge command, a third timing parameter for characterizing the time interval between executing two activation commands on the same bank group, and a fourth timing parameter for characterizing the time interval between an activation command and a target command.

[0050] Specifically, the first timing parameter can be denoted as t RCD (i.e., RAS to CASDelay), which refers to the delay from RAS to CAS, where CAS and RAS jointly determine the addressing of the memory chip, and RAS (first activated after the access request) and CAS (activated after RAS is completed) are not continuous. There is a delay between these two operations. Therefore, this delay time can be recorded as the first timing parameter. The above second timing parameter can be recorded as t RAS (i.e. RAS Active Time), which refers to the shortest period from when the memory row is valid to when it is precharged. RAS If the waiting period is too long, the operating system will degrade performance due to meaningless waiting. RAS If the waiting period is too short, the activated row address will enter the inactive state earlier, resulting in insufficient time to complete the burst transmission of data. Therefore, the appropriate t RAS It plays a vital role in the performance of the operating system. The third timing parameter can be denoted as t RC (i.e. Row Cycle Time), which is the minimum time between two row activation commands to the same bank, or the time it takes to complete a row operation cycle in a bank. RC Too long will cause the operating system to reduce performance due to meaningless waiting; RC If t is too short, the new cycle will be initiated before the activated row is fully charged, resulting in data loss and corruption. RC It plays a vital role in the performance of the operating system. Finally, the fourth timing parameter can be understood as the timing information related to the timing between the activation command and other commands.

[0051] In order to facilitate the direct use of the above timing parameters, it is proposed in the embodiments of the present application that the first target timing parameters can also be stored in the serial presence detection device and / or the serial presence detection hub device.

[0052] Among them, Serial Presence Detect (SPD) is an 8-pin EEPROM (Electrically Erasable Programmable ROM) chip, which is used to record many important information of the memory, such as the memory chip and module manufacturer, operating frequency, operating voltage, speed, capacity, voltage and row and column address bandwidth and other parameters. Therefore, SPD information is generally written into the ROM chip by the memory module manufacturer according to the actual performance of the memory chip before leaving the factory.

[0053] Usually, after the computer starts, the motherboard BIOS (Basis Input Output System) will read the information in the SPD and automatically configure the corresponding memory working timing and control registers according to these parameter information, so as to give full play to the performance of the memory stick.

[0054] Furthermore, after adjusting the first target timing parameter of the memory chip, the second target timing parameter of the memory chip can also be adjusted based on the first target timing parameter, wherein the second target timing parameter includes at least one of the following: a fifth timing parameter for characterizing the time interval for sending activation commands to different bank groups at the same logical level, a sixth timing parameter for characterizing the time interval for sending activation commands to the same bank groups at different logical levels, and a seventh interval time for characterizing the permission to send activation commands for more than 4 rows at the same time.

[0055] Specifically, the fifth timing parameter can be denoted as t RRD_S (i.e., Row to Row Delay Short), which indicates the time interval between activation commands when issuing consecutive activation commands to banks of different Bank Groups. The sixth timing parameter can be denoted as t RRD_L (i.e., Row to Row Delay Long), which indicates the time interval between activation commands when issuing consecutive activation commands to multiple banks belonging to the same Bank Group. Finally, the fifth timing parameter can also be recorded as t FAW (i.e. Four Activate Window), which is limited to a window that can accommodate at most four activation commands. At most, four activation commands can be issued within a period of time. When sending activation commands continuously, the activation commands must meet the above t RRD_S and tRRD_L On the other hand, after sending four activation commands, you need to wait for t FAW The fifth activation command can only be sent after the end window.

[0056] It should be noted that the above method of the embodiment of the present application can be applied to at least one of a register clock driver, a high-bandwidth register clock driver or a multi-channel register clock driver.

[0057] For example, Figure 2a is a timing diagram of an optional timing parameter without a dedicated ACR delay setting according to an embodiment of the present application, Figure 2b is a timing diagram of an optional timing parameter for setting a dedicated ACR delay setting according to an embodiment of the present application, through Figure 2a and Figure 2b It is not difficult to find that Figure 2a The t between the host interface and the DRAM module interface RCD ,t RAS ,t RC The timing time is the same, and Figure 2b Medium RCD ,t RAS ,t RC The timing time is different, and assuming that the ACT delay is set to 2 and the normal delay is set to 1 in the embodiment of the present application, Figure 2b Medium RCD ,t RAS ,t RC Compared with the scheduled time Figure 2a The time of each timing parameter in the t is shorter than one cycle. In order to compensate for the influence of the dedicated ACT delay, the method of the embodiment of the present application should be used to adjust the t RCD ,t RAS ,t RC The timing time is increased accordingly to ensure the operating efficiency of the system.

[0058] Based on the scheme defined in the above steps S102 to S106, it can be known that in the embodiment, the first delay time of the memory chip responding to the activation command when performing data access is obtained, wherein the first delay time is used to characterize the time interval between sending the activation command to the memory chip and the memory chip responding to the activation command; the second delay time of the memory chip responding to the target command other than the activation command when performing data access is obtained, wherein the second delay time is used to characterize the time interval between sending the target command to the memory chip and the memory chip responding to the target command; the first target timing parameter of the memory chip is adjusted based on the first delay time and the second delay time, wherein the first target timing parameter is used to determine the target time for accessing the memory chip. By adjusting the timing parameters of the memory chip according to the difference between the delay time of the activation command and the delay time of other commands, the purpose of improving the stability and reliability of the memory chip reading and writing data is achieved, data transmission errors and interference are avoided, and the technical effect of improving system efficiency is achieved, thereby solving the technical problem that the related technology does not adjust the time of the activation command when checking the row address through the activation command, resulting in low data reading and writing efficiency of the operating system.

[0059] Figure 3 is a schematic diagram of a computer system running a memory chip read and write operation control method according to an embodiment of the present application, such as Figure 3 As shown, a computer system 960 includes: a host central processing unit (CPU) 970, a memory controller (MC) 980, and a sub-channel of a dual in-line memory module (DIMM) 300, wherein the DIMM can be a JEDEC standard DDR5. The DIMM includes two sub-channels. Each sub-channel includes 20 dynamic random access memory chips (DRAM) 341-345 and a host data bus 301-305. There is a registered clock driver (RCD) 330 in the DIMM, which will be shared by the two sub-channels. The command / address bus 320 connects the MC and the RCD. The serial presence detection EEPROM (SPD) or the serial presence detection EEPROM with a hub function (SPD_HUB) 350 stores DRAM timing information and can be accessed by the SMBUS.

[0060] Figure 4 is a schematic diagram of a computer system running another memory chip read and write operation control method according to an embodiment of the present application, such as Figure 4As shown, a computer system 930 includes: a host central processing unit (CPU) 940, a memory controller (MC) 950, and a sub-channel of a DIMM 200, wherein the DIMM can be a JEDEC standard DDR5 high-bandwidth DIMM (HighBandwidth DIMM, HBDIMM) or a hybrid DIMM defined in reference 8. The DIMM includes two sub-channels. Each sub-channel includes 20 or 18-DRAM chips 241-245, 5 high-bandwidth data buffers (High Bandwidth DataBuffer, HBDB) 211-215, a host data bus 201-205, and a data bus 221-225 between the HBDB and the DRAM chips. The bus 221-225 runs at half the data rate of the bus 201-205. There is a high-bandwidth register clock driver (High Bandwidth Register Clock Drive, HBRCD) 230 in the DIMM, which will be shared by two sub-channels. The command / address bus 220 connects the MC and the HBRCD. The Serial Presence Detect EEPROM (SPD) or Serial Presence Detect EEPROM and Hub function (SPD_HUB) 250 stores DRAM timing information and can be accessed by the SMBUS.

[0061] Figure 5 is a schematic diagram of a computer system running another memory chip read and write operation control method according to an embodiment of the present application, such as Figure 5 As shown, the computer system 900 includes: a host central processing unit (CPU) 910, a memory controller (MC) 920 and a sub-channel of a DDR5 multiple rank dual inline memory module (Multiple Rank Dual Inline Memory Module, MRDIMM) 100. The MRDIMM includes two sub-channels. Each sub-channel includes 20x4 DRAM chips 141-145, 5 multi-way data buffers (Multi Data Buffer, MDB) 111-115, a host data bus 101-105 and a data bus 121-125 between the MDB and the DRAM chips. The bus 121-125 runs at half the data rate of the bus 101-105. There is a multi-way registered clock driver (MRCD) 130 in the MRDIMM, which will be shared by two sub-channels. The serial presence detection EEPROM (SPD) or the serial presence detection EEPROM with the hub function (SPD_HUB) 150 stores the DRAM timing information and can be accessed by the SMBUS.

[0062] In addition, the present application also provides an embodiment of a memory chip access control device, which executes the memory chip access control method of the above embodiment when the device is running. Figure 6 is a schematic diagram of the structure of an optional memory chip access control device according to an embodiment of the present application, such as Figure 6 As shown, the memory chip access control device at least includes a first acquisition module 61, a second acquisition module 62 and an adjustment module 63, wherein:

[0063] A first acquisition module 61, used for acquiring a first delay time of the memory chip responding to an activation command when performing data access, wherein the first delay time is used for representing a time interval between sending an activation command to the memory chip and the memory chip responding to the activation command;

[0064] A second acquisition module 62, used for acquiring a second delay time of the memory chip responding to a target command other than an activation command when performing data access, wherein the second delay time is used to represent a time interval between sending the target command to the memory chip and the memory chip responding to the target command;

[0065] The adjustment module 63 is used to adjust a first target timing parameter of the memory chip based on the first delay time and the second delay time, wherein the first target timing parameter is used to determine a target time for accessing the memory chip.

[0066] It should be noted that the above Figure 6 The various modules in the memory chip access control device shown can be program modules (for example, a set of program instructions that implement a specific function) or hardware modules. For the latter, it can be expressed in the following forms, but is not limited to this: the expression form of each of the above modules is a processor, or the functions of each of the above modules are implemented by a processor.

[0067] Further, Figure 7 The hardware structure block diagram of a computer terminal (or mobile device) for implementing a method for controlling the read and write operations of a memory chip is shown. Figure 7 As shown, the computer terminal 70 (or mobile device 70) may include one or more (shown as 702a, 702b, ..., 702n in the figure) processors 702 (the processor 702 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 704 for storing data, and a transmission module 706 for communication functions. In addition, it may also include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the BUS bus), a network interface, a power supply and / or a camera. It can be understood by those skilled in the art that Figure 7The structure shown is only for illustration and does not limit the structure of the above electronic device. Figure 7 More or fewer components as shown, or with Figure 7 Different configurations shown.

[0068] It should be noted that the one or more processors 702 and / or other data processing circuits described above may generally be referred to herein as "data processing circuits". The data processing circuits may be embodied in whole or in part as software, hardware, firmware, or any other combination thereof. In addition, the data processing circuit may be a single independent processing module, or may be incorporated in whole or in part into any of the other components in the computer terminal 70 (or mobile device). As described in the embodiments of the present application, the data processing circuit acts as a processor control (e.g., selection of a variable resistor terminal path connected to an interface).

[0069] The memory 704 can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the memory chip read and write operation control method in the embodiment of the present application. The processor 702 executes various functional applications and data processing by running the software programs and modules stored in the memory 704, that is, realizing the above-mentioned memory chip read and write operation control method. The memory 704 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 704 may further include a memory remotely arranged relative to the processor 702, and these remote memories may be connected to the computer terminal 70 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0070] The transmission module 706 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the computer terminal 70. In one example, the transmission module 706 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission module 706 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0071] The display may be, for example, a touch screen liquid crystal display (LCD) that enables a user to interact with a user interface of the computer terminal 70 (or mobile device).

[0072] It should be noted that, in some optional embodiments, the above Figure 7The computer device (or electronic device) shown may include hardware elements (including circuits), software elements (including computer code stored on a computer-readable medium), or a combination of hardware elements and software elements. It should be noted that Figure 7 This is merely one example of a particular embodiment and is intended to illustrate the types of components that may be present in the above-described computer device (or electronic device).

[0073] It should be noted that Figure 7 The electronic device shown is used to perform Figure 1 The memory chip read and write operation control method shown in the figure, therefore the relevant explanations in the execution method of the above commands are also applicable to the electronic device and will not be repeated here.

[0074] According to an embodiment of the present application, a non-volatile storage medium is further provided, in which a program is stored, wherein when the program is running, the device where the non-volatile storage medium is located is controlled to execute the memory chip access control method in Example 1.

[0075] Optionally, the device where the non-volatile storage medium is located implements the following steps by running the program: obtaining a first delay time for the memory chip to respond to an activation command when performing data access, wherein the first delay time is used to characterize the time interval between sending the activation command to the memory chip and the memory chip responding to the activation command; obtaining a second delay time for the memory chip to respond to a target command other than the activation command when performing data access, wherein the second delay time is used to characterize the time interval between sending the target command to the memory chip and the memory chip responding to the target command; adjusting a first target timing parameter of the memory chip based on the first delay time and the second delay time, wherein the first target timing parameter is used to determine the target time for accessing the memory chip.

[0076] According to an embodiment of the present application, an electronic device is also provided, wherein the electronic device includes one or more processors; a memory for storing one or more programs, and when the one or more programs are executed by one or more processors, the one or more processors are implemented to run the programs, wherein the program is configured to execute the memory chip access control method in the above-mentioned embodiment 1 when running.

[0077] Optionally, the processor is configured to execute the following steps through a computer program: obtaining a first delay time for the memory chip to respond to an activation command when performing data access, wherein the first delay time is used to characterize the time interval between sending the activation command to the memory chip and the memory chip responding to the activation command; obtaining a second delay time for the memory chip to respond to a target command other than the activation command when performing data access, wherein the second delay time is used to characterize the time interval between sending the target command to the memory chip and the memory chip responding to the target command; adjusting a first target timing parameter of the memory chip based on the first delay time and the second delay time, wherein the first target timing parameter is used to determine the target time for accessing the memory chip.

[0078] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0079] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0080] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0081] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed over multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0082] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0083] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology or all or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of each embodiment method of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk, etc. Various media that can store program codes.

[0084] The above are only preferred implementations of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A memory chip access control method, characterized in that: include: Acquire a first delay time of the memory chip responding to an activation command when performing data access, wherein the first delay time is used to represent a time interval between sending the activation command to the memory chip and the memory chip responding to the activation command; Acquire a second delay time for the memory chip to respond to a target command other than the activation command when performing data access, wherein the second delay time is used to represent a time interval between sending the target command to the memory chip and the memory chip responding to the target command; A first target timing parameter of the memory chip is adjusted based on the first delay time and the second delay time, wherein the first target timing parameter is used to determine a target time for accessing the memory chip.

2. The method according to claim 1, characterized in that The first delay time of the memory chip in responding to the activation command when accessing data is obtained, including: Acquire a first time when a central processing unit sends an activation command to a memory chip on a dynamic random access memory DRAM module, and acquire a second time when the memory chip responds to the activation command, wherein the activation command is used to activate a target row in a target bank group on the memory chip; A first delay time of the activation command is determined based on the first time and the second time.

3. The method according to claim 1, characterized in that Acquiring a second delay time of the memory chip responding to a target command other than the activation command when accessing data, comprising: The second delay time of the memory chip responding to the target command other than the activation command when accessing data is measured by an adder, wherein the target command includes at least one of the following: a read request command, a write request command, a refresh command, and a precharge command.

4. The method according to claim 3, characterized in that The type of the adder includes at least one of the following: Carry select adder, ripple carry adder, carry skip adder.

5. The method according to claim 3, characterized in that: The first target timing parameter includes at least one of the following: a first timing parameter for characterizing the time interval between sending a column read request command or a column write request command and the previous activation command, a second timing parameter for characterizing the time interval between selecting a row address through the activation command and executing the precharge command, a third timing parameter for characterizing the time interval between executing two activation commands on the same bank group, and a fourth timing parameter for characterizing the time interval between the activation command and the target command.

6. The method according to claim 1, characterized in that The first target timing parameter is stored to a serial presence detect device and / or a serial presence detect hub device.

7. The method according to claim 1, characterized in that After adjusting a first target timing parameter of the memory chip based on the first delay time and the second delay time, the method further includes: Adjust the second target timing parameters of the memory chip based on the first target timing parameters, wherein the second target timing parameters include at least one of the following: a fifth timing parameter for characterizing the time interval for sending activation commands to different bank groups at the same logical level, a sixth timing parameter for characterizing the time interval for sending activation commands to the same bank groups at different logical levels, and a seventh interval time for characterizing the permission to send activation commands for more than 4 rows at the same time.

8. A memory chip access control device, characterized in that: include: A first acquisition module, used for acquiring a first delay time of the memory chip responding to an activation command when performing data access, wherein the first delay time is used for representing a time interval between sending the activation command to the memory chip and the memory chip responding to the activation command; A second acquisition module, used for acquiring a second delay time for the memory chip to respond to a target command other than the activation command when performing data access, wherein the second delay time is used to represent a time interval between sending the target command to the memory chip and the memory chip responding to the target command; An adjustment module is used to adjust a first target timing parameter of the memory chip based on the first delay time and the second delay time, wherein the first target timing parameter is used to determine a target time for accessing the memory chip.

9. A non-volatile storage medium, characterized in that: The non-volatile storage medium stores a computer program, wherein the device where the non-volatile storage medium is located executes the memory chip access control method according to any one of claims 1 to 7 by running the computer program.

10. An electronic device, characterized in that: include: A memory and a processor, wherein the processor is used to run a program stored in the memory, wherein the memory chip access control method according to any one of claims 1 to 7 is executed when the program is run.

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