High-speed processing system and method based on heterogeneous processing architecture

Abstract

The invention discloses a high-speed processing system and method based on a heterogeneous processing architecture, and relates to the technical field of computer data process.The system comprises an analyzer, a matching-operation pipeline and an inverse analyzer, and the matching-operation pipeline comprises a plurality of core modules; the core module comprises an input arbitration unit, a packet processing unit and an output cache unit which are connected through an AXI bus, the system can be seamlessly connected with the P4 program requirement of a user and final processing result feedback through cooperative work of the parser and the inverse parser, and the usability and compatibility of the system are improved. Through a polling processing mode of an input arbitration unit in the core module, precise operation of a packet processing unit based on configuration information and ordered output control of an output queue unit, processing delay of a data packet can be effectively reduced, network transmission efficiency can be improved, various complex P4 program processing logics can be flexibly handled, and the P4 program processing efficiency can be improved. And the method has high adaptability and expansibility.

Description

Technical Field

[0001] The present application relates to the field of computer data processing technology, and in particular to a high-speed processing system and method based on a heterogeneous processing architecture. Background Art

[0002] The growth of network traffic and increasingly complex network applications are driving the continuous development of new network architectures. The SDN architecture achieves programmability on the control plane due to its separation of the data plane and control plane, and programming the control plane through software to centralize the data plane, effectively solving the shortcomings of fixed functions of traditional network devices.

[0003] However, the programmability of existing SDN technology is currently limited to the control plane of the network. The forwarding protocols and packet forwarding processing logic that the data plane can support are still mainly determined by switch devices with fixed functions. The programmability of the data plane is still largely restricted by the packet processing hardware with fixed functions. Summary of the invention

[0004] The embodiments of the present application provide a high-speed processing system and method based on a heterogeneous processing architecture, which solves the defects of the prior art. The present application extends the programmability of the network to the data plane by deploying the P4 program on a specific hardware platform, thereby providing a new solution for fully programmable network devices.

[0005] In a first aspect, an embodiment of the present application provides a high-speed processing system based on a heterogeneous processing architecture, the system comprising: a parser, a match-operation pipeline and an inverse parser, the parser is used to compile a P4 program submitted by a user into configuration information in the match-operation pipeline; the match-operation pipeline is used to perform header matching on an input data packet based on the configuration information and perform an operation pipeline to obtain processed data; the inverse parser is used to reorganize the processed data and convert it into a P4 return data form to return it to the user;

[0006] Wherein, the match-operation pipeline includes a plurality of core modules, and the core modules include an input arbitration unit, a packet processing unit, and an output buffer unit connected via an AXI bus;

[0007] The input arbitration unit is used to process the input data packets in a polling manner, obtain valid message data and send it to the packet processing unit;

[0008] The packet processing unit is used to process the valid message data according to the configuration information, obtain the processed data packet and send it to the output queue unit;

[0009] The output queue unit is used to transfer the processed data packet to the output end through the AXI bus.

[0010] In an optional embodiment, the configuration information is configuration information of a data packet processing function defined by a user.

[0011] In an optional embodiment, the input port of each core module corresponds to a plurality of the core modules, and the input port includes: at least two network ports and at least one DMA interface, and both the network port and the DMA interface are connected to a matching-operation pipeline.

[0012] In an optional embodiment, the input arbitration unit includes:

[0013] The analysis subunit is used to obtain input data packets in a polling manner and analyze them to obtain address location information and target data; the address location information is the address information of the output port of the target information;

[0014] The processing subunit processes the target data based on the address location information to obtain valid message data.

[0015] In an optional embodiment, the packet processing unit includes:

[0016] A configuration subunit, configured to process the valid message data according to the configuration information to obtain a processed data packet;

[0017] A search subunit is used to search the routing table according to the specific address and destination address of the valid message data to obtain a search result.

[0018] The output subunit is used to generate corresponding output queue selection information based on the search result and send the search result to the output queue unit based on the output queue selection information.

[0019] In an optional embodiment, the output queue unit includes multiple output queues, each output queue is composed of a buffer and a read-write pointer, and is used to cache processed data packets and output them in a first-in-first-out order based on the search result.

[0020] According to a second aspect of the present embodiment, a high-speed processing method based on a heterogeneous processing architecture is provided. Based on the high-speed processing based on a heterogeneous processing architecture provided by the first aspect of the embodiment of the present application, the method includes:

[0021] Compile the P4 program submitted by the user to obtain the configuration information of the matching-operation pipeline;

[0022] Based on the configuration information, header matching is performed on the input data packet and the operation pipeline is executed to obtain processed data;

[0023] The processed data is reorganized and converted into P4 return data format and returned to the user.

[0024] In an optional embodiment, performing header matching on the input data packet based on the configuration information and executing the operation pipeline to obtain processed data includes:

[0025] The input data packets are processed in a polling manner to obtain valid message data;

[0026] The valid message data is processed according to the configuration information to obtain a processed data packet.

[0027] In an optional embodiment, the step of processing the input data packet in a polling manner to obtain valid message data includes:

[0028] The input data packet is acquired and analyzed by polling to obtain address location information and target data, wherein the address location information is the address information of the output port of the target information;

[0029] The target data is processed based on the address location information to obtain valid message data.

[0030] In an optional embodiment, the processing the valid message data according to the configuration information to obtain a processed data packet includes:

[0031] Processing the valid message data according to the configuration information to obtain a processed data packet;

[0032] According to the specific address and destination address of the valid message data, the routing table is searched to obtain the search result.

[0033] Generate corresponding output queue selection information based on the search result, and generate a processed data packet based on the search result.

[0034] The present application provides an optional high-speed processing system and method based on a heterogeneous processing architecture, the system includes: a parser, a matching-operation pipeline and an inverse parser, wherein the parser is used to compile the P4 program submitted by the user into the configuration information in the matching-operation pipeline; the matching-operation pipeline is used to perform header matching on the input data packet based on the configuration information and execute the operation pipeline to obtain the processed data; the inverse parser is used to reorganize the processed data and convert it into the P4 return data form and return it to the user; the matching-operation pipeline includes multiple core modules, and the core modules include an input arbitration unit, a packet processing unit and an output buffer unit connected through an AXI bus. The existence of the parser and the inverse parser proposed in the present invention enables the system to achieve a high degree of interactivity and compatibility with the user's P4 program, and the user can flexibly customize the data packet processing logic according to their own needs, accurately execute and feedback the results. Secondly, the core module design in the matching-operation pipeline, especially the close cooperation and fine division of labor between the input arbitration unit, the packet processing unit and the output queue unit, greatly improves the system's processing efficiency and accuracy of data packets. The polling analysis and processing mechanism of the input arbitration unit can effectively cope with the input of multi-source data packets. The flexible processing capability of the packet processing unit based on configuration information can meet various complex network processing requirements. The orderly caching and output control of the output queue unit ensure the stability and reliability of the system output.

[0035] In addition, the parallel processing capabilities of multiple core modules and the high-speed data transmission characteristics of the AXI bus enable the system to perform well in large-scale network data processing scenarios, effectively improving the performance and response speed of the entire network system, and providing strong technical support for the development of modern network technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0037] Figure 1 A schematic diagram of the structure of a high-speed processing system based on a heterogeneous processing architecture optionally provided in an embodiment of the present application;

[0038] Figure 2 A flowchart of a high-speed processing method based on a heterogeneous processing architecture is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0040] The prior art to which the present invention relates is briefly described below.

[0041] SDN (Software Defined Networking) is a new type of network architecture. Compared with the traditional network equipment architecture, its most important feature is that SDN separates the data plane from the control plane, centralizes the control plane and implements software programmability of the control plane, allowing network managers to dynamically control the behavior of the network through software programming, improving the flexibility of network management while reducing the complexity of development. In addition, SDN is scalable and allows users to control the behavior of network devices in the data plane on the control plane through programming interfaces, thereby realizing customized functions of various networks to meet different network application requirements. The above characteristics enable the SDN architecture to monitor the status of the entire network at any time, conveniently define network functions, and enable users to dynamically configure network processing logic on demand.

[0042] The Open Flow protocol is the most widely used protocol architecture in SDN technology. Open Flow uses flow tables and predefined actions to implement packet processing logic, and uses a set of standardized interfaces to provide the control plane with the ability to configure flow tables and actions. On the basis of SDN, Open Flow integrates the control plane of the network into a centralized controller. After the controller obtains the policy logic of the advanced network range, it compiles these policies through the abstract configuration capabilities provided by the data plane, and finally configures them to each data plane device by issuing flow tables to control and manage the packet forwarding behavior of the underlying switching devices, thus realizing the centralized control of all underlying switching devices in the network. The data plane is composed of switches and routers, and its main function is to implement data packet processing according to the flow table rules sent by the controller. The devices on the data plane only obtain these policies from the control plane through the interface, and do not need to specifically implement the packet forwarding logic. OpenFlow formally promotes the separation of the data plane and the control plane, making the data plane develop in the direction of high programmability and easy reconfiguration. The architecture of separating the data plane and the control plane used by it greatly enhances the programmability of the network.

[0043] However, the programmability of existing SDN technology is limited to the control plane of the network. The forwarding protocols and packet forwarding processing logic that the data plane can support are still mainly determined by switch devices with fixed functions. The programmability of the data plane is largely restricted by the packet processing hardware with fixed functions.

[0044] The P4 language has the characteristic of being protocol-independent in the data plane, which enables programmability in the data plane. Unlike SDN, which mainly programs the control plane, the P4 language is designed to program the data plane or to partially define the interface between the control plane and the data plane, and cannot be used to define the functions of the control plane. The SDN solution combined with the P4 solution enables network devices to fully program the packet processing process, which has very important application value and broad application background research in improving network service capabilities and enhancing user experience.

[0045] However, the programmability of existing SDN technology is limited to the control plane of the network. The forwarding protocols and packet forwarding processing logic that the data plane can support are still mainly determined by the switch devices with fixed functions. The programmability of the data plane is still largely restricted by the packet processing hardware with fixed functions. Therefore, this application proposes a high-speed processing system based on a heterogeneous processing architecture to address this situation.

[0046] Figure 1 FIG. 1 is a schematic diagram of an optional high-speed processing system based on a heterogeneous processing architecture according to an embodiment of the present application. Figure 1 As shown, the system includes: a parser, a match-operation pipeline and an inverse parser, wherein the parser is used to compile the P4 program submitted by the user into the configuration information in the match-operation pipeline; the match-operation pipeline is used to perform header matching on the input data packet based on the configuration information and perform the operation pipeline to obtain processed data; the inverse parser is used to reorganize the processed data and convert it into the P4 return data form and return it to the user;

[0047] The match-operation pipeline includes a plurality of core modules, wherein the core modules include an input arbitration unit, a packet processing unit, and an output buffer unit connected via an AXI bus;

[0048] An input arbitration unit, used to process input data packets in a polling manner, obtain valid message data and send it to the packet processing unit;

[0049] The packet processing unit is used to process the valid message data according to the configuration information, obtain the processed data packet and send it to the output queue unit;

[0050] The output queue unit is used to transfer the processed data packets to the output end through the AXI bus.

[0051] Specifically, the parser undertakes the key task of compiling the P4 program submitted by the user into the configuration information in the match-operation pipeline. For example, when the user enters a specific P4 program code, which describes a series of processing rules and logic for the data packet, the parser will deeply parse and compile it. It will identify the header field definition, matching condition settings, and corresponding operation instructions in the P4 program, and convert this information into a configuration information format that the match-operation pipeline can understand and execute. Among them, the configuration information is the configuration information of the data packet processing function defined by the user.

[0052] The matching-operation pipeline includes multiple core modules, each of which is connected to an input arbitration unit, a packet processing unit, and an output buffer unit through an AXI bus.

[0053] The input arbitration unit processes input data packets in a polling manner. Assuming that the system receives data packet streams from multiple different sources, the input arbitration unit will check each data packet in turn according to the established polling order. For example, in an input stream containing data packets A, B, and C, it first checks data packet A to determine whether it is valid message data. If data packet A is in the correct format, the data is complete, and meets the preliminary receiving conditions set by the system, it is determined to be valid message data and sent to the packet processing unit. Then, data packets B and C are processed in the same polling manner to ensure that each data packet has the opportunity to be processed in a timely manner, avoiding processing delays caused by a data packet waiting for a long time.

[0054] The packet processing unit processes valid message data according to the configuration information generated by the parser. Taking a network packet processing scenario as an example, the configuration information specifies the matching rules for specific header fields (such as source IP address, destination IP address, port number, etc.) and corresponding operations (such as modifying certain fields of the header, forwarding the data packet to a specific port, etc.). When the packet processing unit receives valid message data from the input arbitration unit, it will accurately match the header of the data packet according to the matching rules in the configuration information. If the source IP address of the data packet meets the matching conditions in a certain range, the packet processing unit will perform the corresponding operation, such as modifying the destination port number of the data packet to a new value, thereby obtaining the processed data packet and sending it to the output queue unit.

[0055] The output queue unit is mainly responsible for transmitting the processed data packets to the output end through the AXI bus. The output queue unit will temporarily cache and sort the processed data packets to ensure that the data packets are transmitted to the output end in the correct order. For example, in a high-traffic data center network, multiple core modules process a large number of data packets at the same time. The output queue unit can coordinate the output order of these data packets to avoid data confusion and conflicts, and ensure the output stability and reliability of the entire system.

[0056] The inverse parser is responsible for reorganizing the message data processed by the match-operation pipeline and converting it into P4 return data and returning it to the user. After the data packet has undergone a series of complex processing, its data structure and content may have changed significantly. The inverse parser will reorganize the processed data packet into a form that conforms to the P4 program output specification based on pre-set rules and data format requirements. For example, if the header of the data packet is modified or some additional processing information is added in the match-operation pipeline, the inverse parser will extract this key information and integrate it into the P4 return data so that the user can clearly understand the processing process and results of the data packet, which is convenient for the user to monitor and analyze the operating status of the system.

[0057] Through the detailed description of the above embodiments, it can be clearly seen that the high-speed processing system based on the heterogeneous processing architecture has many advantages. First, the collaborative work of the parser and the inverse parser enables the system to seamlessly connect the user's P4 program requirements with the final processing result feedback, improving the ease of use and compatibility of the system. Secondly, the core module design in the matching-operation pipeline, especially the polling processing method of the input arbitration unit, the precise operation of the packet processing unit based on the configuration information, and the orderly output control of the output queue unit, greatly improves the system's processing speed and processing accuracy for data packets. In large-scale network data processing scenarios, it can effectively reduce the processing delay of data packets, improve network transmission efficiency, and can flexibly respond to various complex P4 program processing logics, with strong adaptability and scalability.

[0058] Based on the contents in the above embodiments, as an optional embodiment, the input port of each core module in the high-speed processing system based on the heterogeneous processing architecture provided by the present invention corresponds to multiple core modules, and the input port includes: at least two network ports and at least one DMA interface, and the network port and the DMA interface are both connected to the matching-operation pipeline.

[0059] Based on the contents in the above embodiments, as an optional embodiment, the input arbitration unit in the high-speed processing system based on the heterogeneous processing architecture provided by the present invention includes:

[0060] The analysis subunit is used to obtain input data packets in a polling manner and analyze them to obtain address location information and target data; the address location information is the address information of the output port of the target information;

[0061] The processing subunit processes the target data based on the address location information to obtain valid message data.

[0062] Specifically, when multiple data sources input data packets to the system at the same time, the analysis subunit obtains the input data packets in turn in a polling manner. For example, in a data center network, data packets may be transmitted from different network ports or through a DMA interface. The analysis subunit will perform a detailed analysis of the acquired data packets to determine the output port address information (address location information) of its target information and the target data in the data packet. For example, for a network traffic monitoring system, the analysis subunit will identify key information such as the source IP address and destination IP address in the data packet, and determine which subsequent processing link or output port these data packets should be directed to.

[0063] After obtaining the address location information, the processing subunit further processes the target data according to the information to extract valid message data. For example, if the format of the data packet meets the system's pre-set standards and the data integrity is confirmed, the processing subunit will organize it into valid message data and send it to the packet processing unit. During the processing, the processing subunit may also perform some preliminary verification and preprocessing operations on the data packet, such as checking whether the checksum of the data packet is correct, removing redundant information in the data packet, etc., to improve the efficiency and accuracy of subsequent processing.

[0064] Based on the contents in the above embodiments, as an optional embodiment, the packet processing unit in the high-speed processing system based on the heterogeneous processing architecture provided by the present invention includes:

[0065] A configuration subunit, configured to process the valid message data according to the configuration information to obtain a processed data packet;

[0066] A search subunit is used to search the routing table according to the specific address and destination address of the valid message data to obtain a search result.

[0067] The output subunit is used to generate corresponding output queue selection information based on the search result and send the search result to the output queue unit based on the output queue selection information.

[0068] Specifically, the valid message data is processed according to the configuration information generated by the parser. After receiving the valid message data, the configuration subunit will check whether the source IP address of the data packet is within the interception range. If so, the data packet will be intercepted accordingly, such as marking it as an illegal data packet and recording relevant information; if not, the corresponding configuration operation will be performed according to the user-defined data packet processing function to generate a processed data packet.

[0069] In order to determine the forwarding path of the data packet, the search subunit will search the routing table according to the specific address and destination address of the valid message data. The routing table records the connection relationship and forwarding rules between different network segments. The search subunit will search the routing table for an entry that matches the destination address of the data packet and obtain the search result. This search result will determine which output queue unit the data packet should be sent to next.

[0070] The corresponding output queue selection information is generated based on the search results, and the search results are sent to the output queue unit. For example, if the search results indicate that the data packet should be forwarded to a specific area in the network, the output subunit will select the corresponding output queue and send the data packet and related information to the queue for subsequent output operations.

[0071] Based on the contents in the above embodiments, as an optional embodiment, in the high-speed processing system based on the heterogeneous processing architecture provided by the present invention, the output queue unit includes multiple output queues, each output queue is composed of a buffer and a read-write pointer, which is used to cache processed data packets and output them in a first-in-first-out order based on the search results.

[0072] Specifically, the output queue unit contains multiple output queues, each of which consists of a buffer and a read-write pointer. When the processed data packet is sent to the output queue unit, it will be cached in the corresponding output queue buffer according to the search result. For example, in a network traffic load balancing system, different types of data packets (such as video traffic, voice traffic, data traffic, etc.) will be assigned to different output queues. These output queues are output in a first-in-first-out order, and the read-write pointer is used to accurately control the read and write operations of the data packet to ensure that the data packet can be sent out from the output end in an orderly manner to avoid data confusion and conflict.

[0073] In summary, the existence of the parser and the reverse parser enables the system to achieve a high degree of interactivity and compatibility with the user's P4 program. The user can flexibly customize the data packet processing logic according to their own needs, and the system can accurately execute and feedback the results. Secondly, the core module design in the matching-operation pipeline, especially the close cooperation and fine division of labor between the input arbitration unit, the packet processing unit and the output queue unit, greatly improves the system's processing efficiency and accuracy of data packets. The polling analysis and processing mechanism of the input arbitration unit can effectively cope with multi-source data packet input, the flexible processing capability of the packet processing unit based on configuration information can meet various complex network processing requirements, and the orderly cache and output control of the output queue unit ensure the stability and reliability of the system output. In addition, the parallel processing capability of multiple core modules and the high-speed data transmission characteristics of the AXI bus enable the system to perform well in large-scale network data processing scenarios, effectively improve the performance and response speed of the entire network system, and provide strong technical support for the development of modern network technology.

[0074] The present invention will be described below with reference to a specific embodiment.

[0075] The invention provides a high-speed processing system based on a heterogeneous processing architecture, comprising a parser, a match-operation pipeline and an inverse parser. The parser is used to compile a P4 program submitted by a user into configuration information in the match-operation pipeline; the match-operation pipeline is used to perform header matching on an input data packet based on the configuration information and to perform operation pipeline execution to obtain processed data; the inverse parser is used to reorganize the processed data and convert it into a P4 return data form to return it to the user.

[0076] Specifically, the hardware system design part uses the IP integrated design tool provided by the Vivado integrated development environment. In the IP integrator, some IP cores provided in the Xilinx IP library can be called and configured, and the HDL source code developed by yourself can be packaged as an IP core and placed in the IP Catalog as a custom packaged IP. The system design can be completed by adding the IP core required for the system design in the IP integrated design interface and connecting it to the corresponding interface. After the system design is completed, the completed design needs to be synthesized into a netlist, layout and routing, and constraint files are added. Finally, the bitstream file for configuring the FPGA can be generated.

[0077] The parser designed in P4 language uses 256 bits as the width of the data path, 128 bits as the width of the metadata, and the system uses a system frequency of 200Mhz. The theoretical throughput of the data processing module is 256 bits × 200Mhz, that is, 51.2Gbps, which can theoretically meet the goal of achieving an overall system throughput of 40Gbps on 4 10Gbps Ethernet ports proposed by the present invention. Although the theoretical maximum rate cannot be directly converted into actual system performance. However, through appropriate pipeline optimization measures, the control flow, matching table and operation engine adopt a pipeline structure, which can improve the performance of the system to a certain extent.

[0078] The clock in the data path is provided by the clock module, and its frequency is set to 200MHZ. The received header data bit width is the bit width of the AXI bus, which is 256 bits. In addition to the header data, each module uses the TUSER signal in the AXI-Stream bus to carry up to 128 bits of metadata sume_metadata to transmit information between modules.

[0079] In the data processing plane, data packets enter from four network ports, and the receiving end assigns input information to the TUSER signal according to the different input ports of these data packets. The input arbitration unit processes the input data packets in the FIFO queue and transmits the valid header data in the FIFO queue to the packet processing unit.

[0080] The packet processing unit processes the data packet according to the user-defined data packet processing function. The processed data packet is transmitted to the output queue unit cache. After receiving the transmitted data, the output queue unit transmits the data packet to be output to the FIFO cache of the output end through the AXI bus, and finally outputs it from the circuit through the output end.

[0081] The following is an introduction to the functions of each module in the system:

[0082] In this embodiment, four SFP 10Gb / s ports are used to receive data. Theoretically, a transmission rate of 40Gb / s can be achieved. The receiving end RX consists of four interfaces responsible for receiving network data transmitted by the network port and a DMA interface responsible for receiving host data. Each of the five ports has a cache FIFO, which buffers the received data packets and sends them to the next module.

[0083] Since there are only two SFP+ fiber optic interfaces on the AXKU041 development board, in this embodiment, an Alinx FMC to four-way SFP fiber optic module is used to expand the AXKU041 development board to four available network ports. This module can expand the SFP, where each SFP is connected to the transceiver pins by a group of TX and a group of RX, and can support a data transmission rate of 10Gb / s.

[0084] The input arbitration unit processes the data packets and selects the output port in a polling manner, and finally outputs the data packets transmitted from the four network ports to the next circuit module for processing in turn.

[0085] The packet processing unit is compiled by the P4_SDNet tool developed by Xilinx according to the specific P4 application. Its function is to implement the data packet forwarding function according to the preset algorithm, and it is the core module of the system. In actual use, the data plane defined by P4 is compiled into an HDL module with a standard AXI bus interface and loaded into the system to realize the function of the P4 application.

[0086] The output queue unit is responsible for caching the data packets processed by the previous module into different output queue buffers according to the destination port in the packet header and sending them.

[0087] The transmitting end TX takes out the data that has been processed by the previous module and sends it to the corresponding port.

[0088] The following is a detailed analysis of some modules.

[0089] 1) Input arbitration unit

[0090] The receiving module composed of MAC RX0 to MAC RX3 and DMA RX converts the data packets obtained from the network port and the DMA module of the computer into 256-bit AXI4-Stream data streams and sends them to the input arbitration unit.

[0091] The output interface of the arbitration module uses 4 AXI_Stream buses to receive input data packets from 4 network ports, and at the same time receives data packets from the computer through 1 AXI_Stream bus from the DMA channel. After entering the arbitration module, the AXIS_Stream streams output by each Ethernet controller are first cached into their respective FIFO queues, and then polled and retrieved the valid header data in each queue in turn through a loop.

[0092] 2) Packet processing unit

[0093] The packet processing unit is compiled from the P4 program into HDL source code, and its function is to implement the user-defined data plane function. The implementation of this part requires setting the P4-SDNet compilation parameters according to the actual hardware resources. Similar to the input arbitration unit, the input and output of this module are connected by the AXI4-Stream bus, which has a bit width of 256 bits and is responsible for receiving the data packets and DMA channel data passed in by the input arbitration unit.

[0094] After completing the design of the P4 source code, you can compile the P4 code into an HDL file through P4-SDNet. The compilation first compiles the P4 file into a PX file, and then compiles the PX file into an HDL file.

[0095] This command can specify the input and output type of the generated module and the bus width and other information. After successful compilation, the generated HDL code is packaged as an IP core and can be used in the Vivado tool.

[0096] The HDL program is packaged by running the tcl script file, and the packaged IP core is added to the Vivado IP library for use.

[0097] 3) Output queue unit

[0098] The clock of the output queue unit is designed to be 200Mhz, and the data width is 256bit. This unit receives the signal from the packet processing unit, and then caches the processed data packets generated by the packet processing unit to the corresponding output queue according to the output port of the processed data packet, and finally transmits it to the sending module including MAC TX0 to MAC TX3 and DMA TX. The sending module converts the 256-bit AXI4-Stream data stream into an Ethernet data packet and sends it to the network port and the DMA module of the computer. Among them, in addition to the parameters of the data packet itself, the sume_metadata passed from the previous module to this module also contains relevant information about the corresponding data packet processing, which can be used as a basis for judging the execution of the corresponding data packet processing operation.

[0099] Based on the same inventive concept, an embodiment of the present application provides a high-speed processing method based on a heterogeneous processing architecture. Figure 2 , Figure 2 : is a flowchart of a high-speed processing method based on a heterogeneous processing architecture proposed in an embodiment of the present application. Based on the high-speed processing implementation based on the heterogeneous processing architecture provided in the first aspect of the embodiment of the present application, the method includes:

[0100] S102: Compile the P4 program submitted by the user to obtain configuration information of the matching-operation pipeline;

[0101] S104: performing header matching on the input data packet based on the configuration information and executing the operation pipeline to obtain processed data;

[0102] S106: The processed data is reorganized and converted into P4 return data format and returned to the user.

[0103] Further, performing header matching on the input data packet based on the configuration information and executing the operation pipeline to obtain processed data includes:

[0104] The input data packets are processed in a polling manner to obtain valid message data;

[0105] The valid message data is processed according to the configuration information to obtain a processed data packet.

[0106] Further, the process of processing the input data packet in a polling manner to obtain valid message data includes:

[0107] The input data packet is acquired and analyzed by polling to obtain address location information and target data, wherein the address location information is the address information of the output port of the target information;

[0108] The target data is processed based on the address location information to obtain valid message data.

[0109] Further, the processing of the valid message data according to the configuration information to obtain a processed data packet includes:

[0110] Processing the valid message data according to the configuration information to obtain a processed data packet;

[0111] According to the specific address and destination address of the valid message data, the routing table is searched to obtain the search result.

[0112] Generate corresponding output queue selection information based on the search result, and generate a processed data packet based on the search result.

[0113] It should be noted that the high-speed processing method of the heterogeneous processing architecture provided in the embodiment of the present invention, during specific operation, is implemented based on the high-speed processing based on the heterogeneous processing architecture provided in the first aspect of the embodiment of the present application, which is not elaborated in this embodiment.

[0114] In specific implementation, the above modules can be implemented as independent entities, or can be arbitrarily combined and implemented as the same or several entities. The specific implementation of the above modules can be found in the previous method embodiments, which will not be repeated here.

[0115] Those skilled in the art will appreciate that all or part of the steps in the various methods of the above embodiments can be completed by instructions, or by controlling related hardware through instructions, and the instructions can be stored in a computer-readable storage medium and loaded and executed by a processor. To this end, an embodiment of the present invention provides a storage medium in which a plurality of instructions are stored, and the instructions can be loaded by a processor to execute the steps of any embodiment of the file processing method provided in the embodiment of the present invention.

[0116] The computer-readable storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0117] Since the instructions stored in the storage medium can execute the steps in any embodiment of the file processing method provided in the embodiments of the present invention, the beneficial effects that can be achieved by any file processing method provided in the embodiments of the present invention can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0118] The above is a detailed introduction to a file processing method, device, storage medium and electronic device provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A high-speed processing system based on a heterogeneous processing architecture, characterized in that: include: A parser, a match-operation pipeline, and an inverse parser, wherein the parser is used to compile the P4 program submitted by the user into configuration information in the match-operation pipeline; The match-operation pipeline is used to perform header matching on the input data packet based on the configuration information and perform the operation pipeline to obtain processed data; the inverse parser is used to reorganize the processed data and convert it into a P4 return data form to return it to the user; Wherein, the match-operation pipeline includes a plurality of core modules, and the core modules include an input arbitration unit, a packet processing unit, and an output buffer unit connected via an AXI bus; The input arbitration unit is used to process the input data packets in a polling manner, obtain valid message data and send it to the packet processing unit; The packet processing unit is used to process the valid message data according to the configuration information, obtain the processed data packet and send it to the output queue unit; The output queue unit is used to transfer the processed data packet to the output end through the AXI bus.

2. The high-speed processing system based on heterogeneous processing architecture according to claim 1, characterized in that: The configuration information is configuration information of a data packet processing function defined by a user.

3. The high-speed processing system based on heterogeneous processing architecture according to claim 2, characterized in that: The input port of each core module corresponds to the plurality of core modules, and the input port includes: at least two network ports and at least one DMA interface, and both the network port and the DMA interface are connected to the matching-operation pipeline.

4. The high-speed processing system based on heterogeneous processing architecture according to claim 3, characterized in that: The input arbitration unit comprises: The analysis subunit is used to obtain input data packets in a polling manner and analyze them to obtain address location information and target data; the address location information is the address information of the output port of the target information; The processing subunit processes the target data based on the address location information to obtain valid message data.

5. The high-speed processing system based on heterogeneous processing architecture according to claim 1, characterized in that: The packet processing unit includes: A configuration subunit, configured to process the valid message data according to the configuration information to obtain a processed data packet; A search subunit is used to search the routing table according to the specific address and destination address of the valid message data to obtain a search result. The output subunit is used to generate corresponding output queue selection information based on the search result and send the search result to the output queue unit based on the output queue selection information.

6. The high-speed processing system based on heterogeneous processing architecture according to claim 5, characterized in that: The output queue unit includes a plurality of output queues, each of which is composed of a buffer and a read-write pointer, and is used to cache processed data packets and output them in a first-in-first-out order based on the search result.

7. A high-speed processing method based on a heterogeneous processing architecture, the method being implemented based on the system of any one of claim 16, comprising: Compile the P4 program submitted by the user to obtain the configuration information of the matching-operation pipeline; Based on the configuration information, header matching is performed on the input data packet and the operation pipeline is executed to obtain processed data; The processed data is reorganized and converted into P4 return data format and returned to the user.

8. The high-speed processing method based on heterogeneous processing architecture according to claim 7, characterized in that: The step of performing header matching on the input data packet based on the configuration information and executing the operation pipeline to obtain processed data includes: The input data packets are processed in a polling manner to obtain valid message data; The valid message data is processed according to the configuration information to obtain a processed data packet.

9. The high-speed processing method based on heterogeneous processing architecture according to claim 8, characterized in that: The method of processing the input data packet in a polling manner to obtain valid message data includes: The input data packet is acquired and analyzed by polling to obtain address location information and target data, wherein the address location information is the address information of the output port of the target information; The target data is processed based on the address location information to obtain valid message data.

10. The high-speed processing method based on heterogeneous processing architecture according to claim 8, characterized in that: The processing of the valid message data according to the configuration information to obtain a processed data packet includes: Processing the valid message data according to the configuration information to obtain a processed data packet; According to the specific address and destination address of the valid message data, the routing table is searched to obtain the search result. Generate corresponding output queue selection information based on the search result, and generate a processed data packet based on the search result.

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