DDR (Double Data Rate) controller exception handling method and device and storage medium

Abstract

The invention discloses a DDR (Double Data Rate) controller exception handling method, relates to the technical field of DDR controllers, and aims to improve the stability and reliability of a DDR controller and reduce system crash and data loss caused by exceptions. Through a dynamic adjustment strategy and an error recovery mechanism, high data read-write efficiency and accuracy can still be kept under abnormal conditions.

Description

Technical Field

[0001] The present invention relates to the technical field of DDR controllers, and in particular to a method for handling DDR controller exceptions. Background Art

[0002] As the core component of embedded system storage management, DDR controller accurately regulates the data flow between CPU and DDRSDRAM to ensure efficient data reading and writing and smooth operation of the system. However, in the actual complex operating environment, DDR controller will also face many challenges, such as abnormal conditions such as read and write errors and timing mismatch caused by factors such as voltage fluctuations, signal interference, and temperature changes. Once these problems break out, they will directly threaten the integrity of stored data and the stability of system operation. Especially in embedded systems with extremely high stability requirements, SDRAM, as the core storage medium for programs and data, is likely to trigger abnormal behavior of MCU, such as program runaway, system stuck, etc., once encountering read and write errors, which will cause the entire system to crash. Therefore, building a comprehensive and efficient DDR controller exception handling process is not only responsible for data security, but also an important guarantee for the stable operation of embedded systems. This process should cover multiple links such as rapid diagnosis, intelligent decision-making and recovery, and logging to ensure that the exception can be accurately captured and effectively handled as soon as it occurs, thereby minimizing the occurrence of system failures and improving the reliability and user experience of the overall system. Summary of the invention

[0003] In order to overcome the deficiencies of the above technologies, the present invention provides an exception handling method for improving the stability and reliability of a DDR controller.

[0004] The technical solution adopted by the present invention to overcome the technical problems is: A DDR controller exception processing method, comprising: S1.MCU starts and sends commands to read data to the DDR controller as required; S2. After receiving the command to read data from the MCU, the DDR controller parses and executes the command to read data; S3. The abnormality detection module detects whether the DDR controller receives an abnormal command sent by the MCU to read the data. If so, step S6 is executed, and if not, step S4 is executed; S4. DRAM receives the command parsed by the DDR controller to read data; S5. The abnormality detection module detects whether the DRAM receives an abnormal command from the DDR controller to read the data. If so, step S6 is executed; otherwise, step S7 is executed; S6. The abnormality detection module triggers a hardware interrupt, and the interrupt signal is passed to the MCU and then step S9 is executed; S7.DRAM returns the command read data to the DDR controller; S8. The abnormality detection module detects whether the DRAM returns the command to read the data to the DDR controller abnormally, if so, executes step S6, if otherwise, the DDR control command reads the data back to the MCU; S9. After receiving the interrupt signal, the MCU jumps to the address of the execution program and transfers to the SRAM to execute the DDR exception handling program; S10. After terminating the current DRAM data transmission, the MCU obtains the cause of the abnormality from the register of the DDR controller and determines whether it is a data transmission error. If so, step S12 is executed; otherwise, step S11 is executed; S11. MCU records the DDR controller error information to SRAM and restarts the DDR controller; S12. Perform DRAM data verification, perform read and write tests on the address where the error occurs, and determine whether the error recurs. If so, return to step S11, if not, execute step S13; S13. Record the DDR controller error information, and the abnormality detection module notifies the MCU to resend the read command and then returns to step S2.

[0005] Furthermore, in step S1, the MCU sends the command read data to the DDR controller via the bus.

[0006] Furthermore, in step S3, when the abnormality detection module detects that a timeout error occurs when the DDR controller receives a command sent by the MCU, it is determined to be abnormal.

[0007] Furthermore, in step S5, when the abnormality detection module detects that a timeout error occurs when the DRAM receives the command parsed by the DDR controller to read data, it is determined to be abnormal.

[0008] Furthermore, in step S8, when the abnormality detection module detects that a timeout error occurs when the DRAM returns the command read data to the DDR controller, it is determined to be abnormal.

[0009] Furthermore, in step S11, the DDR controller restores the DRAM data from the external backup device after restarting.

[0010] On the other hand, the present invention also relates to a DDR controller exception handling device, comprising: a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; wherein: The memory is used to store computer programs; The processor is configured to execute, by running a program stored in the memory: S1.MCU starts and sends commands to read data to the DDR controller as required; S2. After receiving the command to read data from the MCU, the DDR controller parses and executes the command to read data; S3. The abnormality detection module detects whether the DDR controller receives an abnormal command sent by the MCU to read the data. If so, step S6 is executed, and if not, step S4 is executed; S4. DRAM receives the command parsed by the DDR controller to read data; S5. The abnormality detection module detects whether the DRAM receives an abnormal command from the DDR controller to read the data. If so, step S6 is executed; otherwise, step S7 is executed; S6. The abnormality detection module triggers a hardware interrupt, and the interrupt signal is passed to the MCU and then step S9 is executed; S7.DRAM returns the command read data to the DDR controller; S8. The abnormality detection module detects whether the DRAM returns the command to read the data to the DDR controller abnormally, if so, executes step S6, if otherwise, the DDR control command reads the data back to the MCU; S9. After receiving the interrupt signal, the MCU jumps to the address of the execution program and transfers to the SRAM to execute the DDR exception handling program; S10. After terminating the current DRAM data transmission, the MCU obtains the cause of the abnormality from the register of the DDR controller and determines whether it is a data transmission error. If so, step S12 is executed; otherwise, step S11 is executed; S11. MCU records the DDR controller error information to SRAM and restarts the DDR controller; S12. Perform DRAM data verification, perform read and write tests on the address where the error occurs, and determine whether the error recurs. If so, return to step S11, if not, execute step S13; S13. Record the DDR controller error information, and the abnormality detection module notifies the MCU to resend the read command and then returns to step S2.

[0011] On the other hand, the present invention also relates to a storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the computer program implements: S1.MCU starts and sends commands to read data to the DDR controller as required; S2. After receiving the command to read data from the MCU, the DDR controller parses and executes the command to read data; S3. The abnormality detection module detects whether the DDR controller receives an abnormal command sent by the MCU to read the data. If so, step S6 is executed, and if not, step S4 is executed; S4. DRAM receives the command parsed by the DDR controller to read data; S5. The abnormality detection module detects whether the DRAM receives an abnormal command from the DDR controller to read the data. If so, step S6 is executed; otherwise, step S7 is executed; S6. The abnormality detection module triggers a hardware interrupt, and the interrupt signal is passed to the MCU and then step S9 is executed; S7.DRAM returns the command read data to the DDR controller; S8. The abnormality detection module detects whether the DRAM returns the command to read the data to the DDR controller abnormally, if so, executes step S6, if otherwise, the DDR control command reads the data back to the MCU; S9. After receiving the interrupt signal, the MCU jumps to the address of the execution program and transfers to the SRAM to execute the DDR exception handling program; S10. After terminating the current DRAM data transmission, the MCU obtains the cause of the abnormality from the register of the DDR controller and determines whether it is a data transmission error. If so, step S12 is executed; otherwise, step S11 is executed; S11. MCU records the DDR controller error information to SRAM and restarts the DDR controller; S12. Perform DRAM data verification, perform read and write tests on the address where the error occurs, and determine whether the error recurs. If so, return to step S11, if not, execute step S13; S13. Record the DDR controller error information, and the abnormality detection module notifies the MCU to resend the read command and then returns to step S2.

[0012] The beneficial effects of the present invention are: improving the stability and reliability of the DDR controller, reducing system crashes and data loss caused by abnormal situations. By dynamically adjusting strategies and error recovery mechanisms, it is ensured that high data read and write efficiency and accuracy can be maintained under abnormal circumstances. Detailed log recording and reporting functions can be provided, which facilitates users to understand the operating status of the DDR controller and perform troubleshooting. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The present invention is a flow chart of the method. DETAILED DESCRIPTION

[0014] The following is combined with Figure 1 The present invention is further described.

[0015] Example 1 A DDR controller exception processing method, comprising: S1.MCU starts and sends commands to read data to the DDR controller as required.

[0016] S2. After receiving the command to read data sent by the MCU, the DDR controller parses and executes the command to read data.

[0017] S3. The abnormality detection module detects whether the DDR controller is abnormal in reading data after receiving the command sent by the MCU. If so, execute step S6; otherwise, execute step S4.

[0018] S4. DRAM receives the command parsed by the DDR controller and reads data.

[0019] S5. The abnormality detection module detects whether the DRAM receives abnormal data from the command parsed by the DDR controller. If so, execute step S6; otherwise, execute step S7.

[0020] S6. The abnormality detection module triggers a hardware interrupt, passes the interrupt signal to the MCU, and then executes step S9.

[0021] S7.DRAM returns the command read data to the DDR controller.

[0022] S8. The abnormality detection module detects whether the DRAM returns the command read data to the DDR controller abnormally. If so, execute step S6. If not, the DDR controller returns the command read data to the MCU.

[0023] S9. After receiving the interrupt signal, the MCU jumps to the address of the execution program and transfers to the SRAM to execute the DDR exception handler.

[0024] S10. After terminating the current DRAM data transmission, the MCU obtains the cause of the exception from the register of the DDR controller and determines whether it is a data transmission error. If so, execute step S12; otherwise, execute step S11.

[0025] S11. MCU records the DDR controller error information to SRAM and restarts the DDR controller.

[0026] S12. Perform DRAM data verification, perform read and write tests on the address where the error occurs, and determine whether the error recurs. If so, return to step S11, if not, execute step S13.

[0027] S13. Record the DDR controller error information, and the abnormality detection module notifies the MCU to resend the read command and then returns to step S2.

[0028] The programs and data required by the MCU during normal operation are all stored in SDRAM. When an exception occurs in the DDR controller, the exception detection module detects the exception information and immediately triggers the DDR controller hardware interrupt, conveying this information to the MCU in the form of a hardware signal. After receiving the information, the MCU immediately terminates the data stream accessed by the DRAM and then jumps to the storage body containing the DDR controller exception handling code, such as SRAM, to execute the corresponding exception handling program. In the exception handling program, the registers of the DDR controller are accessed to obtain its current status and analyze the cause of the exception. Then, based on the analysis results, it is determined whether the DDR controller can return to normal, whether the SDRAM data can be restored, etc., and the error is recorded in the SRAM. After the DDR controller returns to normal, the MCU can read the records in the SRAM to detect the historical status of the DRAM and discover potential problems in a timely manner.

[0029] In this embodiment, in step S1, the MCU sends a command to read data to the DDR controller via the bus.

[0030] In this embodiment, when the abnormality detection module detects in step S3 that a timeout error occurs when the DDR controller receives a command sent by the MCU, it is determined to be abnormal.

[0031] In this embodiment, when the abnormality detection module detects in step S5 that a timeout error occurs when the DRAM receives the command parsed by the DDR controller to read data, it is determined to be abnormal.

[0032] In this embodiment, when the abnormality detection module detects in step S8 that a timeout error occurs when the DRAM returns a command to read data to the DDR controller, it is determined to be abnormal.

[0033] In this embodiment, in step S11 , the DDR controller restores the DRAM data from the external backup device after restarting.

[0034] Example 2 A DDR controller exception processing device comprises: a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; wherein: The memory is used to store computer programs; The processor is configured to execute, by running a program stored in the memory: S1.MCU starts and sends commands to read data to the DDR controller as required.

[0035] S2. After receiving the command to read data sent by the MCU, the DDR controller parses and executes the command to read data.

[0036] S3. The abnormality detection module detects whether the DDR controller is abnormal in reading data after receiving the command sent by the MCU. If so, execute step S6; otherwise, execute step S4.

[0037] S4. DRAM receives the command parsed by the DDR controller and reads data.

[0038] S5. The abnormality detection module detects whether the DRAM receives abnormal data from the command parsed by the DDR controller. If so, execute step S6; otherwise, execute step S7.

[0039] S6. The abnormality detection module triggers a hardware interrupt, passes the interrupt signal to the MCU, and then executes step S9.

[0040] S7.DRAM returns the command read data to the DDR controller.

[0041] S8. The abnormality detection module detects whether the DRAM returns the command read data to the DDR controller abnormally. If so, execute step S6. If not, the DDR controller returns the command read data to the MCU.

[0042] S9. After receiving the interrupt signal, the MCU jumps to the address of the execution program and transfers to the SRAM to execute the DDR exception handler.

[0043] S10. After terminating the current DRAM data transmission, the MCU obtains the cause of the exception from the register of the DDR controller and determines whether it is a data transmission error. If so, execute step S12; otherwise, execute step S11.

[0044] S11. MCU records the DDR controller error information to SRAM and restarts the DDR controller.

[0045] S12. Perform DRAM data verification, perform read and write tests on the address where the error occurs, and determine whether the error recurs. If so, return to step S11, if not, execute step S13.

[0046] S13. Record the DDR controller error information, and the abnormality detection module notifies the MCU to resend the read command and then returns to step S2.

[0047] Example 3 A storage medium, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements: S1.MCU starts and sends commands to read data to the DDR controller as required.

[0048] S2. After receiving the command to read data sent by the MCU, the DDR controller parses and executes the command to read data.

[0049] S3. The abnormality detection module detects whether the DDR controller is abnormal in reading data after receiving the command sent by the MCU. If so, execute step S6; otherwise, execute step S4.

[0050] S4. DRAM receives the command parsed by the DDR controller and reads data.

[0051] S5. The abnormality detection module detects whether the DRAM receives abnormal data from the command parsed by the DDR controller. If so, execute step S6; otherwise, execute step S7.

[0052] S6. The abnormality detection module triggers a hardware interrupt, passes the interrupt signal to the MCU, and then executes step S9.

[0053] S7.DRAM returns the command read data to the DDR controller.

[0054] S8. The abnormality detection module detects whether the DRAM returns the command read data to the DDR controller abnormally. If so, execute step S6. If not, the DDR controller returns the command read data to the MCU.

[0055] S9. After receiving the interrupt signal, the MCU jumps to the address of the execution program and transfers to the SRAM to execute the DDR exception handler.

[0056] S10. After terminating the current DRAM data transmission, the MCU obtains the cause of the exception from the register of the DDR controller and determines whether it is a data transmission error. If so, execute step S12; otherwise, execute step S11.

[0057] S11. MCU records the DDR controller error information to SRAM and restarts the DDR controller.

[0058] S12. Perform DRAM data verification, perform read and write tests on the address where the error occurs, and determine whether the error recurs. If so, return to step S11, if not, execute step S13.

[0059] S13. Record the DDR controller error information, and the abnormality detection module notifies the MCU to resend the read command and then returns to step S2.

[0060] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A DDR controller exception handling method, characterized in that: include: S1.MCU starts and sends commands to read data to the DDR controller as required; S2. After receiving the command to read data from the MCU, the DDR controller parses and executes the command to read data; S3. The abnormality detection module detects whether the DDR controller receives an abnormal command sent by the MCU to read the data. If so, step S6 is executed, and if not, step S4 is executed; S4. DRAM receives the command parsed by the DDR controller to read data; S5. The abnormality detection module detects whether the DRAM receives an abnormal command from the DDR controller to read the data. If so, step S6 is executed; otherwise, step S7 is executed; S6. The abnormality detection module triggers a hardware interrupt, and the interrupt signal is passed to the MCU and then step S9 is executed; S7.DRAM returns the command read data to the DDR controller; S8. The abnormality detection module detects whether the DRAM returns the command to read the data to the DDR controller abnormally, if so, executes step S6, if otherwise, the DDR control command reads the data back to the MCU; S9. After receiving the interrupt signal, the MCU jumps to the address of the execution program and transfers to the SRAM to execute the DDR exception handling program; S10. After terminating the current DRAM data transmission, the MCU obtains the cause of the abnormality from the register of the DDR controller and determines whether it is a data transmission error. If so, step S12 is executed; otherwise, step S11 is executed; S11. MCU records the DDR controller error information to SRAM and restarts the DDR controller; S12. Perform DRAM data verification, perform read and write tests on the address where the error occurs, and determine whether the error recurs. If so, return to step S11, if not, execute step S13; S13. Record the DDR controller error information, and the abnormality detection module notifies the MCU to resend the read command and then returns to step S2.

2. The DDR controller exception handling method according to claim 1, characterized in that: In step S1, the MCU sends a command to read data to the DDR controller via the bus.

3. The DDR controller exception handling method according to claim 1, characterized in that: In step S3, when the abnormality detection module detects that a timeout error occurs when the DDR controller receives a command sent by the MCU, it is determined to be abnormal.

4. The DDR controller exception handling method according to claim 1, characterized in that: In step S5, when the abnormality detection module detects that a timeout error occurs when the DRAM receives the command parsed by the DDR controller to read data, it is determined to be abnormal.

5. The DDR controller exception handling method according to claim 1, characterized in that: In step S8, when the abnormality detection module detects that a timeout error occurs when the DRAM returns the command read data to the DDR controller, it is determined to be abnormal.

6. The DDR controller exception handling method according to claim 1, characterized in that: In step S11, the DDR controller restores the DRAM data from the external backup device after restarting.

7. A DDR controller exception handling device, characterized in that: include: A processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; wherein: The memory is used to store computer programs; The processor is configured to execute, by running a program stored in the memory: S1.MCU starts and sends commands to read data to the DDR controller as required; S2. After receiving the command to read data from the MCU, the DDR controller parses and executes the command to read data; S3. The abnormality detection module detects whether the DDR controller receives an abnormal command sent by the MCU to read the data. If so, step S6 is executed, and if not, step S4 is executed; S4. DRAM receives the command parsed by the DDR controller to read data; S5. The abnormality detection module detects whether the DRAM receives an abnormal command from the DDR controller to read the data. If so, step S6 is executed; otherwise, step S7 is executed; S6. The abnormality detection module triggers a hardware interrupt, and the interrupt signal is passed to the MCU and then step S9 is executed; S7.DRAM returns the command read data to the DDR controller; S8. The abnormality detection module detects whether the DRAM returns the command to read the data to the DDR controller abnormally, if so, executes step S6, if otherwise, the DDR control command reads the data back to the MCU; S9. After receiving the interrupt signal, the MCU jumps to the address of the execution program and transfers to the SRAM to execute the DDR exception handling program; S10. After terminating the current DRAM data transmission, the MCU obtains the cause of the abnormality from the register of the DDR controller and determines whether it is a data transmission error. If so, step S12 is executed; otherwise, step S11 is executed; S11. MCU records the DDR controller error information to SRAM and restarts the DDR controller; S12. Perform DRAM data verification, perform read and write tests on the address where the error occurs, and determine whether the error recurs. If so, return to step S11, if not, execute step S13; S13. Record the DDR controller error information, and the abnormality detection module notifies the MCU to resend the read command and then returns to step S2.

8. A storage medium, characterized in that: The computer readable storage medium stores a computer program, which, when executed by a processor, implements: S1.MCU starts and sends commands to read data to the DDR controller as required; S2. After receiving the command to read data from the MCU, the DDR controller parses and executes the command to read data; S3. The abnormality detection module detects whether the DDR controller receives an abnormal command sent by the MCU to read the data. If so, step S6 is executed, and if not, step S4 is executed; S4. DRAM receives the command parsed by the DDR controller to read data; S5. The abnormality detection module detects whether the DRAM receives an abnormal command from the DDR controller to read the data. If so, step S6 is executed; otherwise, step S7 is executed; S6. The abnormality detection module triggers a hardware interrupt, and the interrupt signal is passed to the MCU and then step S9 is executed; S7.DRAM returns the command read data to the DDR controller; S8. The abnormality detection module detects whether the DRAM returns the command to read the data to the DDR controller abnormally, if so, executes step S6, if otherwise, the DDR control command reads the data back to the MCU; S9. After receiving the interrupt signal, the MCU jumps to the address of the execution program and transfers to the SRAM to execute the DDR exception handling program; S10. After terminating the current DRAM data transmission, the MCU obtains the cause of the abnormality from the register of the DDR controller and determines whether it is a data transmission error. If so, step S12 is executed; otherwise, step S11 is executed; S11. MCU records the DDR controller error information to SRAM and restarts the DDR controller; S12. Perform DRAM data verification, perform read and write tests on the address where the error occurs, and determine whether the error recurs. If so, return to step S11, if not, execute step S13; S13. Record the DDR controller error information, and the abnormality detection module notifies the MCU to resend the read command and then returns to step S2.

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