A method for automated testing of MCU
By integrating the main control MCU chip on the peripheral circuit and using the test machine to control the MCU for automatic program burning and testing, the problem of cumbersome program loading in MCU testing is solved and the test efficiency is improved.
Patent Information
- Application Number
- CN202411313448.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2025-09-26
- Estimated Expiration
- 2044-09-20
AI Technical Summary
The existing MCU testing methods are cumbersome and time-consuming in program loading, low in testing efficiency, and unable to achieve automated configuration and verification.
The main control MCU chip is integrated into the peripheral circuit. The main control chip is controlled by the test machine to program and test the MCU to be tested. The configuration is loaded using the SWD protocol to realize the automated test process.
The MCU test and verification process has been optimized, test efficiency has been improved, and automated program configuration and verification without human intervention has been achieved.
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Figure CN119597565B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of MCU testing, and more particularly, relates to an MCU automatic testing method. Background Art
[0002] MCUs are currently widely used in various fields, including smart homes. Cortex-M core MCUs, in particular, account for a significant portion of the market. MCU testing methods vary from production to packaging and shipment. Existing testing methods require multiple write and erase operations on the MCU. Vectors are written to test a specific MCU function, then erased, and new vectors are written to test other functions. MCU testing requirements are also high, but one of the current difficulties in MCU testing is bitstream loading.
[0003] Typically, when testing digital circuits, the tester applies stimulus based on the corresponding function, observes the output response, and then performs the test. However, when testing MCUs, simply applying stimulus is not possible; testing requires programming to call different module functions before testing.
[0004] The MCU has three BOOT modes when it leaves the factory. The first is to boot from the chip's built-in SRAM, the second is to boot from the chip's built-in FLASH, and the third is to boot from a Bootload reserved in the system memory.
[0005] In MCU applications and routine testing, an external emulator is typically required to configure and load the MCU. The current mainstream testing method involves burning the compiled BIN file into the MCU's internal Flash memory via a PC connected to the emulator. This allows for functional testing and verification of the various modules by programming the configuration. Because MCUs integrate numerous peripherals and interfaces, increasing test coverage requires multiple configuration runs. Conventional configuration methods are time-consuming and cumbersome during testing, resulting in low MCU testing and verification efficiency.
[0006] The invention patent application, published on April 5, 2024, with publication number CN117826743A and titled "An Embedded MCU Test System and Test Method," includes: a chip to be tested and a functional module, a function detection module, and a performance detection module connected to the chip to be tested. In this application, the function of the chip to be tested is detected by the function detection module, and the performance detection module detects the performance of the chip to be tested by the performance detection module. Function detection and performance detection are detected separately, and performance detection is performed only after function detection. In this way, the function detection of the chip to be tested is more comprehensive, ensuring a longer life of the chip to be tested. This invention patent application only makes improvements in terms of functional performance detection and does not involve the MCU configuration loader.
[0007] In the invention patent application entitled "MCU Test Circuit and MCU Test Method," published on January 23, 2024, with publication number CN117434430A, the MCU test circuit includes a master MCU, an MCU under test, an LDO circuit, a voltage adjustment circuit, and a voltage acquisition circuit. The master MCU has an ADC input pin, a DAC input / output pin, a general input pin, and a general output pin. The master MCU is used to adjust the output voltage of the LDO circuit via the DAC input / output pin and the voltage adjustment circuit, and to acquire the output voltage of the LDO circuit via the ADC input pin and the voltage acquisition circuit, thereby performing closed-loop control of the LDO circuit to achieve high-precision testing of the PMU of the MCU under test. This solution can improve the testing efficiency of the PMU monitoring and processing functions of the MCU under test. This invention adds a master MCU for testing the MCU under test, but this invention only achieves high-precision testing of the PMU of the MCU under test. Summary of the Invention
[0008] The purpose of the present invention is to overcome the deficiencies of the prior art and provide an MCU automated testing method to optimize the MCU test verification process and improve the efficiency of MCU test verification.
[0009] To achieve the above object of the invention, the MCU automated testing method of the present invention is characterized by comprising the following steps:
[0010] (1) A main control MCU chip is integrated in the peripheral circuit to connect with the test machine and the MCU chip to be tested to configure the loading program. The test machine controls the main control chip to burn different programs into the MCU chip to be tested and then perform corresponding tests;
[0011] (2) Preparation before the test: Parse the FLM file corresponding to the MCU chip to be tested, i.e., the FLM download algorithm. Convert the debugged X function codes, i.e., the compiled X BIN files, and the parsed FLM download algorithm into a script file of binary data that can be burned into FLASH through the PC. Store it into the main control MCU chip through the JTAG protocol. The main control program of the main control MCU chip receives the command of the test machine through polling to control the reading and writing of the FLASH of the MCU chip to be tested.
[0012] (3) The test machine controls the configuration program of the main control MCU chip: the test machine sends instructions to control the main control MCU chip to configure different function codes to the MCU chip to be tested, so as to test the internal resources of the MCU chip;
[0013] (4) Configuration program of the master MCU chip: The master MCU chip is connected to the SWDIO / SWCLK pin of the MCU chip under test, and the function code is configured into the MCU chip under test by sending a data code stream through the SWD protocol. The debug port DP of the MCU chip under test realizes the physical connection between the debug interface of the master MCU chip and the MCU chip under test, and the access port AP of the MCU chip under test realizes the access to the kernel resources. After the configuration is successful, the master MCU chip sends a configuration success message to the test machine;
[0014] (5) Start the execution program: After the test machine receives the configuration success information sent by the main control MCU chip, it configures the MCU chip to start the execution program from the internal FLASH;
[0015] (6) Execute test verification: The test machine performs test and verification on the MCU chip to be tested, including AC and DC parameter testing and peripheral function verification;
[0016] (7) Determine whether the test is finished, that is, whether all X function codes have been configured to the MCU chip to be tested. If finished, the MCU test is completed. If not finished, return to step (3).
[0017] The object of the present invention is achieved in this way.
[0018] The MCU automated testing method of the present invention integrates a main control MCU chip on the peripheral circuit, which is used to connect with the test machine and the device under test to configure and load the program. The test machine controls the main control chip to burn different programs into the MCU under test and then perform corresponding tests. The present invention solves the problem of the program needing to be repeatedly configured and loaded online during the MCU testing process. That is, no external manual intervention is required during the MCU testing process, and the program's repeated configuration loading and test verification are completed by the test machine throughout the entire process. The present invention optimizes the chip test verification process and greatly improves the efficiency of MCU test verification. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 This is a flowchart of a specific implementation method of the MCU automated testing method of the present invention;
[0020] Figure 2 yes Figure 1 The MCU automated testing method shown corresponds to the process architecture diagram;
[0021] Figure 3 yes Figure 1 Schematic diagram of the process of preparation before testing;
[0022] Figure 4 yes Figure 1 The flowchart of the test machine control main MCU chip configuration program is shown;
[0023] Figure 5 yes Figure 1 The flowchart of the main control MCU chip configuration program is shown;
[0024] Figure 6 yes Figure 1 The flowchart for executing test verification is shown in FIG. DETAILED DESCRIPTION
[0025] The following describes the specific embodiments of the present invention in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, such descriptions will be omitted here.
[0026] Figure 1 It is a flowchart of a specific implementation method of the MCU automatic testing method of the present invention.
[0027] In this embodiment, if Figure 1 As shown, the MCU automated testing method of the present invention includes the following steps:
[0028] Step S1: Add a main control MCU chip
[0029] In this embodiment, if Figure 2 As shown, a master MCU chip is integrated into the peripheral circuitry. This chip connects to the ATE (Automatic Test Equipment) tester and the MCU under test to configure and load programs. The tester controls the master chip to program the MCU under test with different programs before performing the corresponding tests. ATE is a computer-controlled device that tests components, circuit boards, and subsystems. Computer programming replaces manual labor, allowing automated test sequences.
[0030] Step S2: Preparation before testing
[0031] In this embodiment, if Figure 2 、 3 As shown, the FLM file corresponding to the MCU chip to be tested, that is, the FLM download algorithm, is parsed. The debugged X function codes Bin1, that is, the compiled X BIN files, and the parsed FLM download algorithm are converted into a script file of binary data that can be burned to FLASH through a script on the PC. The script file is stored in the main control MCU chip through the JTAG protocol. Among them, the main control program of the main control MCU chip receives the command of the test machine in a polling manner to control the reading and writing of the FLASH of the MCU chip to be tested.
[0032] The FLM file corresponding to the MCU chip under test is downloaded and the algorithm is used to parse the Flash information and the required symbols and sections in sequence. Then, based on the section information, a script file of the binary blob of the algorithm program that can be executed in RAM is created. In this way, the BIN or HEX file completed by the debug compiler of the MCU under test can be converted into a script file of binary data that can be burned to the flash.
[0033] Step S3: Test the machine control main MCU chip configuration program
[0034] MCU internal resources are very rich, usually in the MCU test need to be configured multiple times to improve the MCU internal resource test coverage. Figure 2 、 4 As shown, the test machine ATE sends instructions to control the main control MCU chip to configure different function codes to the MCU chip under test to test the internal resources of the MCU chip.
[0035] Step S4: Main control MCU chip configuration program
[0036] In this embodiment, if Figure 2 、 5 As shown, the master MCU chip is connected to the SWDIO / SWCLK pin of the MCU chip under test, and the function code is configured into the MCU chip under test by sending a data code stream through the SWD protocol. The debug port DP of the MCU chip under test realizes the physical connection between the debug interface of the master MCU chip and the MCU chip under test, and the access port AP of the MCU chip under test realizes access to the kernel resources. After the configuration is successful, the master MCU chip sends a configuration success message to the test machine. In this embodiment,
[0037] Step S5: Start the execution program
[0038] In this embodiment, if Figure 2 、 6As shown, after the test machine ATE receives the configuration success information sent by the main control MCU chip, it configures the MCU chip to start executing the program from the internal FLASH;
[0039] Step S6: Perform test verification
[0040] In this embodiment, if Figure 2 、 6 As shown, the test machine ATE performs testing and verification on the MCU chip to be tested, including AC and DC parameter testing and peripheral function verification.
[0041] Step S7: Determine whether the test is finished, that is, whether all X function codes have been configured to the MCU chip to be tested. If finished, the MCU test is completed. If not finished, return to step S3.
[0042] Although the above describes the illustrative specific embodiments of the present invention to facilitate understanding of the present invention by those skilled in the art, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concepts of the present invention are protected.
Claims
1. A MCU automated testing method, characterized in that: The following steps are involved: (1) A main control MCU chip is integrated in the peripheral circuit to connect with the test machine and the MCU chip to be tested to configure the loading program. The test machine controls the main control chip to burn different programs into the MCU chip to be tested and then perform corresponding tests; (2) Preparation before the test: Parse the FLM file corresponding to the MCU chip to be tested, i.e., the FLM download algorithm. Convert the debugged X function codes, i.e., the compiled X BIN files, and the parsed FLM download algorithm into a script file of binary data that can be burned into FLASH through the PC. Store it into the main control MCU chip through the JTAG protocol. The main control program of the main control MCU chip receives the command of the test machine through polling to control the reading and writing of the FLASH of the MCU chip to be tested. (3) The test machine controls the configuration program of the main control MCU chip: the test machine sends instructions to control the main control MCU chip to configure different function codes to the MCU chip to be tested, so as to test the internal resources of the MCU chip; (4) Configuration program of the master MCU chip: The master MCU chip is connected to the SWDIO / SWCLK pin of the MCU chip under test, and the function code is configured into the MCU chip under test by sending a data code stream through the SWD protocol. The debug port DP of the MCU chip under test realizes the physical connection between the debug interface of the master MCU chip and the MCU chip under test, and the access port AP of the MCU chip under test realizes the access to the kernel resources. After the configuration is successful, the master MCU chip sends a configuration success message to the test machine; (5) Start the execution program: After the test machine receives the configuration success information sent by the main control MCU chip, it configures the MCU chip to start the execution program from the internal FLASH; (6) Execute test verification: The test machine performs test and verification on the MCU chip to be tested, including AC and DC parameter testing and peripheral function verification; (7) Determine whether the test is finished, that is, whether all X function codes have been configured to the MCU chip to be tested. If finished, the MCU test is completed. If not finished, return to step (3).
2. The MCU automated testing method according to claim 1, wherein: The test machine is ATE (Automatic Test Equipment).
Citation Information
Patent Citations
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