Chip simulation model generation method and device, equipment and storage medium

Abstract

The invention relates to a chip simulation model generation method and device, equipment and a storage medium. The method comprises the following steps: acquiring a configuration file of each module of a chip to be modeled, wherein the configuration file is used for describing a register of the module corresponding to the configuration file; analyzing the configuration file of each module, and determining information of a register of each module; according to the information of the registers of all the modules, register objects in the chip simulation model and index data of the register objects are generated, and the index data are used for searching the register objects in the chip simulation model; and generating the simulation model according to the register object in the simulation model and the index data of the register object. By adopting the method, rapid simulation modeling can be carried out on the chip at the register level.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a method, device, equipment and storage medium for generating a chip simulation model. Background Art

[0002] At present, in chip verification activities, emulators can be used to simulate chips and run chip software on the simulated chips. The simulated chips allow developers to develop and test chip software without hardware support, which improves the efficiency of chip software development and testing.

[0003] In the related art, the simulator for simulating the chip includes the Quick Emulator (QEMU) simulator. However, the QEMU simulator can usually only establish a chip simulation model based on the business level, and cannot simulate the register level well. Therefore, there is currently a lack of methods for fast simulation modeling of chips at the register level. Summary of the invention

[0004] Based on this, it is necessary to provide a method, device, equipment and storage medium for generating a chip simulation model that can quickly simulate and model the chip at the register level to address the above technical problems.

[0005] In a first aspect, the present application provides a method for generating a chip simulation model. The method comprises:

[0006] Obtain configuration files of various modules of the chip to be modeled, where the configuration files are used to describe registers of the modules corresponding to the configuration files;

[0007] Parsing the configuration files of the modules to determine the register information of the modules;

[0008] Generate a register object in the chip simulation model and index data of the register object according to the register information of each module, wherein the index data is used to search for the register object in the chip simulation model;

[0009] The chip simulation model is generated according to the register objects in the chip simulation model and the index data of the register objects.

[0010] In one embodiment, the index data includes a pointer array and a mapping relationship table corresponding to each module, the pointer array is used to determine the mapping relationship table corresponding to the module to which the register object to be searched belongs, and the mapping relationship table includes the association relationship between the register object of the module corresponding to the mapping relationship table and the access address.

[0011] In one of the embodiments, after generating the chip simulation model according to the register objects in the chip simulation model and the index data of the register objects, the method further includes:

[0012] Receive a register access request, wherein the access request is used to request access to a target register object, and the target register object is any register object in the chip simulation model;

[0013] According to the pointer array, searching for a mapping relationship table corresponding to the module to which the target register object belongs;

[0014] Determine the access address of the target register object according to the mapping relationship table corresponding to the module to which the target register object belongs;

[0015] The target register object is accessed in the chip simulation model using the access address of the target register object.

[0016] In one embodiment, searching, according to the pointer array, a mapping relationship table corresponding to the module to which the target register object belongs includes:

[0017] According to the first address of the mapping relationship table corresponding to each module stored in the pointer array, the mapping relationship table corresponding to the module to which the target register object belongs is searched.

[0018] In one embodiment, determining the access address of the target register object according to a mapping relationship table corresponding to the module to which the target register object belongs includes:

[0019] In the mapping relationship table corresponding to the module to which the target register object belongs, a binary search algorithm is used to determine the access address of the target register object.

[0020] In one of the embodiments, the chip simulation model is further provided with an external interface;

[0021] After generating the chip simulation model according to the register objects in the chip simulation model and the index data of the register objects, the method further includes:

[0022] The chip simulation model is connected to the external test software through the external interface, so that the external test software calls the chip simulation model to perform software debugging.

[0023] In a second aspect, the present application also provides a device for generating a chip simulation model. The device comprises:

[0024] An acquisition module is used to acquire configuration files of various modules of the chip to be modeled, wherein the configuration files are used to describe registers of the modules corresponding to the configuration files;

[0025] A parsing module, used to parse the configuration files of the modules and determine the register information of the modules;

[0026] A generation module is used to generate register objects in the chip simulation model and index data of the register objects according to the information of the registers of the various modules, and the index data is used to search for the register objects in the chip simulation model; the chip simulation model is generated according to the register objects in the chip simulation model and the index data of the register objects.

[0027] In one embodiment, the index data includes a pointer array and a mapping relationship table corresponding to each module, the pointer array is used to determine the mapping relationship table corresponding to the module to which the register object to be searched belongs, and the mapping relationship table includes the association relationship between the register object of the module corresponding to the mapping relationship table and the access address.

[0028] In one embodiment, the chip simulation model generation device further includes:

[0029] A query module is used to receive a register access request, wherein the access request is used to request access to a target register object, wherein the target register object is any register object in the chip simulation model; according to the pointer array, a mapping relationship table corresponding to the module to which the target register object belongs is searched; according to the mapping relationship table corresponding to the module to which the target register object belongs, an access address of the target register object is determined; and the target register object is accessed in the chip simulation model using the access address of the target register object.

[0030] In one of the embodiments, the query module is specifically used to search for a mapping relationship table corresponding to the module to which the target register object belongs according to the first address of the mapping relationship table corresponding to each module stored in the pointer array.

[0031] In one of the embodiments, the query module is specifically configured to determine the access address of the target register object by using a binary search algorithm in a mapping relationship table corresponding to the module to which the target register object belongs.

[0032] In one of the embodiments, the chip simulation model is further provided with an external interface;

[0033] The chip simulation model generation device also includes:

[0034] The access module is used to access the chip simulation model to the external test software through the external interface, so that the external test software calls the chip simulation model to perform software debugging.

[0035] In a third aspect, the present application further provides a computer device, wherein the computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the method for generating a chip simulation model described in the first aspect is implemented.

[0036] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method for generating a chip simulation model described in the first aspect above is implemented.

[0037] In a fifth aspect, the present application further provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the method for generating a chip simulation model described in the first aspect is implemented.

[0038] The above-mentioned chip simulation model generation method, device, equipment and storage medium first obtain the configuration files of each module of the chip to be modeled, and the configuration files are used to describe the registers of the modules corresponding to the configuration files. Secondly, the configuration files of each module are parsed to determine the information of the registers of each module. Thirdly, according to the information of the registers of each module, the register objects and the index data of the register objects in the chip simulation model are generated, and the index data are used to find the register objects in the chip simulation model. Finally, the simulation model is generated according to the register objects and the index data of the register objects in the simulation model. Through the chip simulation model generation method, since the register objects and the index data of the register objects are generated based on the information of the registers of each module, and then the chip simulation model is generated through the register objects and the index data of the register objects, the generated chip simulation model can simulate the register level very well, thereby realizing the rapid simulation modeling of the chip at the register level. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 An application environment diagram of a chip simulation model generation method provided in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of a process for generating a chip simulation model provided in an embodiment of the present application;

[0041] Figure 3 A schematic diagram of the structure of a model template provided in an embodiment of the present application;

[0042] Figure 4A schematic diagram of a chip simulation model provided in an embodiment of the present application being connected to external testing software;

[0043] Figure 5 A schematic diagram of a flow chart of another method for generating a chip simulation model provided in an embodiment of the present application;

[0044] Figure 6 A schematic diagram of a data structure of index data provided in an embodiment of the present application;

[0045] Figure 7 A schematic diagram of a flow chart of another method for generating a chip simulation model provided in an embodiment of the present application;

[0046] Figure 8 A schematic diagram of a flow chart of another method for generating a chip simulation model provided in an embodiment of the present application;

[0047] Fig. 9 A structural block diagram of a device for generating a chip simulation model provided in an embodiment of the present application;

[0048] Fig.10 An internal structure diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0050] The chip simulation model generation method provided in the embodiment of the present application can be implemented through a terminal device or a server.

[0051] Exemplarily, if the above-mentioned chip simulation model generation method can be implemented by a terminal device, then after obtaining the configuration files of each module of the chip to be modeled, the terminal device can directly parse the configuration files to determine the register information. Subsequently, the terminal device can generate the register objects and the index data of the register objects in the chip simulation model according to the register information, and then generate the chip simulation model based on the register objects and the index data of the register objects in the chip simulation model.

[0052] For example, if the above chip simulation model generation method can also be implemented by a server, it can be applied to Figure 1 In the application environment shown, the terminal 102 communicates with the server 104 through a network. The data storage system can store data that the server 104 needs to process. The data storage system can be integrated on the server 104, or placed on the cloud or other network servers.

[0053] The terminal device 102 scans the directory storing the configuration files of the chip to be modeled, and obtains the configuration files of each module of the chip to be modeled. Subsequently, the server 104 obtains the configuration files from the terminal device 102, and parses the configuration files to determine the register information. Subsequently, the server 104 can generate the register objects and the index data of the register objects in the chip simulation model according to the register information, and then generate the chip simulation model based on the register objects and the index data of the register objects in the chip simulation model. Finally, when the chip software needs to be debugged, the server 104 can send the chip simulation model to the corresponding debugging device.

[0054] The directory of the configuration file of the chip to be modeled is not a specific file storage location, and can be set arbitrarily according to actual conditions. Exemplarily, the directory of the configuration file of the chip to be modeled can be any folder for storing the configuration file of the chip to be modeled.

[0055] The terminal 102 may be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, IoT devices, and portable wearable devices. The IoT devices may be smart speakers, smart TVs, smart air conditioners, smart car-mounted devices, etc. The portable wearable devices may be smart watches, smart bracelets, head-mounted devices, etc. The server 104 may be implemented as an independent server or a server cluster consisting of multiple servers.

[0056] In one embodiment, Figure 2 As shown, a method for generating a chip simulation model is provided, and the method is applied to a terminal device as an example for description, including S201-S204:

[0057] S201. Obtain configuration files of various modules of the chip to be modeled, where the configuration files are used to describe registers of the modules corresponding to the configuration files.

[0058] In the present application, when simulation modeling of a chip is required, configuration files of various modules of the chip to be modeled may be obtained to generate a chip simulation model.

[0059] It should be understood that a chip generally includes multiple modules, each module is responsible for different functions, and exemplary, the modules of the chip may include a timer module, an interrupt controller, a power management module, an analog-to-digital converter (ADC), etc. In the embodiment of the present application, each module of the chip corresponds to a configuration file, and each configuration file contains register information of the corresponding module.

[0060] The present application embodiment does not limit the file format of the configuration file, which can be a configuration file in any data format. Exemplarily, the configuration file can be a hardware abstraction layer header (HAL.h) file, which can contain declarations of chip operation functions, constants, and data structures.

[0061] It should be understood that the embodiments of the present application do not limit how to obtain the configuration files of each module of the chip to be modeled. In some embodiments, the terminal device can collect the configuration files of each module of the chip by scanning the file directory of the chip to be modeled.

[0062] S202: Parse the configuration files of each module to determine the register information of each module.

[0063] In this step, after the terminal device obtains the configuration files of each module of the chip to be modeled, it can parse the configuration files of each module to determine the register information of each module.

[0064] The register information may include register address information and register bit segment information, etc. The register address information may include a register reset value, a register valid bit mask, a register offset address, and a register absolute address, etc.

[0065] It should be understood that the embodiments of the present application do not limit how to parse the register information from the configuration file. In some embodiments, the terminal device extracts the register information from the configuration file through various computer languages ​​or regular matching.

[0066] Among them, the above-mentioned computer languages ​​may include C language, Python language, etc.

[0067] S203. Generate register objects and index data of register objects in the chip simulation model according to the register information of each module. The index data is used to search for register objects in the chip simulation model.

[0068] In this step, after the terminal device parses the register information of each module, it can generate the register object and the index data of the register object in the chip simulation model according to the register information of each module.

[0069] It should be understood that the embodiments of the present application do not limit how to generate register objects in a chip simulation model. In some embodiments, the domain objects of the chip to be modeled can be instantiated, and then the register objects in the above chip simulation model can be generated based on the register information and the instantiated domain objects.

[0070] In some embodiments, after the terminal device parses the address information of the register from the information of the registers of each module, the index data of the register object can be established based on the address information of the register.

[0071] The index data of the register object may include two levels of index information, so as to perform indexing in a hierarchical manner to search for the register object.

[0072] Exemplarily, the index data includes a pointer array and a mapping relationship table corresponding to each module. The first level is the pointer array, and the second level is the mapping relationship table. The pointer array is used to determine the mapping relationship table corresponding to the module to which the register object to be found belongs, and the mapping relationship table includes the association relationship between the register object of the module corresponding to the mapping relationship table and the access address.

[0073] Exemplarily, the pointer array may include the first address of the mapping relationship table corresponding to each module. When searching for a register object, the first address of the mapping relationship table corresponding to the module to which the target register object to be searched belongs may be first determined through the pointer array, and then the mapping relationship table corresponding to the module to which the target register object belongs is obtained through the first address of the found mapping relationship table. Subsequently, the access address of the target register object is found in the mapping relationship table corresponding to the module to which the target register object belongs.

[0074] Two-level indexing through the pointer array and the mapping relationship table corresponding to each module can not only avoid the space waste caused by the non-continuous address of the register, but also avoid the slow search speed caused by directly indexing the mapping relationship table, so that when searching for register objects in the chip simulation model, the time complexity and space complexity can be optimized.

[0075] S204: Generate a chip simulation model according to the register objects in the chip simulation model and the index data of the register objects.

[0076] In this step, after the terminal device generates the register objects and index data of the register objects in the chip simulation model according to the register information of each module, the chip simulation model can be generated according to the register objects and index data of the register objects in the chip simulation model.

[0077] It should be understood that the embodiments of the present application do not limit how to generate a chip simulation model based on register objects and index data of register objects in the chip simulation model. In some embodiments, a chip simulation model can be generated based on register objects, index data and a pre-set model template.

[0078] For example, Figure 3A schematic diagram of a model template provided in an embodiment of the present application, such as Figure 3 As shown, the above model template may include a register-related unit and a model engine unit, wherein the model engine unit includes an interface unit and a search unit, and the register-related unit includes an integration unit, a management unit, a register object unit and a register bit segment unit.

[0079] The interface unit includes the external interface of the chip simulation model, providing register read and write functions. The search unit is used to search for the corresponding register object in the chip simulation model based on the address. The integration unit is responsible for the aggregation of register objects corresponding to all modules in the chip simulation model. The register object unit includes the register objects corresponding to each module, and the register bit segment unit includes the implementation of each bit segment of the register object.

[0080] It should be understood that the above-mentioned model engine unit can be a unit pre-generated in the model template, and the above-mentioned register-related unit can be adjusted based on the register object and the index data of the register object in the chip simulation model, so that the adjusted register-related unit and model engine unit are finally combined into a chip simulation model.

[0081] In some embodiments, after the chip simulation model is generated, the terminal device can connect the chip simulation model to the external test software through the external interface, so that the external test software calls the chip simulation model to perform software debugging.

[0082] The external test software may be chip software. In chip verification activities, the external test software is integrated with a chip simulation model so that the chip simulation model can simulate a real chip, thereby assisting the development and testing of the external test software.

[0083] Among them, the above-mentioned external interface can be any interface in the interface unit, and the embodiment of the present application does not limit this. Exemplarily, it can be a read-write interface.

[0084] For example, Figure 4 A schematic diagram of a chip simulation model provided in an embodiment of the present application connected to an external test software, such as Figure 4 As shown, the external test software includes an interface layer, a business layer and a module layer. After the chip simulation model is connected to the external test software, it is located at the bottom layer of the external test software.

[0085] In the present application, since the above chip simulation model has no external dependencies, it can complete self-compilation independently, so that the chip simulation model can be easily connected to any external testing software without changing other codes.

[0086] The chip simulation model generation method provided in the embodiment of the present application can quickly construct the chip simulation model only after the configuration information related to the registers of the chip to be modeled is released, thereby greatly reducing the development speed of the chip software, and will not occupy any hardware components, saving software development costs.

[0087] The method for generating a chip simulation model provided in an embodiment of the present application first obtains configuration files of each module of the chip to be modeled, and the configuration files are used to describe the registers of the modules corresponding to the configuration files. Secondly, the configuration files of each module are parsed to determine the information of the registers of each module. Thirdly, based on the information of the registers of each module, register objects and index data of the register objects in the chip simulation model are generated, and the index data are used to find the register objects in the chip simulation model. Finally, a simulation model is generated based on the register objects and index data of the register objects in the simulation model. Through the method for generating a chip simulation model, register objects and index data of register objects are generated based on the information of the registers of each module, and then a chip simulation model is generated through the register objects and index data of the register objects, so that the generated chip simulation model can simulate the register level very well, thereby realizing rapid simulation modeling of the chip at the register level.

[0088] The following describes how to access register objects in the chip simulation model. Figure 5 A schematic diagram of a process flow of another method for generating a chip simulation model provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the method for generating the chip simulation model includes S301-S308:

[0089] S301. Obtain configuration files of various modules of the chip to be modeled, where the configuration files are used to describe registers of the modules corresponding to the configuration files.

[0090] S302: parse the configuration files of each module to determine the register information of each module.

[0091] S303. Generate register objects and index data of register objects in the chip simulation model according to the register information of each module, where the index data is used to search for register objects in the chip simulation model.

[0092] Among them, the index data includes a pointer array and a mapping relationship table corresponding to each module. The pointer array is used to determine the mapping relationship table corresponding to the module to which the register object to be found belongs. The mapping relationship table includes the association relationship between the register object of the module corresponding to the mapping relationship table and the access address.

[0093] For example, Figure 6A schematic diagram of a data structure of index data provided in an embodiment of the present application. Figure 6 As shown in FIG. 1 , the chip includes an input output subsystem (IOSUB) module, a hardware acceleration (HAC) module, a data processing engine (DPE) module, a remote direct memory access processing engine (RDMA Processing Engine, RPE) module, and a peripheral component interconnect extension (PCIE) module. The pointer data contains the first address of the mapping relationship table corresponding to the IOSUB module, the HAC module, the DPE module, the RPE module, and the PCIE module. The corresponding mapping relationship table can be found through the first address of the mapping relationship table stored in the pointer data. Each mapping relationship contains an access address and a register object value, and the register object value is used to distinguish different register objects.

[0094] Each mapping relationship includes a plurality of association relationships between register objects and access addresses, and each association relationship can be arranged in ascending order according to the access address to speed up the search.

[0095] S304: Generate a chip simulation model according to the register objects in the chip simulation model and the index data of the register objects.

[0096] S305: Receive a register access request.

[0097] The access request is used to request access to a target register object, and the target register object is any register object in the chip simulation model.

[0098] S306. According to the pointer array, search for a mapping relationship table corresponding to the module to which the target register object belongs.

[0099] It should be understood that the embodiments of the present application provide for how to find the mapping relationship table corresponding to the module to which the target register object belongs. In some embodiments, the terminal device can find the mapping relationship table corresponding to the module to which the target register object belongs based on the first address of the mapping relationship table corresponding to each module stored in the pointer array.

[0100] For example, continue to refer to Figure 6 When the target register object belongs to the IOSUB module, the pointer data can determine the first address of the mapping relationship table corresponding to the IOSUB module, and then find the mapping relationship table corresponding to the IOSUB module through the first address of the mapping relationship table corresponding to the IOSUB module.

[0101] S307: Determine the access address of the target register object according to the mapping relationship table corresponding to the module to which the target register object belongs.

[0102] It should be understood that the embodiments of the present application provide for how to determine the access address of the target register object based on the mapping relationship table corresponding to the module to which the target register object belongs. In some embodiments, the terminal device may use a binary search algorithm to determine the access address of the target register object in the mapping relationship table corresponding to the module to which the target register object belongs.

[0103] Among them, the binary search algorithm is a search algorithm for finding a specific element in an ordered array. It divides the array into two parts from the middle, and then determines the size relationship between the target element and the middle element. If they are equal, it returns the index of the middle element. If the target element is smaller, it continues to search in the left half, and if the target element is larger, it continues to search in the right half until the target element is found or it is determined that the target element is not in the array.

[0104] In the present application, by arranging the association relationships in the mapping relationship table in ascending order according to the access address, the mapping relationship table can be used as an ordered array, and the association relationships can be used as elements in the ordered array, so that the access address matching the target register object can be quickly found through a binary search algorithm.

[0105] S308. Use the access address of the target register object to access the target register object in the chip simulation model.

[0106] Two-level indexing through the pointer array and the mapping relationship table corresponding to each module can not only avoid the space waste caused by the non-continuous address of the register, but also avoid the slow indexing speed caused by directly indexing through the mapping relationship table, thereby achieving the comprehensive optimization in time complexity and space complexity when searching for register objects in the chip simulation model.

[0107] Figure 7 A schematic diagram of a process flow of another chip simulation model generation method provided in an embodiment of the present application is shown as follows: Figure 7 As shown, the method for generating the chip simulation model includes S401-S405:

[0108] S401. Obtain configuration files of various modules of the chip to be modeled, where the configuration files are used to describe registers of the modules corresponding to the configuration files.

[0109] S402: Parse the configuration files of each module to determine the register information of each module.

[0110] S403. Generate register objects and index data of register objects in the chip simulation model according to the register information of each module, where the index data is used to search for register objects in the chip simulation model.

[0111] S404: Generate a chip simulation model according to the register objects in the chip simulation model and the index data of the register objects.

[0112] S405 . Connect the chip simulation model to the external test software through the external interface, so that the external test software calls the chip simulation model to perform software debugging.

[0113] The external test software may be chip software. In chip verification activities, the external test software is integrated with a chip simulation model so that the chip simulation model can simulate a real chip, thereby assisting the development and testing of the external test software.

[0114] Among them, the above-mentioned external interface can be any interface in the interface unit, and the embodiment of the present application does not limit this. Exemplarily, it can be a read-write interface.

[0115] In the present application, since the above chip simulation model has no external dependencies, it can complete self-compilation independently, so that the chip simulation model can be easily connected to any external testing software without changing other codes.

[0116] Figure 8 A schematic diagram of a process flow of another method for generating a chip simulation model provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, the method for generating the chip simulation model includes S501-S509:

[0117] S501. Obtain configuration files of various modules of the chip to be modeled, where the configuration files are used to describe registers of the modules corresponding to the configuration files.

[0118] S502: Parse the configuration files of each module to determine the register information of each module.

[0119] S503. Generate register objects and index data of register objects in the chip simulation model according to the register information of each module, where the index data is used to search for register objects in the chip simulation model.

[0120] Among them, the index data includes a pointer array and a mapping relationship table corresponding to each module. The pointer array is used to determine the mapping relationship table corresponding to the module to which the register object to be found belongs. The mapping relationship table includes the association relationship between the register object of the module corresponding to the mapping relationship table and the access address.

[0121] S504: Generate a chip simulation model according to the register objects in the chip simulation model and the index data of the register objects.

[0122] S505 , connecting the chip simulation model to the external test software through the external interface, so that the external test software calls the chip simulation model to perform software debugging.

[0123] S506: Receive a register access request, where the access request is used to request access to a target register object, and the target register object is any register object in the chip simulation model.

[0124] S507. According to the first address of the mapping relationship table corresponding to each module stored in the pointer array, search for the mapping relationship table corresponding to the module to which the target register object belongs.

[0125] S508. Determine the access address of the target register object using a binary search algorithm in the mapping relationship table corresponding to the module to which the target register object belongs.

[0126] S509: Use the access address of the target register object to access the target register object in the chip simulation model.

[0127] The method for generating a chip simulation model provided in an embodiment of the present application first obtains configuration files of each module of the chip to be modeled, and the configuration files are used to describe the registers of the modules corresponding to the configuration files. Secondly, the configuration files of each module are parsed to determine the information of the registers of each module. Thirdly, based on the information of the registers of each module, register objects and index data of the register objects in the chip simulation model are generated, and the index data are used to find the register objects in the chip simulation model. Finally, a simulation model is generated based on the register objects and index data of the register objects in the simulation model. Through the method for generating a chip simulation model, register objects and index data of register objects are generated based on the information of the registers of each module, and then a chip simulation model is generated through the register objects and index data of the register objects, so that the generated chip simulation model can simulate the register level very well, thereby realizing rapid simulation modeling of the chip at the register level.

[0128] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0129] Based on the same inventive concept, the embodiment of the present application also provides a device for generating a chip simulation model for implementing the method for generating a chip simulation model involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiments of the device for generating one or more chip simulation models provided below can refer to the limitations of the method for generating a chip simulation model above, and will not be repeated here.

[0130] In one embodiment, Fig. 9 As shown, a device 600 for generating a chip simulation model is provided, comprising: an acquisition module 601, a parsing module 602, a generation module 603, a query module 604 and an access module 605, wherein:

[0131] The acquisition module 601 is used to acquire configuration files of each module of the chip to be modeled, where the configuration files are used to describe the registers of the modules corresponding to the configuration files.

[0132] The parsing module 602 is used to parse the configuration files of each module and determine the register information of each module.

[0133] Generation module 603 is used to generate register objects and index data of register objects in the chip simulation model according to the register information of each module, and the index data is used to find register objects in the chip simulation model; the chip simulation model is generated according to the register objects and index data of register objects in the chip simulation model.

[0134] In one of the embodiments, the index data includes a pointer array and a mapping relationship table corresponding to each module. The pointer array is used to determine the mapping relationship table corresponding to the module to which the register object to be found belongs. The mapping relationship table includes the association relationship between the register object of the module corresponding to the mapping relationship table and the access address.

[0135] In one embodiment, the chip simulation model generation device 600 further includes:

[0136] The query module 604 is used to receive a register access request, where the access request is used to request access to a target register object, where the target register object is any register object in the chip simulation model; according to the pointer array, a mapping relationship table corresponding to the module to which the target register object belongs is searched; according to the mapping relationship table corresponding to the module to which the target register object belongs, an access address of the target register object is determined; and the target register object is accessed in the chip simulation model using the access address of the target register object.

[0137] In one embodiment, the query module 604 is specifically used to search the mapping relationship table corresponding to the module to which the target register object belongs according to the first address of the mapping relationship table corresponding to each module stored in the pointer array.

[0138] In one embodiment, the query module 604 is specifically configured to determine the access address of the target register object by using a binary search algorithm in a mapping relationship table corresponding to the module to which the target register object belongs.

[0139] In one of the embodiments, the chip simulation model is also provided with an external interface.

[0140] The chip simulation model generation device 600 also includes:

[0141] The access module 605 is used to access the chip simulation model to the external test software through the external interface, so that the external test software calls the chip simulation model to perform software debugging.

[0142] Each module in the above-mentioned chip simulation model generation device can be implemented in whole or in part by software, hardware and their combination. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0143] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Fig.10As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a method for generating a chip simulation model is implemented.

[0144] The display unit of the computer device is used to form a visually visible picture, and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a key, trackball, or touchpad provided on the computer device housing, or an external keyboard, touchpad, or mouse, etc.

[0145] Those skilled in the art will understand that Fig.10 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0146] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the above-mentioned chip simulation model generation method when executing the computer program.

[0147] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the method for generating the chip simulation model is implemented.

[0148] In one embodiment, a computer program product is provided, including a computer program, which implements the above-mentioned method for generating a chip simulation model when executed by a processor.

[0149] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0150] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0151] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for generating a chip simulation model, characterized in that: The method comprises: Obtain configuration files of various modules of the chip to be modeled, where the configuration files are used to describe registers of the modules corresponding to the configuration files; Parsing the configuration files of the modules to determine the register information of the modules; Generate a register object in the chip simulation model and index data of the register object according to the register information of each module, wherein the index data is used to search for the register object in the chip simulation model; The chip simulation model is generated according to the register objects in the chip simulation model and the index data of the register objects.

2. The method according to claim 1, characterized in that The index data includes a pointer array and a mapping relationship table corresponding to each module. The pointer array is used to determine the mapping relationship table corresponding to the module to which the register object to be found belongs. The mapping relationship table includes the association relationship between the register object of the module corresponding to the mapping relationship table and the access address.

3. The method according to claim 2, characterized in that After generating the chip simulation model according to the register objects in the chip simulation model and the index data of the register objects, the method further includes: Receive a register access request, wherein the access request is used to request access to a target register object, and the target register object is any register object in the chip simulation model; According to the pointer array, searching for a mapping relationship table corresponding to the module to which the target register object belongs; Determine the access address of the target register object according to the mapping relationship table corresponding to the module to which the target register object belongs; The target register object is accessed in the chip simulation model using the access address of the target register object.

4. The method according to claim 3, characterized in that The step of searching, according to the pointer array, a mapping relationship table corresponding to the module to which the target register object belongs comprises: According to the first address of the mapping relationship table corresponding to each module stored in the pointer array, the mapping relationship table corresponding to the module to which the target register object belongs is searched.

5. The method according to claim 3, characterized in that: The step of determining the access address of the target register object according to a mapping relationship table corresponding to the module to which the target register object belongs includes: In the mapping relationship table corresponding to the module to which the target register object belongs, a binary search algorithm is used to determine the access address of the target register object.

6. The method according to any one of claims 1 to 5, characterized in that: The chip simulation model is also provided with an external interface; After generating the chip simulation model according to the register objects in the chip simulation model and the index data of the register objects, the method further includes: The chip simulation model is connected to the external test software through the external interface, so that the external test software calls the chip simulation model to perform software debugging.

7. A device for generating a chip simulation model, characterized in that: The device comprises: An acquisition module is used to acquire configuration files of various modules of the chip to be modeled, wherein the configuration files are used to describe registers of the modules corresponding to the configuration files; A parsing module, used to parse the configuration files of the modules and determine the register information of the modules; A generation module is used to generate register objects in the chip simulation model and index data of the register objects according to the information of the registers of the various modules, and the index data is used to search for the register objects in the chip simulation model; the chip simulation model is generated according to the register objects in the chip simulation model and the index data of the register objects.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

Images