Standard cell memory and chip

Abstract

The invention provides a standard cell memory and a chip, and the memory comprises an input latch module which carries out the latch output of a source enable signal, an address signal and a data signal; the address decoding control module is used for generating a write-in enable signal and a read-out enable signal based on the source enable signal and the address signal; the data storage module comprises a first storage unit and a second storage unit, the first storage unit and the second storage unit are arranged into a storage array based on a checkerboard pattern, enabling ends of the storage units in the same row are cascaded through an external phase inverter and receive selective writing enabling bits of the corresponding row, and data ends of the storage units in the same column are cascaded through an internal phase inverter and receive corresponding data bits; storing each data bit into each storage unit of the corresponding row based on the corresponding row write selection enabling bit; and the data reading module comprises a column reading unit and is used for reading the data bits in the storage units of the corresponding rows in a layered reading manner. According to the invention, the problem that the dynamic power consumption of the existing standard cell memory is increased along with the increase of the design capacity is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of digital integrated circuit design, and in particular relates to a standard unit memory and a chip. Background Art

[0002] With the development of IoT applications, the demand for low-power chip applications continues to increase. Ultra-low operating voltage design has become a new type of low-power design solution, which reduces chip power consumption by reducing the operating voltage. The common static random access memory (SRAM) with wordline charge and discharge structure cannot further reduce the operating voltage because its minimum operating voltage is higher than other digital circuits. In order to solve this technical problem, a memory based on standard cell design, namely, standard cell memory (SCM) is proposed; compared with conventional SRAM-type designs, SCM can be designed based on standard logic processes and can provide lower operating voltage and lower power consumption; however, as the design capacity increases, the signal load increases, resulting in increased dynamic power consumption, which is not conducive to achieving low power consumption.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a standard cell memory and a chip for solving the problem that the dynamic power consumption of the prior standard cell memory increases with the increase of the design capacity.

[0005] In order to achieve the above-mentioned object and other related objects, the present invention provides a standard cell memory, wherein the standard cell memory comprises:

[0006] An input latch module is used to latch and output the source enable signal, address signal and data signal at the effective transition edge of the clock signal;

[0007] an address decoding control module, receiving the source enable signal and the address signal, and generating a write enable signal and a read enable signal based on the source enable signal and the address signal, wherein the write enable signal includes a plurality of row select write enable bits, and the row select write enable bits of the even rows and the row select write enable bits of the odd rows have opposite effective potentials;

[0008] A data storage module, comprising a plurality of first storage units and a plurality of second storage units, both of which are arranged into a storage array based on a checkerboard pattern, the enable end of each storage unit in the same row is cascaded through an external inverter and receives a corresponding row select write enable bit, and the data end of each storage unit in the same column is cascaded through an internal inverter and receives a corresponding data bit in the data signal, so as to store each data bit in the data signal in each storage unit of the corresponding row based on the corresponding row select write enable bit, wherein the storage control mode of the first storage unit and the second storage unit is opposite;

[0009] The data readout module includes a plurality of column readout units corresponding to each column in the storage array. Each column readout unit receives the readout enable signal and reads the data bits in each storage unit of the corresponding row in a hierarchical readout manner under the control of the readout enable signal.

[0010] Optionally, the address decoding control module includes:

[0011] An address decoding unit receives the address signal and decodes the address signal to generate the readout enable signal, wherein the readout enable signal includes a plurality of row select read enable bits;

[0012] The write enable unit includes a plurality of first enable generation units and a plurality of second enable generation units, which are arranged at row intervals and perform opposite logical operations; each enable generation unit corresponds one-to-one to each row select read enable bit and receives the source enable signal to generate a corresponding row select write enable bit by performing a corresponding logical operation on the source enable signal and the corresponding row select read enable bit.

[0013] Optionally, the address decoding unit comprises a hot decoder.

[0014] Optionally, the effective potential of the row select write enable bit of the even row is a high potential, and the effective potential of the row select write enable bit of the odd row is a low potential; wherein the first enable generation unit includes a two-input AND gate, and the second enable generation unit includes a two-input NAND gate.

[0015] Optionally, the first storage unit is implemented based on an AND-NOR unit, and the second storage unit is implemented based on an OR-NAND unit; wherein, the first storage unit stores data when the enable terminal is connected to a high potential, and the second storage unit stores data when the enable terminal is connected to a low potential.

[0016] Optionally, the first storage unit includes a first AND-OR-N unit, a second AND-OR-N unit and a first internal inverter; the first input end of the first AND-OR-N unit is connected to the first input end of the second AND-OR-N unit via the first internal inverter and serves as the first data end of the first storage unit, the second input end of the first AND-OR-N unit is connected to the second input end of the second AND-OR-N unit and serves as the enable end of the first storage unit, the third input end of the first AND-OR-N unit is connected to the output end of the second AND-OR-N unit, the output end of the first AND-OR-N unit serves as the first output end of the first storage unit, the first input end of the second AND-OR-N unit serves as the second data end of the first storage unit, the third input end of the second AND-OR-N unit is connected to the output end of the first AND-OR-N unit, and the output end of the second AND-OR-N unit serves as the second output end of the first storage unit.

[0017] Optionally, the second storage unit includes a first OR NAND unit, a second OR NAND unit and a second internal inverter; the first input end of the first OR NAND unit is connected to the first input end of the second OR NAND unit via the second internal inverter and serves as the first data end of the second storage unit, the second input end of the first OR NAND unit is connected to the second input end of the second OR NAND unit and serves as the enable end of the second storage unit, the third input end of the first OR NAND unit is connected to the output end of the second OR NAND unit, the output end of the first OR NAND unit serves as the first output end of the second storage unit, the first input end of the second OR NAND unit serves as the second data end of the second storage unit, the third input end of the second OR NAND unit is connected to the output end of the first OR NAND unit, and the output end of the second OR NAND unit serves as the second output end of the second storage unit.

[0018] Optionally, the output modes of each storage unit in the even column and each storage unit in the odd column are opposite, wherein each storage unit in the even column adopts a positive output mode, and each storage unit in the odd column adopts a negative output mode; in the positive output mode, the first output end of the first storage unit serves as an inverting output end and the second output end serves as a positive output end, and the first output end of the second storage unit serves as a positive output end and the second output end serves as an inverting output end; in the negative output mode, the first output end of the first storage unit serves as a positive output end and the second output end serves as an inverting output end, and the first output end of the second storage unit serves as an inverting output end and the second output end serves as a positive output end.

[0019] Optionally, the column read-out unit includes a starting level read-out unit, at least one even level read-out unit and at least one odd level read-out unit, each level read-out unit is cascaded, and the even level read-out unit and the odd level read-out unit are arranged at intervals; wherein the hierarchical level of the column read-out unit is determined by the bit width of the read-out enable signal.

[0020] Optionally, the starting level read-out unit includes at least one of a first combinational logic unit and a second combinational logic unit, the first combinational logic unit includes two two-input AND gates and one two-input NOR gate, and the second combinational logic unit includes three two-input AND gates and one three-input NOR gate, wherein the number of each combinational logic unit is determined by the input bit width of the starting level read-out unit.

[0021] Optionally, the even-level readout unit includes at least one of a two-input NOR gate, a three-input NOR gate and a four-input NOR gate, wherein the number of each NOR gate is determined by the input bit width of the even-level readout unit.

[0022] Optionally, the odd-level readout unit includes at least one of a two-input NAND gate, a three-input NAND gate and a four-input NAND gate, wherein the number of each NAND gate is determined by the input bit width of the odd-level readout unit.

[0023] Optionally, when the hierarchical number of the column read-out unit is an odd number, the column read-out unit reads the corresponding data bit from the inverting output end of each storage unit in the corresponding column; when the hierarchical number of the column read-out unit is an even number, the column read-out unit reads the corresponding data bit from the non-inverting output end of each storage unit in the corresponding column.

[0024] The present invention further provides a chip, comprising: the standard unit memory as described in any one of the above items.

[0025] As described above, the standard cell memory and chip of the present invention, through the design of input latch module, address decoding control module, data storage module and data readout module, uses a checkerboard method for data storage and adopts a cascade inverter method for signal transmission, which can improve the quality of cascade input signal, reduce signal load, thereby achieving the effect of reducing transient conduction current and dynamic power consumption, and reads data through a hierarchical readout method, thereby reducing the readout logic delay. The present invention is designed by standard cells and can work based on the minimum operating voltage of the standard cell library, thereby reducing the power consumption required for work, and is suitable for low-power application scenarios; compared with conventional SRAM memory, the present invention can reduce the mask input, thereby reducing product costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a schematic diagram of the structure of a standard cell memory in an embodiment of the present invention.

[0027] Figure 2 Shown is a schematic structural diagram of an input latch module in an embodiment of the present invention.

[0028] Figure 3 Shown is a structural schematic diagram of an address decoding control module in an embodiment of the present invention.

[0029] Figure 4 It is a schematic diagram of the structure of a data storage module in an embodiment of the present invention.

[0030] Figure 5 Shown is a schematic diagram of the structure of an AND or NOR unit in an embodiment of the present invention.

[0031] Figure 6 Shown is a structural schematic diagram of an OR-NAND unit in an embodiment of the present invention.

[0032] Figure 7 Shown is a schematic structural diagram of a first storage unit in an embodiment of the present invention.

[0033] Figure 8 Shown is a schematic structural diagram of a second storage unit in an embodiment of the present invention.

[0034] Fig. 9 Shown is a structural schematic diagram of a data readout module in an embodiment of the present invention.

[0035] Component number description

[0036] 10 Standard Cell Memory

[0037] 100 Input Latch Module

[0038] 110 Enable latch unit

[0039] 120 Address latch unit

[0040] 130 Data latch unit

[0041] 200 Address decoding control module

[0042] 210 Address decoding unit

[0043] 220 Write enable unit

[0044] 221 First enabling generation unit

[0045] 222 Second enabling generation unit

[0046] 300 Data Storage Module

[0047] 310 First storage unit

[0048] 311 First AND or NOT unit

[0049] 312 Second AND / OR NOT unit

[0050] 313 First internal inverter

[0051] 320 Second storage unit

[0052] 321 First OR and NOT unit

[0053] 322 Second OR and NOT unit

[0054] 323 Second internal inverter

[0055] 330 External Inverter

[0056] 400 Data readout module

[0057] 410 column readout unit

[0058] 411 Initial level readout unit

[0059] 411a First combinational logic unit

[0060] 411b Second combinational logic unit

[0061] 412 Even-level readout unit

[0062] 413 Odd-number layer readout unit DETAILED DESCRIPTION

[0063] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0064] See also Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the form, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0065] like Figures 1 to 9 As shown, this embodiment provides a standard cell memory 10 , including an input latch module 100 , an address decoding control module 200 , a data storage module 300 and a data reading module 400 .

[0066] like Figure 1 and Figure 2As shown, the input latch module 100 is used to latch and output the source enable signal EN, the address signal AIN and the data signal DIN respectively at the valid transition edge (for example, the rising edge) of the clock signal CK.

[0067] Specifically, Figure 2 As shown, the input latch module 100 includes an enable latch unit 110, an address latch unit 120, and a data latch unit 130. The enable latch unit 110 is used to latch and output the source enable signal EN at the rising edge of the clock signal CK, the address latch unit 120 is used to latch and output each address bit in the address signal AIN in sequence at the rising edge of the clock signal CK, and the data latch unit 130 is used to latch and output each data bit in the data signal DIN in sequence at the rising edge of the clock signal CK. In one example, the enable latch unit 110, the address latch unit 120, and the data latch unit 130 are all implemented by D flip-flops; of course, the enable latch unit 110, the address latch unit 120, and the data latch unit 130 can also be implemented by other logic circuits with latch output functions, without limitation.

[0068] like Figure 1 and Figure 3 As shown, the address decoding control module 200 receives a source enable signal EN and an address signal AIN, and generates a write enable signal WRE and a read enable signal RDE based on the source enable signal EN and the address signal AIN, wherein the write enable signal WRE includes a number of row select write enable bits WRE[0] to WRE[n], and the effective potentials of the row select write enable bits of the even rows and the row select write enable bits of the odd rows are opposite; in one example, the effective potential of the row select write enable bits of the even rows is a high potential, and the effective potential of the row select write enable bits of the odd rows is a low potential.

[0069] Specifically, Figure 3As shown, the address decoding control module 200 includes an address decoding unit 210 and a write enable unit 220. The address decoding unit 210 receives an address signal AIN, and decodes the address signal AIN to generate a read enable signal RDE, wherein the read enable signal RDE includes a number of row select read enable bits RDE[0] to RDE[n]. In one example, the address decoding unit 210 includes a hot code decoder, which converts the input based on the hot code encoding into a binary coded output, and in the binary coded output, that is, RDE[0] to RDE[n], the high potential is the effective potential; in fact, the bit width of the read enable signal RDE is the addressing number, wherein the selected address is a high potential, and the unselected address is a low potential. The write enable unit 220 includes a plurality of first enable generating units 221 and a plurality of second enable generating units 222, which are arranged at intervals in rows and perform opposite logic operations; each enable generating unit corresponds to each row select read enable bit and receives a source enable signal EN, so as to generate a corresponding row select write enable bit by performing a corresponding logic operation on the source enable signal EN and the corresponding row select read enable bit. In one example, the first enable generating unit 221 includes a two-input AND gate, the first input end is connected to the corresponding row select read enable bit, the second input end is connected to the source enable signal EN, and the output end generates the corresponding row select write enable bit; the second enable generating unit 22 includes a two-input NAND gate, the first input end is connected to the corresponding row select read enable bit, the second input end is connected to the source enable signal EN, and the output end generates the corresponding row select write enable bit.

[0070] Take the write enable unit 220 including four first enable generation units 221 and four second enable generation units 222 as an example: when performing a read operation, the source enable signal EN=0, and the address decoding unit 210 generates a read enable signal RDE. At this time, WRE[0]~WRE[7] are 01010101, and each row select write enable bit is invalid; when performing a write operation, the source enable signal EN=1, if RDE[0]~RDE[7] is 10000000, then WRE[0]~WRE[7] is 11010101, among which the row select write enable bit WRE[0] is valid, and the other row select write enable bits are invalid. It should be noted that when the first enable generation unit 221 and the second enable generation unit 222 are arranged in rows, the row number starts from 0. At this time, the first enable generation unit 221 is located in an even row and the second enable generation unit 222 is located in an odd row. In fact, in the memory of this embodiment, as long as the row number and column number are involved, they all start from 0.

[0071] like Figure 1 and Figure 4As shown, the data storage module 300 includes a plurality of first storage units 310 and a plurality of second storage units 320, which are arranged into a storage array based on a checkerboard pattern, the enable end of each storage unit in the same row is cascaded through an external inverter 330 and receives a corresponding row select write enable bit, and the data end of each storage unit in the same column is cascaded through an internal inverter and receives a corresponding data bit in a data signal DIN, so as to store each data bit in the data signal DIN in each storage unit of the corresponding row based on the corresponding row select write enable bit, wherein the storage control methods of the first storage unit 310 and the second storage unit 320 are opposite; in one example, the first storage unit 310 performs data storage when the enable terminal is connected to a high potential, and the second storage unit 320 performs data storage when the enable terminal is connected to a low potential. In the above-mentioned data storage module 300, the first storage unit 310 and the second storage unit 320 store data in a checkerboard manner, and use a cascade inverter method to transmit the data signal DIN and the write enable signal WRE, so that the load fan-out of each level is fixed, avoiding the continuous leakage current caused by the slow flipping of the input signal as the data scale increases, so that it is more suitable for large-scale expansion of the circuit; and by using a cascade method to transmit signals, the logic signals are flipped one by one, and the power supply reduces the concurrent load, which is beneficial to reduce transient power consumption.

[0072] When the first storage unit 310 and the second storage unit 320 are arranged based on a checkerboard pattern to obtain a storage array, the position of each storage unit can be represented by a combination of (row number, column number), then: the first storage unit 310 is arranged at a position where both the row number and the column number are even or odd, and the second storage unit 320 is arranged at a position where only one of the row number and the column number is an odd number; taking a 4×4 storage array as an example, the position of each storage unit can be represented as (0, 0), (0, 1), (0, 2), (0, 3), (1, 0), (1, 1), ( 1,2), (1,3), (2,0), (2,1), (2,2), (2,3), (3,0), (3,1), (3,2), (3,3), wherein the first storage unit 310 is arranged at the position (0,0), (0,2), (1,1), (1,3), (2,0), (2,2), (3,1), (3,3), and the second storage unit 320 is arranged at the position (0,1), (0,3), (1,0), (1,2), (2,1), (2,3), (3,0), (3,2). In addition, the enable terminals of the storage cells in the same row are cascaded via the external inverter 330 to receive the corresponding write enable bit, that is, in the same row, the enable terminal of the first storage cell receives the corresponding write enable bit, and the enable terminal of the next storage cell is connected to the enable terminal of the previous storage cell via the external inverter 330, for example, the enable terminal of the second storage cell is connected to the enable terminal of the first storage cell via the external inverter, and the enable terminal of the third storage cell is connected to the enable terminal of the second storage cell via the external inverter, and so on; the data terminals of the storage cells in the same column are cascaded via the internal inverter to receive the corresponding data bit, that is, in the same column, the first data terminal of the first storage cell receives the corresponding data bit, and the first data terminal of the current storage cell is connected to its second data terminal and to the first data terminal of the next storage cell via the internal inverter, for example, the first data terminal of the first storage cell is connected to its second data terminal and the first data terminal of the second storage cell via the internal inverter, and the first data terminal of the second storage cell is connected to its second data terminal and the first data terminal of the third storage cell via the internal inverter, and so on.

[0073] Specifically, the first storage unit 310 is implemented based on an AND-OR-NOT (AOI) unit, and the second storage unit 320 is implemented based on an OR-AND-NOT (OAI) unit. The AND-OR-NOT (AOI) unit includes a two-input AND gate AND and a two-input NOR gate XOR. Figure 5As shown; wherein, the first input end of the two-input AND gate AND serves as the first input end IN1 of the AND-OR-NON (AOI) unit, the second input end of the two-input AND gate AND serves as the second input end IN2 of the AND-OR-NON (AOI) unit, the output end of the two-input AND gate AND is connected to the first input end of the two-input NOR gate XOR, the second input end of the two-input NOR gate XOR serves as the third input end IN3 of the AND-OR-NON (AOI) unit, and the output end of the two-input NOR gate XOR serves as the output end OUT of the AND-OR-NON (AOI) unit. The AND-OR-NON (OAI) unit includes a two-input OR gate OR and a two-input NAND gate NAND, as shown Figure 6 As shown; wherein, the first input end of the two-input OR gate OR serves as the first input end IN1 of the OR-NAND (OAI) unit, the second input end of the two-input OR gate OR serves as the second input end IN2 of the OR-NAND (OAI) unit, the output end of the two-input OR gate OR is connected to the first input end of the two-input NAND gate NAND, the second input end of the two-input NAND gate NAND serves as the third input end IN3 of the OR-NAND (OAI) unit, and the output end of the two-input NAND gate NAND serves as the output end OUT of the OR-NAND (OAI) unit.

[0074] In one example, if Figure 7 As shown, the first storage unit 310 includes a first AND-OR-NOT (AOI) unit 311, a second AND-OR-NOT (AOI) unit 312 and a first internal inverter 313; wherein the first input end of the first AND-OR-NOT (AOI) unit 311 is connected to the first input end of the second AND-OR-NOT (AOI) unit 312 via the first internal inverter 313, the first input end of the first AND-OR-NOT (AOI) unit 311 also serves as the first data end of the first storage unit 310, the second input end of the first AND-OR-NOT (AOI) unit 311 is connected to the second input end of the second AND-OR-NOT (AOI) unit 312 and serves as the first storage unit 310. The first storage unit 310 is connected to the enable terminal of the first AND-OR-NON (AOI) unit 311, the third input terminal of the first AND-OR-NON (AOI) unit 311 is connected to the output terminal of the second AND-OR-NON (AOI) unit 312, the output terminal of the first AND-OR-NON (AOI) unit 311 is used as the first output terminal of the first storage unit 310, the first input terminal of the second AND-OR-NON (AOI) unit 312 is used as the second data terminal of the first storage unit 310, the third input terminal of the second AND-OR-NON (AOI) unit 312 is connected to the output terminal of the first AND-OR-NON (AOI) unit 311, and the output terminal of the second AND-OR-NON (AOI) unit 312 is used as the second output terminal of the first storage unit 310. The first storage unit 310 stores data when the enable terminal is connected to a high potential, and retains data when the enable terminal is connected to a low potential.

[0075] In one example, if Figure 8As shown, the second storage unit 320 includes a first or NAND (OAI) unit 321, a second or NAND (OAI) unit 322 and a second internal inverter 323; wherein the first input end of the first or NAND (OAI) unit 321 is connected to the first input end of the second or NAND (OAI) unit 322 via the second internal inverter 323, the first input end of the first or NAND (OAI) unit 321 also serves as the first data end of the second storage unit 320, the second input end of the first or NAND (OAI) unit 321 is connected to the second input end of the second or NAND (OAI) unit 322 and serves as the second storage unit The first or NAND (OAI) unit 321 is connected to the enable terminal of the second storage unit 320, the third input terminal of the first or NAND (OAI) unit 321 is connected to the output terminal of the second or NAND (OAI) unit 322, the output terminal of the first or NAND (OAI) unit 321 is used as the first output terminal of the second storage unit 320, the first input terminal of the second or NAND (OAI) unit 322 is used as the second data terminal of the second storage unit 320, the third input terminal of the second or NAND (OAI) unit 322 is connected to the output terminal of the first or NAND (OAI) unit 321, and the output terminal of the second or NAND (OAI) unit 322 is used as the second output terminal of the second storage unit 320. The second storage unit 320 stores data when the enable terminal is connected to a low potential, and retains data when the enable terminal is connected to a high potential.

[0076] In the above-mentioned data storage module 300, the effective potentials of the input enable signal of the even row (i.e., the corresponding row select write enable bit connected) and the input enable signal of the odd row (i.e., the corresponding row select write enable bit connected) are opposite, wherein the effective potential of the input enable signal of the even row is a high potential, and the effective potential of the input enable signal of the odd row is a low potential. In addition, the output modes of the storage cells in the even columns and the storage cells in the odd columns are opposite, wherein the storage cells in the even columns adopt a positive output mode, and the storage cells in the odd columns adopt a negative output mode; for the first storage cell 310: in the positive output mode, the first output end of the first storage cell 310 serves as the negative output end QB and the second output end serves as the positive output end Q, and in the negative output mode, the first output end of the first storage cell 310 serves as the positive output end Q and the second output end serves as the negative output end QB; for the second storage cell 320: in the positive output mode, the first output end of the second storage cell 320 serves as the positive output end Q and the second output end serves as the negative output end QB, and in the negative output mode, the first output end of the second storage cell 320 serves as the negative output end QB and the second output end serves as the positive output end Q.

[0077] When performing a write operation, if WRE[0]~WRE[7] are 11010101, that is, the row select write enable bit WRE[0] is valid and the other row select write enable bits are invalid, then: the storage cells in row 0 are enabled and store the data bits, and the storage cells in the other rows are not enabled.

[0078] like Figure 1 and Fig. 9 As shown, the data read module 400 includes a plurality of column read units 410 corresponding one to each column in the storage array; each column read unit 410 receives a read enable signal RDE, and under the control of the read enable signal RDE, reads the data bits in each storage cell of the corresponding row in a hierarchical read manner, thereby reducing the read logic delay.

[0079] Specifically, Fig. 9 As shown, the column readout unit 410 includes a starting level readout section 411, at least one even level readout section 412 and at least one odd level readout section 413, wherein each level readout section is cascaded, and the even level readout section 412 and the odd level readout section 413 are arranged alternately. In fact, the number of even level readout sections 412 and odd level readout sections 413 determines the hierarchical level of the column readout unit 410, wherein the hierarchical level of the column readout unit 410=1+the number of even level readout sections 412+the number of odd level readout sections 413; and the hierarchical level of the column readout unit 410 is determined by the bit width (i.e., the addressing number) of the readout enable signal RDE, wherein the bit width of the readout enable signal RDE increases, and the hierarchical level of the column readout unit 410 increases. In application, if the hierarchical level number of the column read-out unit 410 is an odd number, then: the column read-out unit 410 reads the corresponding data bit from the inverting output end of each storage cell in the corresponding column, that is, the input end of the starting level read-out unit 411 in the column read-out unit 410 is connected to the inverting output end of each storage cell in the corresponding column; if the hierarchical level number of the column read-out unit 410 is an even number, then: the column read-out unit 410 reads the corresponding data bit from the positive output end of each storage cell in the corresponding column, that is, the input end of the starting level read-out unit 411 in the column read-out unit 410 is connected to the positive output end of each storage cell in the corresponding column.

[0080] The starting level readout unit 411 includes at least one of a first combinational logic unit 411a and a second combinational logic unit 411b; in one example, the first combinational logic unit 411a includes two two-input AND gates and one two-input NOR gate, wherein the input ends of the two two-input AND gates serve as the input ends of the first combinational logic unit 411a, the output ends of the two two-input AND gates are respectively connected to the input ends of the two-input NOR gates, and the output end of the two-input NOR gate serves as the output end of the first combinational logic unit 411a; the second combinational logic unit 411b includes three two-input AND gates and one three-input NOR gate, wherein the input ends of the three two-input AND gates serve as the input ends of the second combinational logic unit 411b, the output ends of the three two-input AND gates are respectively connected to the input ends of the three-input NOR gates, and the output end of the three-input NOR gate serves as the output end of the second combinational logic unit 411b. In fact, the number of each combinational logic unit is determined by the input bit width of the starting-level readout unit 411, that is, by the bit width of the readout enable signal RDE; in application, if the remainder after the bit width of the readout enable signal RDE is divided by 3 is 0, that is, it is an integer, then all the second combinational logic units 411b are used in the starting-level readout unit 411; if the remainder after the bit width of the readout enable signal RDE is divided by 3 is 1, then in the starting-level readout unit 411, 2 first combinational logic units 411a are used, and the rest use the second combinational logic units 411b; if the remainder after the bit width of the readout enable signal RDE is divided by 3 is 2, then in the starting-level readout unit 411, 1 first combinational logic unit 411a is used, and the rest use the second combinational logic units 411b. It should be noted that the connection method between the starting level readout unit 411 and the previous stage circuit is through a two-input AND gate, wherein the two input ends of each two-input AND gate receive the corresponding row select enable bit and the output of the corresponding storage unit respectively, and whether the positive output end or the negative output end of the corresponding storage unit is connected is determined by the hierarchical level of the column readout unit 410.

[0081] The even-level readout unit 412 includes at least one of a two-input NOR gate, a three-input NOR gate, and a four-input NOR gate, wherein the input end of each NOR gate serves as the input end of the even-level readout unit 412 and is connected to the output end of the starting-level readout unit 411 or the output end of the previous-level odd-level readout unit 413, and the output end of each NOR gate serves as the output end of the even-level readout unit 412. In fact, the number of each NOR gate is determined by the input bit width of the even-level readout unit 412; in application, if the remainder after the input bit width of the even-level readout unit 412 is divided by 4 is 0, that is, it is an integer divisible, then all four-input NOR gates are used in the even-level readout unit 412; if the remainder after the input bit width of the even-level readout unit 412 is divided by 4 is 1, then 1 two-input NOR gate and 1 If the input bit width of the even-level readout unit 412 is divided by 4 and the remainder is 2, then in the even-level readout unit 412, 1 two-input NOR gate is used, and the rest use four-input NOR gates; if the input bit width of the even-level readout unit 412 is divided by 4 and the remainder is 3, then in the even-level readout unit 412, 1 three-input NOR gate is used, and the rest use four-input NOR gates.

[0082] The odd-level readout unit 413 includes at least one of a two-input NAND gate, a three-input NAND gate, and a four-input NAND gate, wherein the input end of each NAND gate serves as the input end of the odd-level readout unit 413 and is connected to the output end of the previous even-level readout unit 412, and the output end of each NAND gate serves as the output end of the odd-level readout unit 413. In fact, the number of each NAND gate is determined by the input bit width of the odd-level readout unit 413; in application, if the remainder after the input bit width of the odd-level readout unit 413 is divided by 4 is 0, that is, it is an integer, then all four-input NAND gates are used in the odd-level readout unit 413; if the remainder after the input bit width of the odd-level readout unit 413 is divided by 4 is 1, then 1 two-input NAND gate and 1 three-input NAND gates are used, and the rest use four-input NAND gates; if the input bit width of the odd-level read-out unit 413 is divided by 4 and the remainder is 2, then in the odd-level read-out unit 413, one two-input NAND gate is used, and the rest use four-input NAND gates; if the input bit width of the odd-level read-out unit 413 is divided by 4 and the remainder is 3, then in the odd-level read-out unit 413, one three-input NAND gate is used, and the rest use four-input NAND gates.

[0083] When performing a read operation, if RDE[0]~RDE[7] is 10000000, that is, the row select read enable bit RDE[0] is valid and the other row select read enable bits are invalid, then: the storage unit in the 0th row in the corresponding column is read, thereby realizing the read operation of each storage unit in the 0th row.

[0084] The standard cell memory 10 of this embodiment is a digital integrated circuit, which can be applied to both chip-level design and IP (intellectual property core, referred to as IP core) level design. In addition, this embodiment can expand the memory capacity based on the combination of different configurations of address bit width and data bit width, wherein the logic gates involved are all common standard cells (implemented by calling corresponding devices in a commercial standard cell library or using other standard cells), and the circuit design can be completed through a standard digital design process; it can be seen that this embodiment supports memory capacity expansion and power consumption reduction.

[0085] Accordingly, this embodiment further provides a chip, including a standard cell memory 10, wherein the standard cell memory 10 is implemented using the structure described above. Of course, the chip may also include other device structures, which are not limited thereto.

[0086] In summary, a standard cell memory and chip of the present invention, through the design of input latch module, address decoding control module, data storage module and data readout module, uses a checkerboard method for data storage and adopts a cascade inverter method for signal transmission, which can improve the quality of cascade input signals and reduce signal load, thereby achieving the effect of reducing transient conduction current and dynamic power consumption, and reads data through a layered readout method, thereby reducing the readout logic delay. The present invention is designed with standard cells and can work based on the minimum operating voltage of the standard cell library, thereby reducing the power consumption required for work, and is suitable for low-power application scenarios; compared with conventional SRAM memory, the present invention can reduce mask investment, thereby reducing product costs. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0087] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A standard cell memory, characterized in that: The standard cell memory comprises: An input latch module is used to latch and output the source enable signal, address signal and data signal at the effective transition edge of the clock signal; an address decoding control module, receiving the source enable signal and the address signal, and generating a write enable signal and a read enable signal based on the source enable signal and the address signal, wherein the write enable signal includes a plurality of row select write enable bits, and the row select write enable bits of the even rows and the row select write enable bits of the odd rows have opposite effective potentials; A data storage module, comprising a plurality of first storage units and a plurality of second storage units, both of which are arranged into a storage array based on a checkerboard pattern, the enable end of each storage unit in the same row is cascaded through an external inverter and receives a corresponding row select write enable bit, and the data end of each storage unit in the same column is cascaded through an internal inverter and receives a corresponding data bit in the data signal, so as to store each data bit in the data signal in each storage unit of the corresponding row based on the corresponding row select write enable bit, wherein the storage control mode of the first storage unit and the second storage unit is opposite; The data readout module includes a plurality of column readout units corresponding to each column in the storage array. Each column readout unit receives the readout enable signal and reads the data bits in each storage unit of the corresponding row in a hierarchical readout manner under the control of the readout enable signal.

2. The standard cell memory according to claim 1, characterized in that: The address decoding control module comprises: An address decoding unit receives the address signal and decodes the address signal to generate the readout enable signal, wherein the readout enable signal includes a plurality of row select read enable bits; The write enable unit includes a plurality of first enable generation units and a plurality of second enable generation units, which are arranged at row intervals and perform opposite logical operations; each enable generation unit corresponds one-to-one to each row select read enable bit and receives the source enable signal to generate a corresponding row select write enable bit by performing a corresponding logical operation on the source enable signal and the corresponding row select read enable bit.

3. The standard cell memory according to claim 2, characterized in that: The address decoding unit includes a hot decoder.

4. The standard cell memory according to claim 2, characterized in that: The effective potential of the row select write enable bit of the even row is a high potential, and the effective potential of the row select write enable bit of the odd row is a low potential; wherein the first enable generation unit includes a two-input AND gate, and the second enable generation unit includes a two-input NAND gate.

5. The standard cell memory according to any one of claims 1 to 4, characterized in that: The first storage unit is implemented based on an AND-NOR unit, and the second storage unit is implemented based on an OR-NAND unit; wherein the first storage unit stores data when the enable terminal is connected to a high potential, and the second storage unit stores data when the enable terminal is connected to a low potential.

6. The standard cell memory according to claim 5, characterized in that: The first storage unit includes a first AND-OR-N unit, a second AND-OR-N unit and a first internal inverter; the first input end of the first AND-OR-N unit is connected to the first input end of the second AND-OR-N unit via the first internal inverter and serves as the first data end of the first storage unit, the second input end of the first AND-OR-N unit is connected to the second input end of the second AND-OR-N unit and serves as the enable end of the first storage unit, the third input end of the first AND-OR-N unit is connected to the output end of the second AND-OR-N unit, the output end of the first AND-OR-N unit serves as the first output end of the first storage unit, the first input end of the second AND-OR-N unit serves as the second data end of the first storage unit, the third input end of the second AND-OR-N unit is connected to the output end of the first AND-OR-N unit, and the output end of the second AND-OR-N unit serves as the second output end of the first storage unit.

7. The standard cell memory according to claim 5, characterized in that: The second storage unit includes a first OR NAND unit, a second OR NAND unit and a second internal inverter; the first input end of the first OR NAND unit is connected to the first input end of the second OR NAND unit via the second internal inverter and serves as the first data end of the second storage unit, the second input end of the first OR NAND unit is connected to the second input end of the second OR NAND unit and serves as the enable end of the second storage unit, the third input end of the first OR NAND unit is connected to the output end of the second OR NAND unit, the output end of the first OR NAND unit serves as the first output end of the second storage unit, the first input end of the second OR NAND unit serves as the second data end of the second storage unit, the third input end of the second OR NAND unit is connected to the output end of the first OR NAND unit, and the output end of the second OR NAND unit serves as the second output end of the second storage unit.

8. The standard cell memory according to claim 5, characterized in that: The output modes of each storage unit in the even column and each storage unit in the odd column are opposite, wherein each storage unit in the even column adopts a positive output mode, and each storage unit in the odd column adopts a negative output mode; in the positive output mode, the first output end of the first storage unit serves as an inverting output end and the second output end serves as a positive output end, and the first output end of the second storage unit serves as a positive output end and the second output end serves as an inverting output end; in the negative output mode, the first output end of the first storage unit serves as a positive output end and the second output end serves as an inverting output end, and the first output end of the second storage unit serves as an inverting output end and the second output end serves as a positive output end.

9. The standard cell memory according to claim 1, characterized in that: The column readout unit includes a starting level readout unit, at least one even level readout unit and at least one odd level readout unit, each level readout unit is cascaded, and the even level readout unit and the odd level readout unit are arranged at intervals; wherein the hierarchical level of the column readout unit is determined by the bit width of the readout enable signal.

10. The standard cell memory according to claim 9, characterized in that: The starting level read-out unit includes at least one of a first combinational logic unit and a second combinational logic unit, wherein the first combinational logic unit includes two two-input AND gates and one two-input NOR gate, and the second combinational logic unit includes three two-input AND gates and one three-input NOR gate, wherein the number of each combinational logic unit is determined by the input bit width of the starting level read-out unit.

11. The standard cell memory according to claim 9, characterized in that: The even-level readout unit includes at least one of a two-input NOR gate, a three-input NOR gate and a four-input NOR gate, wherein the number of each NOR gate is determined by the input bit width of the even-level readout unit.

12. The standard cell memory according to claim 9, characterized in that: The odd-level readout unit includes at least one of a two-input NAND gate, a three-input NAND gate, and a four-input NAND gate, wherein the number of each NAND gate is determined by the input bit width of the odd-level readout unit.

13. The standard cell memory according to any one of claims 9 to 12, characterized in that: When the hierarchical level number of the column readout unit is an odd number, the column readout unit reads the corresponding data bit from the inverting output end of each storage unit in the corresponding column; when the hierarchical level number of the column readout unit is an even number, the column readout unit reads the corresponding data bit from the non-inverting output end of each storage unit in the corresponding column.

14. A chip, characterized in that: The chip comprises: a standard cell memory as claimed in any one of claims 1 to 13.

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