TSV repairing system and method for 3D stacked chips
By using TSV current detection circuit and controller in 3D stacked chips to detect and repair abnormal TSV groups, the problem of low utilization of TSV repair resources in the prior art is solved, and the yield of the chip is improved.
Patent Information
- Application Number
- CN202411488739.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-23
- Publication Date
- 2025-03-11
AI Technical Summary
In the prior art, the repair resource utilization rate of TSV repair methods is low, resulting in a low chip yield.
It provides a TSV repair system with 3D stacked chips, including a TSV current detection circuit and a controller. By detecting the current values of each main TSV group in the TSV array, it determines whether the target TSV group is in an abnormal state, and transfers data to the remaining normal main TSV group or backup TSV group through the shift register module for repair.
Effectively save repair resources, improve the utilization rate of repair resources, and improve the yield of chips.
Smart Images
Figure CN119601066A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and in particular to a TSV repair system and method for 3D stacked chips. Background Art
[0002] With the development of integrated circuits, many applications have put forward requirements for miniaturization, high speed, high bandwidth and low power consumption of chips. As Moore's Law gradually becomes invalid, it has become a new trend to increase chip performance and reduce size and power consumption by adopting advanced packaging technology. Among them, 3D stacking packaging is to stack multiple chips or wafers, thin and etch the chips to form through silicon vias (TSV) to achieve interconnection between upper and lower chips, which can shorten the interconnection lines between chips and achieve high speed, low power consumption and small area requirements.
[0003] However, during the preparation process, due to process reasons, there may be defects such as insulation layer integrity defects, bump open circuits, and hole filling gaps. The unqualified TSV quality caused by these faults will affect the normal operation of the stacked chips. When performing TSV detection, the relevant technology usually detects the entire TSV chain. If it is found that the entire TSV chain has open circuits due to process defects, the entire TSV chain is replaced. In the case of limited chip area and limited spare TSV resources, spare TSV resources will be wasted, and limited resources cannot be used to repair more defective TSVs, resulting in low chip yield. Summary of the invention
[0004] The main purpose of the present application is to provide a TSV repair system and method for 3D stacked chips, which can at least solve the problem of low utilization rate of repair resources in TSV repair methods in related technologies, resulting in low chip yield.
[0005] To achieve the above-mentioned purpose, the first aspect of the present application provides a TSV repair system for 3D stacked chips, comprising: at least two stacked chips, at least one TSV array, at least one TSV current detection circuit and a controller, the chip comprising a shift register module, the two chips are associated through the TSV array, the TSV current detection circuit and the shift register module are respectively connected to the TSV array and the controller, the TSV module comprises a plurality of main TSV groups and a plurality of spare TSV groups; the TSV current detection circuit is used to: detect the current value of each main TSV group in the TSV array, and upload the current value to the controller; the controller is used to: if it is determined according to the current value that the corresponding target TSV group is in an abnormal state, then generate a corresponding control signal and transmit it to the corresponding shift register module; wherein the control signal is used to instruct the shift register module to transfer the data transmitted to the target TSV group to the remaining main TSV groups or the spare TSV groups in the TSV array that are in a normal state.
[0006] The second aspect of the present application provides a TSV repair method, including a TSV repair system for a 3D stacked chip as described in the first aspect of the present application, the TSV repair method comprising: a TSV current detection circuit detects the current value of each main TSV group in the TSV array, and uploads the current value to a controller; if the controller determines that the corresponding target TSV group is in an abnormal state based on the current value, a corresponding control signal is generated and transmitted to the corresponding shift register module; wherein the control signal is used to instruct the shift register module to transfer the data transmitted to the target TSV group to the remaining main TSV groups or spare TSV groups in the TSV array that are in a normal state.
[0007] From the above description, it can be seen that the present application detects the current of each main TSV group through a TSV current detection circuit, and then the controller determines whether the corresponding main TSV group is faulty based on the detected current. If the main TSV group is faulty, the data flowing through the faulty TSV group is transmitted to the remaining normal main TSV groups or spare TSV groups through the shift register module, that is, the faulty TSV group is replaced with the remaining normal main TSV groups or spare TSV groups, thereby effectively saving repair resources and improving the utilization rate of repair resources, so as to improve the yield of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.
[0009] Figure 1 is a structural schematic diagram of a first TSV repair system according to an embodiment of the present application; Figure 2 is a circuit schematic diagram of a TSV path selection circuit and a TSV current detection circuit according to an embodiment of the present application; Figure 3 is a structural schematic diagram of a second TSV repair system according to an embodiment of the present application; Figure 4 It is a basic flow chart of a TSV repair method according to an embodiment of the present application; Figure 5 Schematic diagram of the structure of the third TSV repair system of the embodiment of the present application. DETAILED DESCRIPTION
[0010] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.
[0011] In the related art, due to the low utilization rate of repair resources of the TSV repair method, the chip yield is low. Therefore, an embodiment of the present application provides a TSV repair system for 3D stacked chips.
[0012] like Figure 1 The figure shows a structural schematic diagram of a TSV repair system provided in an embodiment of the present application, wherein the TSV repair system includes: at least two stacked chips, at least one TSV array, at least one TSV current detection circuit and a controller, wherein the chip includes a shift register module, and the two chips are associated through the TSV array, and the TSV current detection circuit and the shift register module are respectively connected to the TSV array and the controller, and the TSV module includes a plurality of main TSV groups and a plurality of spare TSV groups.
[0013] Among them, the TSV current detection circuit is used to: detect the current value of each main TSV group in the TSV array, and upload the current value to the controller; the controller is used to: if it is determined according to the current value that the corresponding target TSV group is in an abnormal state, then generate a corresponding control signal and transmit it to the corresponding shift register module; wherein the control signal is used to instruct the shift register module to transfer the data transmitted to the target TSV group to the remaining main TSV groups or spare TSV groups in the TSV array that are in a normal state.
[0014] In this embodiment, every two stacked chips in the TSV repair system are interconnected through a TSV array. Each TSV array can be connected to one or more TSV current detection circuits. The current of each main TSV group in the TSV array is detected by the TSV current detection circuit, and then the controller determines whether the main TSV group is abnormal based on the acquired current value. If the main TSV group is abnormal, the data that originally needs to enter the abnormal main TSV group can be transmitted to the remaining normal main TSV groups or spare TSV groups in the TSV array through the shift register module. Each chip is designed with a shift register module, so that each chip can be repaired independently. Compared with the traditional repair method of replacing the entire TSV chain together, it can greatly save repair resources and improve the utilization rate of existing repair resources and the reliability of chips.
[0015] Furthermore, the TSV repair system also includes a plurality of TSV path selection circuits, each main TSV group includes at least two parallel sub-TSVs, each spare TSV group includes at least two parallel sub-spare TSVs, and the TSV path selection circuits are respectively connected to the corresponding main TSV groups and TSV current detection circuits.
[0016] In this embodiment, each main TSV group and spare TSV group in the TSV array is provided with at least two sub-TSVs, and multiple sub-TSVs are connected in parallel. When one of the TSVs fails, the remaining normal TSVs can be used to continue to transmit data to improve the reliability of the chip. Each main TSV group is connected to a TSV path selection circuit, and each TSV path selection circuit is connected in parallel. A TSV array can be provided with one or more TSV current detection circuits connected to the TSV path selection circuit. When there is a lot of TSV data, multiple TSV current detection circuits can be provided to improve the efficiency of detection, for example, n (n≥2) main TSV groups are used as a unit, and a TSV current detection circuit is provided for each unit.
[0017] like Figure 2 FIG. 1 is a schematic diagram of a TSV path selection circuit and a TSV current detection circuit provided by this embodiment. Figure 2The TSV path selection circuit includes a first switch tube P1, a second switch tube N1, a first inverter and a first transmission gate; the first end of the first switch tube P1 is connected to a power supply, the second end of the first switch tube P1 is connected to one end of the first inverter, the third end of the first switch tube P1 is connected to one end of the corresponding sub-TSV, the other end of the first inverter is connected to an external excitation signal generator, the first end of the second switch tube N1 is connected to the other end of the sub-TSV, the second end of the second switch tube N1 is connected to the TSV current detection circuit, the third end of the second switch tube N1 is grounded, and the first transmission gate is respectively connected to the first end and the second end of the second switch tube N1 and is used to connect to the excitation signal generator. Among them, the first inverter is used to: invert the first excitation signal transmitted by the excitation signal generator to obtain a second excitation signal, and transmit the second excitation signal to the first switch tube P1; wherein the second excitation signal is used to control the first switch tube P1 to enter the on state, and the first excitation signal is also used to control the second switch tube N1 to enter the on state through the first transmission gate.
[0018] In this embodiment, each sub-TSV is connected to a TSV path selection circuit, and each TSV path selection circuit is connected in parallel. The excitation signal generator can transmit an excitation signal to the corresponding TSV path selection circuit, so that the corresponding TSV path selection circuit enters a working state, and then the current flowing through the sub-TSV is detected by the TSV current detection circuit. Among them, the TSV path selection circuit includes a first switch tube P1 and a second switch tube N1. The first switch tube P1 can be a PMOS tube, and the second switch tube N1 can be an NMOS tube. When the test_1 transmitted by the excitation signal generator is a high level, the first inverter makes the first switch tube P1 and the second switch tube N1 both in a conducting state. At this time, the current flowing through the first switch tube P1 is I1, and the current flowing through the sub-TSV is also I1. The current I1 can be detected by the TSV current detection circuit.
[0019] For further information, see Figure 2 The TSV current detection circuit includes a fifth switch tube P3, a sixth switch tube N4 and a seventh switch tube N3; the first end of the fifth switch tube P3 is respectively connected to the power supply and the controller, the second end of the fifth switch tube P3 is respectively connected to the third end of the fifth switch tube P3 and the first end of the sixth switch tube N4, the second end of the sixth switch tube N4 is respectively connected to multiple TSV path selection circuits, the third end of the sixth switch tube N4 is grounded, and the seventh switch tube N3 is respectively connected to the second end and the third end of the sixth switch tube N4 and is used to connect to an external excitation signal generator; wherein, when the seventh switch tube N3 receives the fifth excitation signal transmitted by the excitation signal generator, the TSV current detection circuit enters a working state.
[0020] In this embodiment, the TSV current detection circuit can be used as a current mirror to load the current I1 flowing through the first switch tube P1. The TSV current detection circuit includes a fifth switch tube P3, a sixth switch tube N4 and a seventh switch tube N3, wherein the fifth switch tube P3 can be a PMOS tube, the sixth switch tube N4 can be an NMOS tube, and the seventh switch tube N3 can be an NMOS tube. The excitation generator transmits a high-level excitation signal test_enable to the seventh switch tube N3 to control the seventh switch tube N3 to be cut off, so that the TSV current detection circuit enters the working state, that is, the fifth switch tube P3 and the sixth switch tube N4 enter the conducting state, thereby mirroring the current I1 and transmitting it to the controller. By setting the TSV current detection circuit, the currents of multiple sub-TSVs can be quickly detected.
[0021] Further, see Figure 2 The TSV path selection circuit also includes a third switch tube P2, a fourth switch tube N2, a second inverter and a second transmission gate; the first end of the third switch tube P2 is connected to the power supply, the second end of the third switch tube P2 is connected to one end of the second inverter, the third end of the third switch tube P2 is connected to one end of the sub-TSV, the other end of the second inverter is connected to the excitation signal generator, the first end of the fourth switch tube N2 is connected to the other end of the sub-TSV, the second end of the fourth switch tube N2 is connected to the TSV current detection circuit, the third end of the fourth switch tube N2 is grounded, and the second transmission gate is respectively connected to the first end and the second end of the fourth switch tube N2 and is used to connect to the excitation signal generator. Among them, the second inverter is used to: invert the third excitation signal transmitted by the excitation signal generator to obtain a fourth excitation signal, and transmit the fourth excitation signal to the third switch tube P2; wherein the fourth excitation signal is used to control the third switch tube P2 to enter the on state, and the third excitation signal is also used to control the fourth switch tube N2 to enter the on state through the second transmission gate.
[0022] In this embodiment, since the first switch tube P1, the second switch tube N1, the fifth switch tube P3 and the sixth switch tube N4 are affected by the process and temperature, so that the judgment of the sub-TSV according to the current I1 is biased, a selection branch can be added to obtain different currents. In this embodiment, a selection branch is connected in parallel, that is, a third switch tube P2 is added in parallel with the first switch tube P1 and a fourth switch tube N2 is added in parallel with the second switch tube N1. The third switch tube P2 is the same as the first switch tube P1, both of which are PMOS tubes, and the fourth switch tube N2 is the same as the second switch tube N1, both of which are NMOS tubes. By setting the second excitation signal test_2 to a high level, the third switch tube P2 and the fourth switch tube N2 can both enter a conducting state. At this time, the current flowing through the first switch tube P1 and the third switch tube P2 is I2, and the current flowing through the sub-TSV is 2I2, which is then divided into the second switch tube N1 and the fourth switch tube N2. The current I2 is copied to the path of the fifth switch tube P3 through the current mirror circuit, so that the controller can determine whether the sub-TSV is faulty according to the currents I1 and I2.
[0023] like Figure 3 FIG. 1 is a schematic diagram of the structure of the second TSV repair system provided in this embodiment. Figure 3 The TSV repair system includes multiple stacked chips, multiple TSV arrays and multiple TSV current detection circuits. Two adjacent chips are associated through the TSV array. The TSV array is connected to at least one TSV current detection circuit. The shift register module in the first chip is connected to the corresponding TSV array and is used to connect to an external data source generator. The shift register module in the last chip is connected to the corresponding TSV array and is used to connect to an external data processing device. The shift register module in the middle chip is respectively connected to one end of the two corresponding TSV arrays.
[0024] In this embodiment, taking a four-layer stacked chip as an example, every two adjacent layers of chips are directly associated through a TSV array, and a shift register module is designed in each layer of chips. The shift register module in the first layer, i.e., the first layer chip, is used to receive data transmitted by an external data source generator, and transmits the data to each main TSV group in the TSV array between the first and second layer chips. The shift register module in the middle layer, i.e., the second layer chip, is used to receive data transmitted by the first layer main TSV, and transmits the data to each main TSV group in the TSV array between the second and third layer chips. The shift register in the last layer, i.e., the fourth layer chip, is used to receive data transmitted by each main TSV group in the TSV array between the third and fourth layer chips, and transmits it to an external data processing device. Among them, the shift register module in each layer of chips can be set to one or more.
[0025] The TSV repair system for 3D stacked chips provided in the embodiment of the present application detects the current of each main TSV group through a TSV current detection circuit, and then the controller determines whether the corresponding main TSV group is faulty based on the detected current. If the main TSV group is faulty, the data flowing through the faulty TSV group is transferred to the remaining normal main TSV groups or spare TSV groups through the shift register module, that is, the faulty TSV group is replaced with the remaining normal main TSV groups or spare TSV groups, thereby effectively saving repair resources and improving the utilization rate of repair resources, so as to improve the yield of the chip.
[0026] The present application also provides a TSV repair method, which is applied to the TSV repair system of the above 3D stacked chip. Figure 4 The basic process diagram of the TSV repair method shown in FIG. 1 includes: Step 401 : A TSV current detection circuit detects the current value of each main TSV group in a TSV array, and uploads the current value to a controller.
[0027] In some embodiments, the current value includes a first TSV current value and a second TSV current value, and the TSV current detection circuit detects the current value of each main TSV group in the TSV array, including: when the first switch tube and the second switch tube corresponding to the main TSV group are both in the on state, the TSV current detection circuit detects the first TSV current value; when the first switch tube, the second switch tube, the third switch tube and the fourth switch tube corresponding to the main TSV group are both in the on state, the TSV current detection circuit detects the second TSV current value.
[0028] In this embodiment, each main TSV group performs two current detections, the first current detection is obtained by controlling the first switch tube and the second switch tube to be closed, and the second current detection is obtained by controlling the first switch tube, the second switch tube, the third switch tube and the fourth switch tube to be closed. By applying excitation to the path corresponding to each main TSV group, the TSV current detection circuit can obtain the current value of each main TSV group.
[0029] Step 402: If the controller determines that the corresponding target TSV group is in an abnormal state according to the current value, a corresponding control signal is generated and transmitted to the corresponding shift register module.
[0030] In this embodiment, when the controller determines that the main TSV group is in an abnormal state based on the acquired current value, a corresponding control signal will be generated and transmitted to the shift register module corresponding to the abnormal main TSV group, wherein the control signal is used to instruct the shift register module to transfer the data transmitted to the target TSV group to the remaining main TSV groups or spare TSV groups in the TSV array that are in a normal state, thereby completing the repair of the abnormal TSV group.
[0031] In some embodiments, if the controller determines that the corresponding target TSV group is in an abnormal state based on the current value, a corresponding control signal is generated and transmitted to the corresponding shift register module, including: the controller calculates the impedance value of the corresponding target TSV group based on the first TSV current value and the second TSV current value; if the impedance value does not meet the corresponding preset reference impedance range, the controller determines that the target TSV group is in an abnormal state, and generates a corresponding control signal and transmits it to the corresponding shift register module.
[0032] In this embodiment, when the first current detection is performed on each main TSV group, that is, when both the first switch tube and the second switch tube are controlled to be turned on, the current flowing through the main TSV group is detected to be I1, and the controller uses the formula: The impedance of the main TSV group can be obtained, where R PMOS is the impedance of the first switch tube, R TSV is the impedance of the TSV to be calculated, R NMOS is the resistance value of the second switch tube, is the power supply voltage. Since the switch tube is affected by the process and temperature, the impedance R of the first switch tube PMOS , the impedance of the second switch tube R NMOS There will be deviations, resulting in deviations in the measured TSV impedance. Therefore, a second current detection can be performed, that is, the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are all controlled to be turned on. At this time, it is detected that the current flowing through the first switch tube and the third switch tube is I2, and the current flowing through the main TSV group is 2I2. The controller uses the formula: The impedance of the main TSV group can be obtained. Through two current detections, the impedance of the main TSV group can be calculated according to the following formula: By performing two current detections on the TSV, the measurement error caused by transistor deviation can be effectively eliminated, and the accuracy of TSV impedance calculation can be improved. After that, the impedance value of the main TSV group is compared with the preset reference impedance range, so that it can be determined whether the two sub-TSVs in the main TSV group are faulty. If both sub-TSVs are faulty, it can be determined that the main TSV group is in an abnormal state.
[0033] Furthermore, in some embodiments, the spare TSV group is located at the end of the row or column where the target TSV group is located, and after the corresponding control signal is generated and transmitted to the corresponding shift register module, it also includes: if the target TSV group is not the last main TSV group, the shift register module transmits the data transmitted to the target TSV group to any sub-TSV in the corresponding normal main TSV group that is in a normal state; wherein the normal main TSV group is the next adjacent main TSV group in the row or column that has not transmitted data and is in a normal state; if the target TSV group is the last main TSV group, the shift register module transmits the data transmitted to the target TSV group to any sub-spare TSV in the spare TSV group that is adjacent and has not transmitted data in the row or column.
[0034] In this embodiment, a plurality of spare TSV groups are arranged at the end of each row or column in each TSV array. Figure 5 Take the TSV repair system in as an example, each row has 8 main TSV groups (i.e., TSV21~TSV28, TSV31~TSV38, TSV41~TSV48), and each row of TSVs in each TSV array is provided with 2 spare TSV groups (i.e., TSV2r1~TSV2r2, TSV3r1~TSV3r2, TSV4r1~TSV4r2), so that each group of main TSVs can be repaired up to twice. The spare TSV group is placed at one end of the main TSV group, so that when the spare TSV group replaces the defective main TSV, the transmitted signal can be shifted in one direction. At the same time, each layer of chips is designed with a shift register module, so that each layer of chips can be repaired independently, which can greatly improve the success rate of repair compared to the traditional solution of repairing the entire TSV chain together. Figure 5 In the TSV repair system shown in , a faulty main TSV group (i.e., TSV23) appears in the second-layer chip, and two faulty main TSV groups (i.e., TSV46 and TSV47) appear in the fourth layer. In the second-layer chip, for the faulty main TSV group (i.e., TSV23), the signal din3 originally entering TSV23 can be shifted into TSV24 through the shift register chain module, and at the same time, the signals din4 to din8 are sequentially shifted into any sub-TSV in a normal state among TSV25 to TSV2r1 for signal transmission. In the fourth-layer chip, for the faulty signal groups TSV46 and TSV47, the signals din6 and din7 originally entering TSV46 and TSV47 are shifted into any sub-TSV in a normal state among TSV48 and TSV4r1 through the shift register chain, and at the same time, the signal din8 is transmitted through any sub-spare TSV in the redundant signal group TSV4r2.
[0035] It should be noted that the various embodiments in the present application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0036] It should also be noted that, in the content of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" can expressly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "include one..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.
[0037] The above description of the disclosed embodiments enables professionals and technicians in the field to implement or use the present application. Various modifications to these embodiments will be apparent to professionals and technicians in the field, and the general principles defined in the present application can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown in the present application, but will conform to the widest range consistent with the principles and novel features disclosed in the present application.
Claims
1. A TSV repair system for 3D stacked chips, characterized in that: include: At least two stacked chips, at least one TSV array, at least one TSV current detection circuit and a controller, the chip includes a shift register module, the two chips are associated through the TSV array, the TSV current detection circuit and the shift register module are respectively connected to the TSV array and the controller, and the TSV module includes a plurality of main TSV groups and a plurality of spare TSV groups; The TSV current detection circuit is used to: detect the current value of each main TSV group in the TSV array, and upload the current value to the controller; The controller is used for: if it is determined according to the current value that the corresponding target TSV group is in an abnormal state, generating a corresponding control signal and transmitting it to the corresponding shift register module; The control signal is used to instruct the shift register module to transfer the data transmitted to the target TSV group to the remaining main TSV groups or the spare TSV groups in the TSV array that are in a normal state.
2. The TSV repair system according to claim 1, characterized in that: It also includes a plurality of TSV path selection circuits, each of the main TSV groups includes at least two parallel sub-TSVs, each of the backup TSV groups includes at least two parallel sub-backup TSVs, and the TSV path selection circuits are respectively connected to the corresponding main TSV groups and the TSV current detection circuits.
3. The TSV repair system according to claim 2, characterized in that: The TSV path selection circuit includes a first switch tube, a second switch tube, a first inverter and a first transmission gate; The first end of the first switch tube is connected to a power source, the second end of the first switch tube is connected to one end of the first inverter, the third end of the first switch tube is connected to one end of the corresponding sub-TSV, the other end of the first inverter is connected to an external excitation signal generator, the first end of the second switch tube is connected to the other end of the sub-TSV, the second end of the second switch tube is connected to the TSV current detection circuit, the third end of the second switch tube is grounded, and the first transmission gate is respectively connected to the first end and the second end of the second switch tube and is used to be connected to the excitation signal generator; The first inverter is used to: invert the first excitation signal transmitted by the excitation signal generator to obtain a second excitation signal, and transmit the second excitation signal to the first switch tube; wherein the second excitation signal is used to control the first switch tube to enter a conducting state, and the first excitation signal is also used to control the second switch tube to enter a conducting state through the first transmission gate.
4. The TSV repair system according to claim 3, characterized in that: The TSV path selection circuit also includes a third switch tube, a fourth switch tube, a second inverter and a second transmission gate; The first end of the third switch tube is connected to a power source, the second end of the third switch tube is connected to one end of the second inverter, the third end of the third switch tube is connected to one end of the sub-TSV, the other end of the second inverter is connected to the excitation signal generator, the first end of the fourth switch tube is connected to the other end of the sub-TSV, the second end of the fourth switch tube is connected to the TSV current detection circuit, the third end of the fourth switch tube is grounded, and the second transmission gate is respectively connected to the first end and the second end of the fourth switch tube and is used to be connected to the excitation signal generator; The second inverter is used to: invert the third excitation signal transmitted by the excitation signal generator to obtain a fourth excitation signal, and transmit the fourth excitation signal to the third switch tube; wherein the fourth excitation signal is used to control the third switch tube to enter a conducting state, and the third excitation signal is also used to control the fourth switch tube to enter a conducting state through the second transmission gate.
5. The TSV repair system according to claim 2, characterized in that: The TSV current detection circuit includes a fifth switch tube, a sixth switch tube and a seventh switch tube; The first end of the fifth switch tube is respectively connected to the power supply and the controller, the second end of the fifth switch tube is respectively connected to the third end of the fifth switch tube and the first end of the sixth switch tube, the second end of the sixth switch tube is respectively connected to the plurality of TSV path selection circuits, the third end of the sixth switch tube is grounded, the seventh switch tube is respectively connected to the second end and the third end of the sixth switch tube and is used to be connected to an external excitation signal generator; wherein, when the seventh switch tube receives the fifth excitation signal transmitted by the excitation signal generator, the TSV current detection circuit enters a working state.
6. The TSV repair system according to claim 1, characterized in that: It includes multiple stacked chips, multiple TSV arrays and multiple TSV current detection circuits. Two adjacent chips are associated through the TSV array. The TSV array is connected to at least one of the TSV current detection circuits. The shift register module in the first chip is connected to the corresponding TSV array and is used to connect to an external data source generator. The shift register module in the last chip is connected to the corresponding TSV array and is used to connect to an external data processing device. The shift register module in the middle chip is respectively connected to one end of the two corresponding TSV arrays.
7. A TSV repair method, characterized in that: A TSV repair system for a 3D stacked chip according to any one of claims 1 to 6, wherein the TSV repair method comprises: The TSV current detection circuit detects the current value of each main TSV group in the TSV array and uploads the current value to the controller; If the controller determines that the corresponding target TSV group is in an abnormal state according to the current value, a corresponding control signal is generated and transmitted to the corresponding shift register module; The control signal is used to instruct the shift register module to transfer the data transmitted to the target TSV group to the remaining main TSV groups or spare TSV groups in the TSV array that are in a normal state.
8. The TSV repair method according to claim 7, characterized in that: The current value includes a first TSV current value and a second TSV current value. The TSV current detection circuit detects the current value of each main TSV group in the TSV array, including: When the first switch tube and the second switch tube corresponding to the main TSV group are both turned on, the TSV current detection circuit detects the first TSV current value; When the first switch tube, the second switch tube, the third switch tube and the fourth switch tube corresponding to the main TSV group are all turned on, the TSV current detection circuit detects the second TSV current value.
9. The TSV repair method according to claim 8, characterized in that: If the controller determines that the corresponding target TSV group is in an abnormal state according to the current value, a corresponding control signal is generated and transmitted to the corresponding shift register module, including: The controller calculates the impedance value of the corresponding target TSV group according to the first TSV current value and the second TSV current value; If the impedance value does not satisfy the corresponding preset reference impedance range, the controller determines that the target TSV group is in an abnormal state, and generates a corresponding control signal to transmit to the corresponding shift register module.
10. The TSV repair method according to claim 7, characterized in that: The spare TSV group is located at the end of the row or column where the target TSV group is located. After the corresponding control signal is generated and transmitted to the corresponding shift register module, the method further includes: If the target TSV group is not the last main TSV group, the shift register module transmits the data transmitted to the target TSV group to any sub-TSV in a normal state in the corresponding normal main TSV group; wherein the normal main TSV group is the next adjacent main TSV group in the row or column that has not transmitted data and is in a normal state; If the target TSV group is the last main TSV group, the shift register module transfers the data transmitted to the target TSV group to any sub-spare TSV in the spare TSV group adjacent to the row or column and not transmitting data.