Chip packaging method and chip packaging structure
By half-cutting and grinding the plastic sealing layer of the chip packaging structure, the thermal stress difference caused by inconsistent thermal expansion coefficient between the packaging layer material and the chip, trace layer and carrier plate is solved, which improves production efficiency and reduces costs.
Patent Information
- Application Number
- CN202411766964.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-03-11
Smart Images
Figure CN119601474A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a chip packaging method and a chip packaging structure. Background Art
[0002] In the semiconductor manufacturing process, packaging is a crucial part of the production process. The packaging layer can not only place, fix, seal and protect the chip to ensure the stability and safety of the chip, but also improve the electrical and thermal performance of the chip and realize the data and signal exchange between the internal circuit of the chip and the external circuit. However, the existing chip packaging process still has the problem of low production efficiency. Summary of the invention
[0003] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a chip packaging method and a chip packaging structure.
[0004] In a first aspect, an embodiment of the present application provides a chip packaging method, the chip packaging method comprising:
[0005] A first carrier is provided, and a stacked wiring layer, a chip layer and a plastic packaging layer are sequentially manufactured on one side of the first carrier to obtain a first plastic packaging structure, wherein the chip layer includes a plurality of chips electrically connected to the wiring layer, wherein the electrode pin side of the chip faces the wiring layer;
[0006] Cutting the plastic encapsulation layer in the first plastic encapsulation structure to form at least one cutting seam on the first plastic encapsulation structure, wherein a cutting depth of the cutting seam in a direction perpendicular to the first carrier board is less than a height of the plastic encapsulation layer;
[0007] The plastic packaging layer of the cut first plastic packaging structure is ground to reduce the thickness of the first plastic packaging structure.
[0008] In a possible implementation, the step of providing a first carrier board, and sequentially manufacturing a stacked wiring layer, a chip layer, and a plastic packaging layer on one side of the first carrier board to obtain a first plastic packaging structure includes:
[0009] Providing a first carrier board, and forming a first adhesive layer on one side of the first carrier board;
[0010] A routing layer is fabricated on a side of the first adhesive layer away from the first carrier board, wherein the routing layer comprises a plurality of routing units and gap channels between the routing units;
[0011] Manufacturing a chip layer on a side of the wiring layer away from the first carrier board;
[0012] A plastic encapsulation layer is made on the peripheral sides of the routing unit and the chip layer and on the side of the chip layer away from the first carrier board to form a first plastic encapsulation structure including a plurality of plastic encapsulation units, wherein the plastic encapsulation unit includes the routing unit, at least one chip electrically connected to the routing unit, and a plastic encapsulation layer covering the routing unit.
[0013] In a possible implementation, the step of cutting the plastic encapsulation layer in the first plastic encapsulation structure to form at least one cutting seam on the first plastic encapsulation structure includes:
[0014] The plastic encapsulation layer in the first plastic encapsulation structure is cut along the extension direction of the gap channel to form a cutting seam between any adjacent plastic encapsulation units, wherein the orthographic projection of the cutting seam on the first carrier is located within the orthographic projection of the gap channel on the first carrier.
[0015] In a possible implementation manner, the step of manufacturing a chip layer on a side of the routing layer away from the first carrier board includes:
[0016] At least one chip is placed on a side of the wiring unit away from the first carrier board, wherein the electrode pins of the chip face the wiring unit and are electrically connected to the wiring unit;
[0017] A bottom filling glue layer is formed between the chip and the wiring layer to fill the two, so as to obtain the chip layer.
[0018] In a possible implementation, the step of manufacturing a plastic encapsulation layer on the peripheral sides of the routing unit and the chip layer and on the side of the chip layer away from the first carrier to form a first plastic encapsulation structure including a plurality of plastic encapsulation units includes:
[0019] The first carrier board with the chip layer manufactured is placed in a plastic packaging mold, and the plastic packaging material is pressed into the mold by injection molding. A plastic packaging layer is manufactured on the adjacent routing units and the peripheral sides of the chip layer and on the side of the chip layer away from the first carrier board to form a first plastic packaging structure including a plurality of plastic packaging units.
[0020] In a possible implementation manner, after the step of grinding the plastic encapsulation layer of the cut first plastic encapsulation structure to reduce the thickness of the first plastic encapsulation structure, the method further includes:
[0021] removing the first carrier board, and transferring the first plastic package structure to a second carrier board, wherein the grinding side of the first plastic package structure is in contact with the second carrier board;
[0022] A conductive interconnect structure is fabricated on a side of the routing layer away from the second carrier, wherein an orthographic projection of the conductive interconnect structure on the second carrier does not overlap with an orthographic projection of the gap channel on the second carrier;
[0023] The second carrier is removed, and the first plastic encapsulation structure is cut based on the gap channel to obtain a chip packaging structure including at least one plastic encapsulation unit.
[0024] In a possible implementation, the step of removing the first carrier and transferring the first plastic package structure to the second carrier includes:
[0025] removing the first adhesive layer to separate the first plastic packaging structure from the first carrier board;
[0026] A second carrier board is provided, a second adhesive layer is manufactured on one side of the second carrier board, and the plastic sealing layer is bonded to the second adhesive layer.
[0027] In a second aspect, an embodiment of the present application further provides a chip packaging structure, which is manufactured according to the chip packaging method described in any one of the first aspects above, and the chip packaging structure includes:
[0028] Routing unit;
[0029] A chip, wherein the chip is located at one side of the wiring layer, wherein the electrode pin side of the chip faces the wiring layer;
[0030] A plastic encapsulation layer is located around the chip and the wiring unit, and on a side of the chip away from the wiring unit, and a side wall of the plastic encapsulation layer has a step structure.
[0031] In a possible implementation, in a direction away from the routing unit, the plastic sealing layer includes a first plastic sealing portion and a second plastic sealing portion which are stacked;
[0032] The first plastic sealing part and the second plastic sealing part form the step structure at the side wall position of the plastic sealing layer;
[0033] The second plastic sealing portion is disposed around the first plastic sealing portion, and in a direction perpendicular to the routing unit and away from the routing unit, a height of the second plastic sealing portion is smaller than a height of the first plastic sealing portion.
[0034] In a possible implementation, the chip packaging structure further includes a conductive interconnect structure, the conductive interconnect structure is located on a side of the routing unit away from the chip, and the conductive interconnect structure is connected to routing in the routing unit.
[0035] Based on any of the above aspects, the chip packaging method and chip packaging structure provided in the embodiments of the present application first perform a half-cutting process on the first plastic packaging structure to form a cutting seam on the first plastic packaging structure, which can release part of the thermal stress caused by the inconsistent thermal expansion coefficients of the plastic packaging layer and the chip, wiring layer and the first carrier board, thereby reducing the impact of thermal stress on the grinding process, reducing the risk of carrier board breakage, and improving the production efficiency of subsequent processes. At the same time, the carrier board can be recycled to reduce production costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0037] Figure 1 A schematic diagram of a process flow of a chip packaging method provided in an embodiment of the present application;
[0038] Figure 2 for Figure 1 The corresponding process diagram;
[0039] Figure 3 for Figure 1 Schematic diagram of the sub-step flow of step S110;
[0040] Figure 4 for Figure 3 The corresponding process diagram;
[0041] Figure 5 Another schematic diagram of a chip packaging method according to an embodiment of the present application;
[0042] Figure 6 for Figure 5 The corresponding process diagram;
[0043] Figure 7 A schematic diagram of a chip packaging structure provided in an embodiment of the present application Figure 1 ;
[0044] Figure 8 A schematic diagram of a chip packaging structure provided in an embodiment of the present application Figure 2 . DETAILED DESCRIPTION
[0045] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0046] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0047] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0048] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0049] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed", "connected", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0050] The inventors discovered that in the relevant chip packaging process, the thermal expansion coefficients (CTE) between the packaging layer material and the chip, wiring layer and carrier are inconsistent, resulting in large thermal stress differences. This thermal stress difference may cause the carrier to crack during the grinding of the plastic packaging layer, thereby affecting subsequent processes and reducing production efficiency.
[0051] In order to solve this problem, the inventor innovatively designed the following technical solution, and the specific implementation scheme of this application will be described in detail below in conjunction with the accompanying drawings. It should be noted that the defects existing in the above-mentioned solutions in the prior art are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above-mentioned technical problems and the solutions proposed in this embodiment below for the above-mentioned problems should all be the contributions made by the inventor to this application in the process of invention and creation, and should not be understood as the technical content known to those skilled in the art.
[0052] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.
[0053] In order to solve the problems in the prior art, the present application provides a chip packaging method. Figure 1 and Figure 2 , Figure 1 Schematic diagram of the chip packaging method. Figure 2 for Figure 1 The corresponding process diagram. Figure 1 and Figure 2 Each step of the chip packaging method is described in detail.
[0054] Step S110: providing a first carrier board, and sequentially manufacturing a stacked wiring layer, a chip layer and a plastic packaging layer on one side of the first carrier board to obtain a first plastic packaging structure.
[0055] In this step, the first carrier 210 may be, but is not limited to, a glass carrier, a resin carrier, etc. The chip layer 120 includes a plurality of chips 121 electrically connected to the wiring layer 110, wherein the electrode pins of the chips 121 face the wiring layer 110. Exemplarily, the chips 121 may include chips such as a system-on-chip (SoC chip) and a high-bandwidth memory chip (HBM).
[0056] Step S120: cutting the plastic packaging layer in the first plastic packaging structure to form at least one cutting seam on the first plastic packaging structure.
[0057] In this step, the orthographic projection of the cutting seam 131 on the first carrier 210 does not overlap with the orthographic projection of the chip 121 on the first carrier 210 , wherein the cutting depth of the cutting seam 131 in the direction perpendicular to the first carrier 210 is less than the height of the plastic encapsulation layer 130 .
[0058] Step S130: grinding the plastic packaging layer of the cut first plastic packaging structure to reduce the thickness of the first plastic packaging structure.
[0059] In this step, the plastic encapsulation layer 130 of the first plastic encapsulation structure 101 can be ground according to the actual needs of the product until the surface of the first plastic encapsulation structure 101 is flat and meets the preset size range. For example, the plastic encapsulation layer 130 of the first plastic encapsulation structure 101 can be ground to expose the side of the chip 121 opposite to the electrode pin to ensure the heat dissipation performance of the chip 121.
[0060] In this embodiment, the first plastic encapsulation structure 101 is first half-cut to form a cutting seam 131 on the first plastic encapsulation structure 101, which can release part of the thermal stress caused by the inconsistent thermal expansion coefficients of the plastic encapsulation layer 130 and the chip 121, the wiring layer 110 and the first carrier 210, thereby reducing the impact of thermal stress on the grinding process, reducing the risk of carrier breakage, and improving the production efficiency of subsequent processes. At the same time, the carrier can be recycled to reduce production costs.
[0061] For further information, please refer to Figure 3 and Figure 4 , step S110 may include the following steps.
[0062] Step S111: providing a first carrier board, and forming a first adhesive layer on one side of the first carrier board.
[0063] In this step, the first adhesive layer can be made of a thermal peeling and / or laser peeling material, wherein the first adhesive layer can be removed by heating and / or laser treatment. Exemplarily, when the first carrier 210 is a glass carrier, the first adhesive layer is made of a laser peeling material.
[0064] Step S112: manufacturing a wiring layer on a side of the first adhesive layer away from the first carrier board.
[0065] In this step, the routing layer 110 includes a plurality of routing units 111 and gap channels between the routing units 111 .
[0066] Step S113: manufacturing a chip layer on a side of the wiring layer away from the first carrier board.
[0067] In this step, at least one chip 121 can be placed on the side of the routing unit 111 away from the first carrier 210, wherein the electrode pins of the chip 121 face the routing unit 111, and the chip 121 is welded to the routing layer 110 to achieve electrical connection between the two. Next, a bottom filling glue layer is formed between the chip 121 and the routing layer 110 to obtain the chip layer 120. Specifically, a suitable bottom filling material can be selected according to the material properties (such as thermal expansion coefficient) of the chip 121 and the routing layer 110, and the bottom filling material can be applied between the chip 121 and the routing layer 110, and finally filled in the gap between the chip 121 and the routing layer 110 by heating, and the bottom filling glue layer is formed after the bottom filling material is cooled and solidified. The bottom filling glue layer can improve the mechanical connection strength between the chip 121 and the routing layer 110 and protect the chip 121 from physical loss.
[0068] Step S114: forming a plastic encapsulation layer on the peripheral sides of the routing unit and the chip layer and on the side of the chip layer away from the first carrier board to form a first plastic encapsulation structure including a plurality of plastic encapsulation units.
[0069] In this step, the first carrier board 210 with the chip layer 120 is placed in a plastic encapsulation mold, and the plastic encapsulation material is pressed into the mold by injection molding. A plastic encapsulation layer 130 is made on the surrounding sides of the adjacent routing units 111 and the chip layer 120 and on the side of the chip layer 120 away from the first carrier board 210 to form a first plastic encapsulation structure 101 including a plurality of plastic encapsulation units, wherein the plastic encapsulation unit includes a routing unit 111, at least one chip 121 electrically connected to the routing unit 111, and a plastic encapsulation layer 130 covering the routing unit 111.
[0070] For further information, please refer to Figure 5 and Figure 6 After step S130, the chip packaging method provided in the embodiment of the present application further includes the following steps.
[0071] Step S140: removing the first carrier board, and transferring the first plastic package structure to a second carrier board.
[0072] In this step, a second adhesive layer may be first made on one side of the second carrier 220 using a thermal stripping and / or laser stripping material, and then the first plastic encapsulation structure 101 may be transferred to the side of the second adhesive layer away from the second carrier 220, wherein the grinding side of the first plastic encapsulation structure 101 is in contact with the second carrier 220. The second carrier 220 may be, but is not limited to, a glass carrier, a resin carrier, etc. Exemplarily, when the first carrier 210 is a glass carrier, the first adhesive layer is made of a laser stripping material.
[0073] Step S150: fabricating a conductive interconnection structure on a side of the wiring layer away from the second carrier board.
[0074] In this step, the routing layer 110 may be cleaned first to remove dirt and / or oxide layer on the surface of the routing layer 110, and then a conductive interconnection structure 140 is made on the side of the routing layer 110 away from the chip layer 120, wherein the orthographic projection of the conductive interconnection structure 140 on the second carrier does not overlap with the orthographic projection of the gap channel on the second carrier, and the conductive interconnection structure 140 includes conductive balls or copper pillar bumps electrically connected to the routing layer 110. Exemplarily, after the routing layer 110 is cleaned, copper metal deposition may be performed on the routing layer 110 to form a plurality of conductive bumps or conductive recesses on the side of the routing layer 110 facing away from the chip layer 120, and finally the prefabricated conductive balls are transferred to the conductive bumps or conductive recesses of the routing layer 110, so that the conductive balls are electrically connected to the routing layer 110, or the conductive bumps may be soldered to form copper pillar bumps electrically connected to the routing layer 110.
[0075] Step S160: removing the second carrier board, and cutting the first plastic packaging structure based on the gap channels to obtain a chip packaging structure including at least one plastic packaging unit.
[0076] In this step, the second adhesive layer can be removed by thermal debonding or laser debonding to separate the second carrier and the first plastic packaging structure 101. Then, the first plastic packaging structure 101 is cut based on the gap channel to obtain a chip packaging structure 10 including at least one plastic packaging unit, wherein the side wall of the chip packaging structure 10 has a step structure.
[0077] Based on the same inventive concept, please refer to Figure 7 The present application also provides a chip packaging structure 10, which includes a routing unit 111, a chip 121 and a plastic packaging layer 130. The chip packaging structure 10 includes at least one chip 121, the chip 121 is located on one side of the routing unit 111, and the electrode pins of the chip 121 face the routing layer 110. The plastic packaging layer 130 is located on the peripheral side of the chip 121 and the routing unit 111, and on the side of the chip 121 away from the routing unit 111, and the sidewall of the plastic packaging layer 130 has a step structure.
[0078] In this embodiment, the step structure of the side wall can be formed by performing secondary processing on the first plastic packaging structure 101. Specifically, the first plastic packaging structure 101 can be firstly subjected to half-cutting processing to form a cutting seam 131 on the first plastic packaging structure 101, and after releasing part of the thermal stress generated by the inconsistency of thermal expansion coefficients between the plastic packaging layer 130 and the chip 121, the wiring unit 111 and the first carrier 210, the first plastic packaging structure 101 is then subjected to grinding and slitting processing to obtain the chip packaging structure 10. In this way, the influence of thermal stress on the grinding process can be effectively reduced, the risk of carrier board breakage can be reduced, the production efficiency of subsequent processes can be improved, and the carrier board can be recycled to reduce production costs.
[0079] Please refer to FIG. 8 . In the direction away from the wiring unit 111, the plastic sealing layer 130 includes a first plastic sealing portion 132 and a second plastic sealing portion 133 which are stacked. The first plastic sealing portion 132 and the second plastic sealing portion 133 form a step structure at the side wall of the plastic sealing layer 130, wherein the second plastic sealing portion 133 surrounds the first plastic sealing portion 132, and in the direction perpendicular to the wiring unit 111 and away from the wiring unit 111, the height of the second plastic sealing portion 133 is less than the height of the first plastic sealing portion 132.
[0080] Further, please refer again to Figure 8 The chip packaging structure 10 also includes a conductive interconnection structure 140, which is located on a side of the routing unit 111 away from the chip 121, and is connected to the routing in the routing unit 111, wherein the conductive interconnection structure 140 includes conductive balls or conductive column bumps.
[0081] To summarize, the embodiments of the present application provide a chip packaging method and a chip packaging structure. In the above-mentioned chip packaging method, the first plastic packaging structure is first half-cut to form a cutting seam on the first plastic packaging structure, which can release part of the thermal stress caused by the inconsistent thermal expansion coefficients of the plastic packaging layer and the chip, the wiring layer and the first carrier board, thereby reducing the impact of thermal stress on the grinding process, reducing the risk of carrier board breakage, and improving the production efficiency of subsequent processes. At the same time, the carrier board can be recycled to reduce production costs.
[0082] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A chip packaging method, characterized in that: The method comprises: A first carrier is provided, and a stacked wiring layer, a chip layer and a plastic packaging layer are sequentially manufactured on one side of the first carrier to obtain a first plastic packaging structure, wherein the chip layer includes a plurality of chips electrically connected to the wiring layer, wherein the electrode pin side of the chip faces the wiring layer; Cutting the plastic encapsulation layer in the first plastic encapsulation structure to form at least one cutting seam on the first plastic encapsulation structure, wherein a cutting depth of the cutting seam in a direction perpendicular to the first carrier board is less than a height of the plastic encapsulation layer; The plastic packaging layer of the cut first plastic packaging structure is ground to reduce the thickness of the first plastic packaging structure.
2. The chip packaging method according to claim 1, characterized in that: The step of providing a first carrier board, and sequentially manufacturing a stacked wiring layer, a chip layer, and a plastic packaging layer on one side of the first carrier board to obtain a first plastic packaging structure includes: Providing a first carrier board, and forming a first adhesive layer on one side of the first carrier board; A routing layer is fabricated on a side of the first adhesive layer away from the first carrier board, wherein the routing layer comprises a plurality of routing units and gap channels between the routing units; Manufacturing a chip layer on a side of the wiring layer away from the first carrier board; A plastic encapsulation layer is made on the peripheral sides of the routing unit and the chip layer and on the side of the chip layer away from the first carrier board to form a first plastic encapsulation structure including a plurality of plastic encapsulation units, wherein the plastic encapsulation unit includes the routing unit, at least one chip electrically connected to the routing unit, and a plastic encapsulation layer covering the routing unit.
3. The chip packaging method according to claim 2, characterized in that: The step of cutting the plastic encapsulation layer in the first plastic encapsulation structure to form at least one cutting seam on the first plastic encapsulation structure includes: The plastic encapsulation layer in the first plastic encapsulation structure is cut along the extension direction of the gap channel to form a cutting seam between any adjacent plastic encapsulation units, wherein the orthographic projection of the cutting seam on the first carrier is located within the orthographic projection of the gap channel on the first carrier.
4. The chip packaging method according to claim 2, characterized in that: The step of manufacturing a chip layer on a side of the wiring layer away from the first carrier board comprises: At least one chip is placed on a side of the wiring unit away from the first carrier board, wherein the electrode pins of the chip face the wiring unit and are electrically connected to the wiring unit; A bottom filling glue layer is formed between the chip and the wiring layer to fill the two, so as to obtain the chip layer.
5. The chip packaging method according to claim 2, characterized in that: The step of manufacturing a plastic encapsulation layer on the peripheral sides of the routing unit and the chip layer and on the side of the chip layer away from the first carrier to form a first plastic encapsulation structure including a plurality of plastic encapsulation units includes: The first carrier board with the chip layer manufactured is placed in a plastic packaging mold, and the plastic packaging material is pressed into the mold by injection molding. A plastic packaging layer is manufactured on the adjacent routing units and the peripheral sides of the chip layer and on the side of the chip layer away from the first carrier board to form a first plastic packaging structure including a plurality of plastic packaging units.
6. The chip packaging method according to claim 2, characterized in that: After the step of grinding the plastic encapsulation layer of the cut first plastic encapsulation structure to reduce the thickness of the first plastic encapsulation structure, the method further includes: removing the first carrier board, and transferring the first plastic package structure to a second carrier board, wherein the grinding side of the first plastic package structure is in contact with the second carrier board; A conductive interconnect structure is fabricated on a side of the routing layer away from the second carrier, wherein an orthographic projection of the conductive interconnect structure on the second carrier does not overlap with an orthographic projection of the gap channel on the second carrier; The second carrier is removed, and the first plastic encapsulation structure is cut based on the gap channel to obtain a chip packaging structure including at least one plastic encapsulation unit.
7. The chip packaging method according to claim 6, characterized in that: The step of removing the first carrier and transferring the first plastic package structure to the second carrier includes: removing the first adhesive layer to separate the first plastic packaging structure from the first carrier board; A second carrier board is provided, a second adhesive layer is manufactured on one side of the second carrier board, and the plastic sealing layer is bonded to the second adhesive layer.
8. A chip packaging structure, characterized in that: The chip packaging method according to any one of claims 1 to 7, wherein the chip packaging structure comprises: Routing unit; A chip, wherein the chip is located at one side of the wiring layer, wherein the electrode pin side of the chip faces the wiring layer; A plastic encapsulation layer is located around the chip and the wiring unit, and on a side of the chip away from the wiring unit, and a side wall of the plastic encapsulation layer has a step structure.
9. The chip packaging structure according to claim 8, characterized in that: In a direction away from the routing unit, the plastic sealing layer includes a first plastic sealing portion and a second plastic sealing portion which are stacked; The first plastic sealing part and the second plastic sealing part form the step structure at the side wall position of the plastic sealing layer; The second plastic sealing portion is disposed around the first plastic sealing portion, and in a direction perpendicular to the routing unit and away from the routing unit, a height of the second plastic sealing portion is smaller than a height of the first plastic sealing portion.
10. The chip packaging structure according to claim 8, characterized in that: The chip packaging structure further includes a conductive interconnection structure, which is located at a side of the routing unit away from the chip, and is connected to the routing in the routing unit.