Conversion control circuit for stackable multi-phase power converter and method thereof

Abstract

The invention relates to a switching control circuit for a stackable multi-phase power converter and a method thereof. The conversion control circuit is used for controlling a plurality of stackable sub-converters which are mutually coupled in parallel so as to generate an output power supply to a load. The conversion control circuit comprises a current sharing end and a current sharing circuit, and the current sharing signal is coupled to a plurality of current sharing ends which are connected in parallel. The current sharing circuit comprises a configuration I, a configuration II and a configuration III, wherein a current sharing signal is generated only according to an inductive current corresponding to one of a plurality of inductors of a plurality of stackable sub-converters; or the second configuration is that the current sharing signal is generated according to a plurality of inductive currents corresponding to a plurality of inductors corresponding to a plurality of starting phases in the plurality of stackable sub-converters, and the proportion of a component generated by the master control circuit in the current sharing signal to a component generated by one of the slave circuits is k, wherein k is related to the difference between the total number of phases and the number of starting phases.

Description

Technical Field

[0001] The present invention relates to a conversion control circuit, and more particularly to a conversion control circuit for a stackable multi-phase power converter. The present invention also relates to a method for controlling the stackable multi-phase power converter. Background Art

[0002] Stackable multiphase power converters can provide high-efficiency DC / DC power conversion to meet the needs of high load current and fast transient response. Therefore, in high performance computing (HPC) applications, stackable multiphase power converters are widely used in CPU, GPU and artificial intelligence. When the load current increases, the number of phases of the stackable multiphase power converter increases; when the load is light, the number of phases will be reduced to save energy.

[0003] Figure 1 A prior art stackable multi-phase power converter is shown. Figure 1 The stackable multi-phase power converter 1001 includes sub-converters 910, 920, 930, 940, which are used to convert the input voltage VIN to generate the output voltage VO to the load 99. Each sub-converter 910, 920, 930, 940 includes a synchronization terminal Y#, an identification terminal ID#, and a current equalization terminal IS#, the synchronization terminal Y# is used to transmit or receive a synchronization signal SYNC, the identification terminal ID# is used to set the phase sequence of the sub-converters 910, 920, 930, 940, and the current equalization terminal IS# is used to transmit or receive a current equalization signal IBUS. The sub-converters 910, 920, 930, 940 generate inductor currents IL1, IL2, IL3, IL4, respectively, thereby generating an output current ISUM.

[0004] Figure 2 A circuit diagram showing a stackable multi-phase power converter of the prior art. Figure 2As shown, the sub-converters 910, 920, 930, 940 include current balancing circuits 911, 921, 931, 941, respectively, and the current balancing circuits 911, 921, 931, 941 include currents IS11, IS21, IS31, IS41 and resistors R1, R2, R3, R4, respectively, wherein the currents IS11, IS21, IS31, IS41 are related to the inductor currents IL1-IL4 corresponding to the sub-converters 910, 920, 930, 940, respectively. The currents IS11, IS21, IS31, IS41 are coupled to the resistors R1, R2, R3, R4, respectively, at the corresponding synchronization terminals, and all the synchronization terminals are coupled in parallel to each other, thereby generating the current balancing signal IBUS. The transconductance amplifier 9N (N is the phase sequence, such as 91, 92, 93, 94) corresponding to each of the sub-converters 910, 920, 930, 940 is used to compare the current sharing signal IBUS with the sensing signal VISN (N is the phase sequence, such as VIS1, VIS2, VIS3, VIS4) of the corresponding sub-converter to generate an adjustment signal Vadj, thereby adjusting the duty cycle and other parameters of the corresponding phase sub-converter, thereby achieving current sharing between each phase sub-converter. The above-mentioned sensing signal VISN is generated according to the corresponding sensing current ISN (N is the phase sequence, such as IS1, IS2, IS3, IS4) and the resistor R.

[0005] The disadvantage of the above prior art is that when the output current ISUM decreases to a certain level (for example, the load 99 becomes a light load), the number of startup phases decreases, which will cause an imbalance in the current balancing signal IBUS, thereby causing the stackable multi-phase power converter to be unable to achieve current balancing. Figure 2 As shown, the stackable multi-phase power converter includes a 4-phase sub-converter. When the output current ISUM decreases, so that the number of startup phases changes from 4 phases to 3 phases (for example, the current IS41 changes to 0), the voltage of the current sharing signal IBUS is as shown in the following formula 1:

[0006] IBUS=(IS11+IS21+IS31) / (R1+R2+R3+R4) (Formula 1)

[0007] It can be seen from the above formula 1 that when the number of activated phases decreases, the current sharing signal IBUS will be unbalanced at least in the instantaneous stage, thereby causing the stackable multi-phase power converter to be unable to achieve current sharing, or causing unnecessary current or voltage overshoot or undershoot.

[0008] Compared to the above-mentioned prior art, the present invention provides a control circuit for controlling a stackable multi-phase power converter, which can continue to achieve the current balancing effect when the number of startup phases of the stackable multi-phase power converter changes, and is not affected by the change in the number of startup phases, thereby achieving the advantages of more power saving, high efficiency, and stable output current and voltage. Summary of the invention

[0009] In one aspect, the present invention provides a conversion control circuit for controlling a stackable sub-converter, wherein a plurality of stackable sub-converters are configured as a stackable multi-phase power converter, wherein each of the plurality of stackable sub-converters includes a power stage circuit and a corresponding conversion control circuit, wherein the plurality of power stage circuits corresponding to the plurality of stackable sub-converters are coupled in parallel to each other to generate an output power to a load, the output power including an output current, wherein the conversion control circuit is used to control at least one switch of the power stage circuit to switch a corresponding inductor, thereby generating the output power, wherein the conversion control circuit is configured as a master circuit or a slave circuit, wherein the plurality of stackable sub-converters have a total number of phases and a number of start-up phases, wherein the number of start-up phases is determined according to the level of the output current, and the conversion control circuit comprises: a current balancing terminal, wherein a current balancing signal is coupled to the plurality of the conversion control circuits connected in parallel to each other; The invention relates to a current balancing terminal; a current balancing circuit for generating and / or receiving the current balancing signal, and for generating an adjustment signal according to a difference between the current balancing signal and a corresponding sub-current sensing signal, so as to adjust at least one parameter of the conversion control circuit, so as to balance the current among the plurality of stackable sub-converters, wherein the sub-current sensing signal is related to an inductor current corresponding to the corresponding inductor; wherein the current balancing circuit includes the following configurations: configuration one: wherein the current balancing signal is generated only according to the inductor current corresponding to one of the plurality of inductors of the plurality of stackable sub-converters; or configuration two: wherein the current balancing signal is generated according to the plurality of inductor currents corresponding to the plurality of inductors corresponding to the plurality of startup phases in the plurality of stackable sub-converters, wherein the ratio of the component generated by the master control circuit to the component generated by one of the slave circuits in the current balancing signal is k, wherein k is related to the difference between the total number of phases and the number of startup phases.

[0010] In one embodiment, in configuration 1, the current sharing signal is generated only according to the inductor current corresponding to the main control circuit.

[0011] In one embodiment, the current balancing circuit corresponding to the master control circuit does not generate the adjustment signal and does not adjust the at least one parameter of the conversion control circuit, wherein each corresponding current balancing circuit of the slave circuit generates the adjustment signal to adjust the corresponding at least one parameter to perform current balancing among the multiple stackable sub-converters.

[0012] In one embodiment, in configuration 2, each corresponding current balancing circuit of the master circuit and the slave circuit generates a corresponding adjustment signal to adjust the corresponding at least one parameter to balance current among the plurality of stackable sub-converters.

[0013] In one embodiment, the conversion control circuit controls the at least one switch of one of the corresponding stackable sub-converters at a fixed time, wherein the fixed time is determined according to a threshold voltage, an integral capacitance value, or an integral current; wherein the adjustment signal is used to adjust the at least one parameter to adjust the fixed time, thereby performing current sharing among the stackable sub-converters, wherein the at least one parameter includes at least one of the threshold voltage, the integral capacitance value, and the integral current.

[0014] In one embodiment, the conversion control circuit further includes a transduction circuit and a filtering circuit, wherein the transduction circuit is used to generate a transduction current according to the difference between the corresponding sub-current sensing signal and the current equalizing signal, and the filtering circuit is used to generate an amplified output signal according to the transduction current, wherein the adjustment signal corresponds to the amplified output signal, and the amplified output signal corresponds to the threshold voltage.

[0015] In one embodiment, the conversion control circuit further includes: a synchronization end, wherein a synchronization signal is coupled to multiple synchronization ends of multiple conversion control circuits connected in parallel; wherein the synchronization signal includes multiple pulses, and the multiple pulses are continuously counted as a count value, wherein the synchronization signal includes a reset signal for resetting and starting the count value; wherein when the count value is related to a phase sequence number corresponding to the conversion control circuit, the conversion control circuit enables the corresponding power stage circuit to generate the output power supply; wherein the master control circuit is used to generate the synchronization signal via the synchronization end, and the slave circuit is used to receive the synchronization signal via the synchronization end.

[0016] In one embodiment, when the count value reaches the start phase number, the reset signal is generated, wherein a pulse of the synchronization signal with a higher voltage level is used to indicate the reset signal.

[0017] In one embodiment, the stackable sub-converter is activated by being triggered by a corresponding pulse of the synchronization signal.

[0018] In one embodiment, the conversion control circuit is configured as an integrated circuit, the synchronization end corresponds to a synchronization pin of the integrated circuit, and the current balancing end corresponds to a current balancing pin of the integrated circuit.

[0019] In another aspect, the present invention also provides a control method for controlling a stackable sub-converter, wherein a plurality of stackable sub-converters are configured as a stackable multi-phase power converter, wherein each of the plurality of stackable sub-converters includes a power stage circuit, wherein the plurality of power stage circuits corresponding to the plurality of stackable sub-converters are coupled in parallel to each other to generate an output power to a load, wherein the power stage circuit includes at least one switch to switch an inductor to generate the output power, wherein one of the plurality of stackable sub-converters is configured as a master stackable sub-converter, and the other of the plurality of stackable sub-converters is configured as a slave stackable sub-converter, wherein the plurality of stackable sub-converters have a total number of phases and a start-up number of phases, and the control method comprises: controlling at least one of the power stage circuits to start the inductor; A switch switches the corresponding inductor; each of the multiple stackable sub-converters is used to generate or receive a current sharing signal; and current sharing is performed between the multiple stackable sub-converters according to the current sharing signal; wherein the step of generating the current sharing signal includes one of the following methods: Method 1: generating the current sharing signal only according to an inductor current corresponding to one of the multiple inductors of the multiple stackable sub-converters; or Method 2: generating the current sharing signal according to multiple inductor currents corresponding to multiple inductors corresponding to multiple startup phases in the multiple stackable sub-converters, wherein the ratio of the component generated by the master stackable sub-converter to the component generated by one of the slave stackable sub-converters in the current sharing signal is k, wherein k is related to the difference between the total number of phases and the number of startup phases.

[0020] The following will be described in detail through specific embodiments to make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A block diagram of a prior art stackable multi-phase power converter is shown.

[0022] Figure 2 A circuit diagram showing a stackable multi-phase power converter of the prior art.

[0023] Figure 3 A circuit diagram showing an embodiment of a conversion control circuit in a stackable multi-phase power converter of the present invention.

[0024] Figure 4A schematic diagram showing a specific embodiment of a current balancing circuit in a stackable multi-phase power converter of the present invention.

[0025] Figure 5 A schematic diagram showing another specific embodiment of the current balancing circuit in the stackable multi-phase power converter of the present invention.

[0026] Figure 6 A schematic diagram showing a specific embodiment of a fixed time generating circuit in a stackable multi-phase power converter of the present invention.

[0027] Figure 7 A schematic diagram showing a specific embodiment of a conversion control circuit in a stackable multi-phase power converter of the present invention.

[0028] Figure 8 An operation waveform diagram of an embodiment of the stackable multi-phase power converter of the present invention is shown.

[0029] Explanation of symbols in the figure

[0030] 10: Power stage circuit

[0031] 1001: Stackable Multiphase Power Converters

[0032] 110, 111, 112, 117: conversion control circuit

[0033] 1100, 1101, 1102: Stackable sub-converters

[0034] 16: Drive

[0035] 17: Resistance

[0036] 18, 181, 182, 187: Current sharing circuit

[0037] 19, 197: Modulation circuit

[0038] 1916: Fixed time generation circuit

[0039] 197: Modulation Circuit

[0040] 20: Power stage circuit

[0041] 2003: Stackable Multiphase Power Converters

[0042] 2004: Stackable Multiphase Power Converters

[0043] 2005: Stackable Multiphase Power Converters

[0044] 210, 211, 212: conversion control circuit

[0045] 2100, 2101, 2102: Stackable sub-converters

[0046] 26: Drive

[0047] 27: Resistance

[0048] 28, 281, 282: Current sharing circuit

[0049] 29: Modulation Circuit

[0050] 30: Power stage circuit

[0051] 310: Conversion control circuit

[0052] 3100: Stackable Sub-Converter

[0053] 36: Drive

[0054] 37: Resistance

[0055] 38: Current balancing circuit

[0056] 39: Modulation circuit

[0057] 40: Power stage circuit

[0058] 410: Conversion control circuit

[0059] 4100: Stackable Sub-Converter

[0060] 60: Comparator

[0061] 70: Filter circuit

[0062] 81, 82, 8N: Transduction circuit

[0063] 910, 920, 930, 940: Subconverter

[0064] 911, 921, 931, 941: Current sharing circuit

[0065] 99: Load

[0066] 9N: Transduction Amplifier

[0067] Cpo: Comparison signal

[0068] CTon: Integrating capacitor

[0069] IS1, IS2, ISN: sensing current

[0070] IS1', IS2', IS3', ISN', IS1a, IS1a': sensing current

[0071] IS11, IS21, IS31, IS41: Current

[0072] IBUS: current sharing signal

[0073] ID#: Identification terminal

[0074] ID_Z: Phase sequence number

[0075] Igm1a: transduction current

[0076] IL1, IL2, IL3, IL4: Inductor current

[0077] Io1, Io2, Io3, IoN: inductor current

[0078] IS#: Current sharing terminal

[0079] ISUM: output current

[0080] ITon: current source

[0081] ISN: Sense Current

[0082] k : integer

[0083] L1, L2, L3, LN: Inductor

[0084] N: integer

[0085] N0: Power stage circuit

[0086] N10, N11, N12: conversion control circuit

[0087] N100, N101, N102: Stackable sub-converters

[0088] N6: Driver

[0089] N7: Resistor

[0090] N8, N81, N82: Current balancing circuit

[0091] N9: Modulation circuit

[0092] Nph_activated: number of activated phases

[0093] Nph_total: total number of phases

[0094] NZ: count value

[0095] R: Resistance

[0096] R1, R2, R3, R4: resistors

[0097] R27, R37, RN7: resistance value

[0098] RX: reset signal

[0099] S6: Switch

[0100] SP1a: Modulation signal

[0101] SPWM, SP1, SP2, SP3, SPN: modulation signal

[0102] Sw0, Sw1, Sw2, Sw3, SwZ: switch nodes SYNC: synchronization signal

[0103] t0~t4,t0':time point

[0104] Ton: On time

[0105] Tsw: cycle

[0106] Va1a: Adjusting the signal

[0107] Vadj, Va1, Va2, Va3, VaN: Adjustment signal

[0108] VAO: Amplifies the output signal

[0109] Vc: integral voltage

[0110] VH: High level

[0111] VIBUS: Current sharing signal

[0112] VIN: Input voltage

[0113] VISN: Sensing Signals

[0114] VISN, VIS2, VIS1a: Sub-current sensing signals

[0115] VL: Low level

[0116] VO: Output voltage

[0117] Vst1, Vst2, Vst3, VstN: voltage

[0118] VTH: Threshold

[0119] Vth_Ton: threshold voltage

[0120] Y#: Synchronous end

[0121] Z: integer DETAILED DESCRIPTION

[0122] The drawings in the present invention are schematic, and are mainly intended to show the coupling relationship between the various circuits and the relationship between the various signal waveforms. The circuits, signal waveforms and frequencies are not drawn according to scale. For the purpose of clarity, many practical details will be described in the following description, but this is not intended to limit the scope of the patent application of the present invention.

[0123] Figure 3 A schematic diagram of an embodiment of a stackable multi-phase power converter of the present invention is shown. In one embodiment, a stackable multi-phase power converter 2003 includes stackable sub-converters 1100-N100 (e.g., 1100, 2100, 3100, ... N100) of N phases, where N is an integer greater than 1, and the same applies below. In one embodiment, the stackable sub-converters 1100, 2100, 3100-N100 respectively include power stage circuits 10, 20, 30-N0, and the power stage circuits 10, 20, 30-N0 are used to be coupled in parallel with each other to generate an output power (e.g., corresponding to an output voltage VO) to a load 99, and the output power includes an output current ISUM. In one embodiment, the power stage circuits 10, 20, 30-N0 operate in staggered phases. Specifically, the power stage circuits 10, 20, 30-N0 are used to switch the inductors L1, L2, L3 and LN to generate corresponding inductor currents Io1, Io2, Io3-IoN, thereby achieving interleaved switching power conversion. The above N is an integer greater than 1, and the same applies below.

[0124] In one embodiment, the power stage circuit is a buck converter, however, this is not intended to limit the scope of the invention. The power stage circuit may also be configured as other switching power converters, such as a boost converter, a buck-boost converter, a flyback converter, etc.

[0125] In one embodiment, the stackable sub-converters 1100, 2100, 3100-N100 further include corresponding conversion control circuits 110, 210, 310-N10 for controlling at least one switch of the respective corresponding power stage circuits to switch the corresponding inductors, thereby generating output power. In one embodiment, the stackable multi-phase power converter 2003 further includes a corresponding number of drivers (16, 26, 36-N6), wherein each driver is respectively coupled between the corresponding conversion control circuit and the power stage circuit to drive the switching thereof.

[0126] In one embodiment, each conversion control circuit 110, 210, 310-N10 can be programmed to be configured as a master circuit or a slave circuit, and the staggered phase sequence number can also be programmed. Figure 3, in one embodiment, each of the conversion control circuits 110, 210, 310 to N10 includes an identification terminal ID# for setting the phase sequence number ID_Z. In one embodiment, a resistor and a constant current source in the conversion control circuit are used to determine the phase sequence number ID_Z of the conversion control circuit. The constant current sources in each of the conversion control circuits 110, 210, 310 to N10 are respectively coupled to the setting resistors 17, 27, 37 to N7 via their respective corresponding identification terminals ID#, thereby generating voltages Vst1, Vst2, Vst3 to VstN. The voltage levels of the voltages Vst1, Vst2, Vst3 to VstN are used to determine the phase sequence number ID_Z of the corresponding conversion control circuit.

[0127] In one embodiment, the identification terminal ID# of the conversion control circuit 110 is coupled to the ground potential to set its phase sequence number ID_Z to 0 (i.e., the resistor 17 can be omitted and short-circuited). In one embodiment, the phase sequence number ID_Z is also used to determine whether the conversion control circuit is configured as a master circuit or a slave circuit. In one embodiment, the identification terminal ID# of the conversion control circuit 110 is coupled to the ground potential to set its phase sequence number ID_Z to 0, thereby setting the conversion control circuit 110 as the master circuit. In one embodiment, the relationship between the resistance values R27, R37, RN7 of the resistors 27, 37, N7 is: R27 < R37 < RN7, thereby setting the phase sequence numbers ID_Z of the conversion control circuits 210, 310, N10 to 1, 2, 3. In one embodiment, phase sequence numbers ID_Z other than 0 (master circuit) will determine that the conversion control circuit (such as 210, 310, N10) is a slave circuit.

[0128] Please continue to refer to Figure 3 , in one embodiment, each of the conversion control circuits 110, 210, 310 to N10 includes a synchronization terminal Y# for transmitting or receiving a synchronization signal SYNC. In one embodiment, all the synchronization terminals Y# (i.e., the synchronization terminals Y# of the conversion control circuits 110, 210, 310 to N10) are coupled to each other. Or from another perspective, all the synchronization terminals Y# are coupled in parallel to each other. That is, the synchronization signal SYNC is coupled to the multiple synchronization terminals Y# of the multiple conversion control circuits (110, 210, 310 to N10) that are coupled in parallel to each other. In one embodiment, the master circuit (i.e., the conversion control circuit 110) generates and transmits the synchronization signal SYNC via the corresponding synchronization terminal Y#. On the other hand, the slave circuits (i.e., the conversion control circuits 210, 310 to N10) are used to receive the synchronization signal SYNC via their respective corresponding synchronization terminals Y#.

[0129] In one embodiment, the identification terminal ID# of the conversion control circuit in the stackable multi-phase power converter 2003 can be omitted. In one embodiment, the phase sequence number ID_Z can be set by other means, such as: a pre-programmed single or multiple write programmable storage circuit, or a digital communication interface (such as an integrated circuit bus circuit IS2C).

[0130] Please continue reading Figure 3 In one embodiment, a plurality of stackable sub-converters have a total number of phases and a number of start-up phases, wherein the number of start-up phases is determined according to the level of the output current. For example, in one embodiment, N is equal to 4, and the stackable sub-converters 1100, 2100, 3100-N100 have a total number of phases of 4 and a number of start-up phases (less than or equal to 4), and the number of start-up phases is determined according to the level of the output current ISUM. When the output current ISUM increases, the number of start-up phases also increases; when the output current ISUM decreases, the number of start-up phases also decreases.

[0131] In one embodiment, each conversion control circuit 110, 210, 310-N10 further includes a current balancing terminal IS#, and the conversion control circuits 110, 210, 310-N10 respectively include current balancing circuits 18, 28, 38-N8, and modulation circuits 19, 29, 39-N9. In one embodiment, the current balancing circuits 18, 28, 38-N8 are used to generate and / or receive a current balancing signal VIBUS, wherein the current balancing signal VIBUS is coupled to the current balancing terminal IS# corresponding to each of the conversion control circuits 110, 210, 310-N10 connected in parallel.

[0132] In one embodiment, the current balancing circuit is further used to generate an adjustment signal Vadj according to the difference between the current balancing signal VIBUS and the corresponding sub-current sensing signal VISN, and the modulation circuit is used to generate a modulation signal SPWM according to the adjustment signal Vadj. Specifically, the current balancing circuits 18, 28, 38-N8 are used to generate corresponding adjustment signals Va1, Va2, Va3-VaN according to the difference between the current balancing signal VIBUS and the corresponding sub-current sensing signal VISN, so as to adjust at least one parameter of the corresponding conversion control circuits 110, 210, 310-N10, and generate corresponding modulation signals SP1, SP2, SP3-SPN through the modulation circuits 19, 29, 39-N9, so as to perform current balancing among the stackable sub-converters 1100, 2100, 3100-N100.

[0133] In one embodiment, the conversion control circuit (e.g., N10) may be configured as an integrated circuit, the synchronization terminal Y# corresponds to the synchronization pin of the integrated circuit, and the current sharing terminal IS# corresponds to the current sharing pin of the integrated circuit. In one embodiment, the conversion control circuit and the driver (e.g., N6) may be integrated into an integrated circuit, or the conversion control circuit, the driver, and the power stage circuit (e.g., N0) may be integrated into an integrated circuit.

[0134] It should be noted that Figure 3 In the embodiment of the present invention, the current balancing circuits 18, 28, 38 to N8 can be configured as follows: Figure 4 or Figure 5 The specific embodiments shown are described below, and the operations of the two specific embodiments will be described respectively.

[0135] See also Figure 4 , Figure 4 A schematic diagram showing a specific embodiment of a current balancing circuit in a stackable multi-phase power converter of the present invention. Figure 4 In the stackable multi-phase power converter 2004, the current balancing signal VIBUS is generated only according to the inductor current (e.g., Io1, Io2-IoN) corresponding to one of the multiple inductors (e.g., L1, L2-LN) of the multiple stackable sub-converters (1101, 2101-N101). For example, in this embodiment, the current balancing signal VIBUS is generated only according to the inductor current Io1 corresponding to the inductor L1 of the stackable sub-converter 1101.

[0136] In a preferred embodiment, the conversion control circuit 111 is configured as a master control circuit. In other words, in this embodiment, the current balancing signal VIBUS is generated only according to the inductor current (Io1) corresponding to the master control circuit (111). In a preferred embodiment, the current balancing circuit 181 corresponding to the master control circuit (e.g., the conversion control circuit 111) does not generate an adjustment signal and does not adjust at least one parameter of the conversion control circuit 111. Each corresponding current balancing circuit (281-N81) of the slave circuit (e.g., the conversion control circuit 211-N11) generates an adjustment signal (Va2-VaN) to adjust the corresponding at least one parameter to perform current balancing between a plurality of stackable sub-converters (1101, 2101-N101).

[0137] Please continue reading Figure 4In one embodiment, the current balancing circuits 181, 281-N81 include transduction circuits 81, 82-8N, respectively. In one embodiment, in the current balancing circuit 181 of the master circuit (conversion control circuit 111), the current balancing signal VIBUS is generated according to the sensed current IS1 related to the inductor current Io1 and the resistor R; in the current balancing circuit (281-N81) of the slave circuit (conversion control circuit 211-N11), the transduction circuit (82-8N) generates the corresponding adjustment signal (Va2-VaN) according to the difference between the current balancing signal VIBUS and the corresponding sub-current sensing signal (VIS2-VISN). In one embodiment, the sub-current sensing signals (VIS2-VISN) of the slave circuit (conversion control circuit 211-N11) are generated according to the corresponding sensing current (IS2-ISN) and the resistor R, wherein the sensing current IS2-ISN is related to the corresponding inductor current Io2-IoN.

[0138] It should be noted that Figure 4 It can be seen from the embodiments of the present invention that the stackable multi-phase power converter of the present invention can generate a current balancing signal by only one of the stackable sub-converters (master control circuit), and the other stackable sub-converters (slave circuits) generate adjustment signals according to their sub-current sensing signals and the current balancing signal to adjust at least one parameter of the corresponding conversion control circuit, thereby achieving current balancing. Since the current balancing signal is only generated by one of the stackable sub-converters (master control circuit), when the number of startup phases of the stackable multi-phase power converter is reduced, the current balancing signal is not affected, and the current balancing state is still continuously achieved.

[0139] See also Figure 5 , Figure 5 Another specific embodiment of the current balancing circuit in the stackable multi-phase power converter of the present invention is shown in the schematic diagram. Figure 5 In the stackable multi-phase power converter 2005, the current balancing signal VIBUS is generated according to the multiple inductor currents (e.g., Io1, Io2-IoN) corresponding to the multiple inductors (e.g., L1, L2-LN) corresponding to the multiple activation phases in the multiple stackable sub-converters (1102, 2102-N102). In one embodiment, the ratio of the component generated by the master control circuit to the component generated by one of the slave circuits in the current balancing signal VIBUS is k. In one embodiment, k is an integer greater than or equal to 1 and is related to the difference between the total number of phases Nph_total and the number of activation phases Nph_activated. Specifically, k can be represented by the following formula 2:

[0140] k=Nph_total-Nph_activated+1 (Formula 2)

[0141] In Formula 2, when the output current ISUM level is higher, the activated phase number Nph_activated is higher, the activated phase number Nph_activated is less than or equal to the total phase number Nph_total, and the activated phase number Nph_activated is greater than or equal to 2 (when it is equal to 1, there is no need for current balancing).

[0142] Specifically, if Figure 5 As shown, in a preferred embodiment, the conversion control circuit 112 is configured as a master circuit, and the other conversion control circuits (such as 212-N12) are configured as slave circuits, and the current balancing circuits 182, 282-N82 respectively include transduction circuits 81, 82-8N. In this embodiment, the current balancing circuits 182, 282-N82 respectively generate and receive the current balancing signal VIBUS according to the corresponding k-times sensing current k*IS1', sensing current IS2'-ISN' and resistor R, wherein the sensing current IS1', IS2'-ISN' are related to the corresponding inductor currents Io1, Io2-IoN. In one embodiment, the transconductance circuits 81, 82-8N generate corresponding adjustment signals Va1, Va2-VaN according to the difference between the current balancing signal VIBUS and the corresponding sub-current sensing signals VIS1, VIS2-VISN, so as to adjust at least one parameter of the corresponding conversion control circuits 112, 212-N12, thereby performing current balancing between the stackable sub-converters 1102, 2102-N102. In this embodiment, the sub-current sensing signals VIS1, VIS2-VISN are generated according to the corresponding sensing currents (IS1, IS2-ISN) and the resistors R, wherein the sensing currents IS1, IS2-ISN are related to the corresponding inductor currents Io1, Io2-IoN.

[0143] It should be noted that in the above embodiment, the component of the current averaging signal VIBUS generated by the master circuit (conversion control circuit 112) is related to k times the sensing current k*IS1', and the component of the current averaging signal VIBUS generated by the slave circuit (conversion control circuit 212~N12) is related to the sensing current IS2'~ISN'.

[0144] In a specific embodiment, N is equal to 3, and the stackable multi-phase power converter 2005 has a total phase number of 3. When the load 99 is heavy (the output current ISUM is large), the startup phase number is equal to 3, and k is equal to 1. Assuming that the resistance values ​​of the resistors R in the current balancing circuits 182, 282-N82 are substantially the same, the level of the current balancing signal VIBUS can be expressed by the following formula 3:

[0145] VIBUS=(1*IS1'+IS2'+IS3') / 3R (Formula 3)

[0146] In the above embodiment, when the load 99 changes to a medium load (the output current ISUM becomes smaller), the number of start-up phases is equal to 2, and k is equal to 2. At this time, the level of the current sharing signal VIBUS can be expressed by the following formula 4:

[0147] VIBUS=(2*IS1'+IS2') / 3R (Formula 4)

[0148] It can be seen from equations 3 and 4 that according to the stackable multi-phase power converter of the present invention, since the current balancing signal VIBUS is related to the k-times sensing current k*IS1' of the main control circuit, when the number of startup phases of the stackable multi-phase power converter changes, the current balancing balance state may not be affected. For example, when the number of startup phases changes from 3 to 2, k changes from 1 to 2. At this time, although the component of the current balancing signal VIBUS is less than the sensing current IS3', the sensing current generated by the main control circuit becomes twice (2*IS1'), so the level of the current balancing signal VIBUS is substantially unaffected, and the current balancing balance state can be continuously achieved, so that even in an instant, the stability of the current and voltage of each phase can be maintained.

[0149] See also Figure 6 , Figure 6 A schematic diagram showing a specific embodiment of a fixed time generating circuit in a stackable multi-phase power converter of the present invention. In one embodiment, the modulation circuit N9 includes Figure 6 The fixed time generating circuit 1916 shown in the figure includes a current source ITon, an integrating capacitor CTon and a comparator 60. In one embodiment, the comparison signal Cpo is used to control the conduction state of the switch S6. When the switch S6 is turned on, the integrated voltage Vc on the integrating capacitor CTon is reset to 0V, for example. When the switch S6 is turned off, the fixed time generating circuit 1916 starts to integrate the current source ITon through the integrating capacitor CTon to generate the integrated voltage Vc. The comparator 60 is used to compare the integrated voltage Vc with the threshold voltage Vth_Ton to generate the comparison signal Cpo.

[0150] In one embodiment, the modulation signal SPN controls at least one switch of the power stage circuit of the corresponding stackable sub-converter for a fixed time according to the comparison signal Cpo, for example, controls the fixed on time of the corresponding power stage circuit. In one embodiment, the fixed time is determined according to the threshold voltage Vth_Ton, the capacitance of the integral capacitor CTon, or the integral current of the current source ITon. In one embodiment, the adjustment signal VaN (corresponding to the aforementioned Vadj) is used to adjust at least one parameter to adjust the fixed time, thereby performing current sharing among multiple stackable sub-converters (for example, stackable sub-converters 1102, 2102~N102). In this embodiment, as Figure 6 As shown, the at least one parameter includes at least one of a threshold voltage Vth_Ton, a capacitance value of an integral capacitor CTon, and an integral current of a current source ITon.

[0151] See also Figure 7 , Figure 7 A schematic diagram of a specific embodiment of the conversion control circuit in the stackable multi-phase power converter of the present invention is shown. In one embodiment, the conversion control circuit 117 includes a current equalizing circuit 187, a modulation circuit 197 and a filter circuit 70. In one embodiment, the transduction circuit 81 in the current equalizing circuit 187 is used to generate a transduction current Igm1a according to the difference between the corresponding sub-current sensing signal VIS1a and the current equalizing signal VIBUS, wherein the sub-current sensing signal VIS1a and the current equalizing signal VIBUS are generated according to the sensing current IS1a and IS1a', respectively, wherein the sensing current IS1a and IS1a' are related to the corresponding inductor current. In one embodiment, the filter circuit 70 is used to generate an amplified output signal VAO according to the transduction current Igm1a. In this embodiment, the adjustment signal Va1a corresponds to the amplified output signal VAO, and the amplified output signal VAO corresponds to the threshold voltage Vth_Ton.

[0152] exist Figure 7 In the embodiment, the modulation circuit 197 adjusts the threshold voltage Vth_Ton by adjusting the signal Va1a to generate the modulation signal SP1a. The modulation signal SP1a is used to control at least one switch of the power stage circuit of the corresponding stackable sub-converter, thereby performing current sharing among multiple stackable sub-converters.

[0153] Please also see Figure 3 and Figure 8 , Figure 8 Display corresponds to Figure 3 Operation waveform diagram of an embodiment of a stackable 4-phase power converter. In a specific embodiment, Figure 3 The stackable multi-phase power converter 2003 has a total of 4 phases, that is, the stackable multi-phase power converter 2003 includes stackable sub-converters 1100, 2100, 3100, and 4100. In one embodiment, the stackable sub-converters 1100, 2100, 3100, and 4100 have corresponding switching nodes Sw0, Sw1, Sw2-SwZ (Sw0, Sw1, Sw2, and Sw3 in this embodiment), and the switching nodes Sw0, Sw1, Sw2-SwZ are nodes where the inductors L1, L2, L3-LN are coupled to the corresponding power stage circuits. The above Z is an integer greater than or equal to 1.

[0154] In one embodiment, if Figure 8As shown, the synchronization signal SYNC includes a plurality of pulses, and the plurality of pulses are continuously counted as a count value NZ, wherein the synchronization signal SYNC includes a reset signal RX for resetting and starting the count value NZ. In one embodiment, when the count value NZ is related to the phase sequence number ID_Z corresponding to the conversion control circuit, the conversion control circuit enables the corresponding power stage circuit to generate an output power supply. In one embodiment, the stackable sub-converter is started by triggering the corresponding pulse of the synchronization signal. The operation of the stackable multi-phase power converter 2003 including 4 phases will be described below.

[0155] Specifically, if Figure 3 and Figure 8 As shown, in this embodiment, the phase sequence numbers ID_Z of the conversion control circuits 110, 210, 310, and 410 are set to 0, 1, 2, and 3, respectively. In one embodiment, in a cycle Tsw, a synchronization signal SYNC and a reset signal RX are generated at time point t0 (for example, by the conversion control circuit 110), and the count value NZ of each conversion control circuit 110, 210, 310, and 410 is set to 0. At time point t1, since the count value NZ is 0 and equal to the phase sequence number ID_Z of the conversion control circuit 110, the falling edge of the synchronization signal SYNC triggers the conversion control circuit 110 to enable the power stage circuit 10, thereby generating an output power supply to the load 99, for example, by controlling the upper bridge switch of the power stage circuit 10 to turn on, so that the switching node Sw0 is electrically connected to the input voltage VIN for a conduction time Ton. At the same time, the falling edge of the synchronization signal SYNC adds the count value NZ to 1. It should be noted that the conduction time Ton is determined by the fixed time generation circuit.

[0156] At time t2, since the count value NZ is 1, the falling edge of the synchronization signal SYNC triggers the conversion control circuit 210 (phase sequence number ID_Z is 1) to enable the power stage circuit 20, thereby generating output power to the load 99, for example, by controlling the upper bridge switch of the power stage circuit 20 to be turned on, so that the switching node Sw1 is electrically connected to the input voltage VIN for a conduction time Ton. At the same time, the falling edge of the synchronization signal SYNC increases the count value NZ to 2.

[0157] At time t3, since the count value NZ is 2, the falling edge of the synchronization signal SYNC triggers the conversion control circuit 310 (phase sequence number ID_Z is 2) to enable the power stage circuit 30, thereby generating output power to the load 99, for example, by controlling the upper bridge switch of the power stage circuit 30 to be turned on, so that the switching node Sw2 is electrically connected to the input voltage VIN for a conduction time Ton. At the same time, the falling edge of the synchronization signal SYNC increases the count value NZ to 3.

[0158] At time t4, since the count value NZ is 3, the falling edge of the synchronization signal SYNC triggers the conversion control circuit 410 (phase sequence number ID_Z is 3) to enable the power stage circuit 40, thereby generating output power to the load 99, for example, by controlling the upper bridge switch of the power stage circuit 40 to be turned on, so that the switching node Sw3 is electrically connected to the input voltage VIN for a conduction time Ton. At the same time, the falling edge of the synchronization signal SYNC increases the count value NZ to 4.

[0159] In one embodiment, when the count value NZ reaches the start phase number, a reset signal RX is generated. In this embodiment, the maximum value is 4. Therefore, when the count value NZ is 4, the rising edge of the synchronization signal SYNC is used to trigger the reset signal RX to reset the count value (for example, at time point t0') and proceed to the next cycle.

[0160] In another embodiment, if Figure 8 As shown, the pulses of the synchronization signal SYNC with a higher voltage level (e.g., a high level VH) are used to indicate the reset signal RX, and the other pulses of the synchronization signal SYNC may be pulses with a lower voltage level (e.g., a low level VL). From one point of view, the reset signal RX in this embodiment is modulated or mixed in a plurality of pulses of the synchronization signal SYNC, and when the voltage level of the synchronization signal SYNC is higher than a threshold value VTH, the local reset signal RX is generated.

[0161] The present invention has been described above with respect to the preferred embodiment, but the above is only to make it easy for those skilled in the art to understand the content of the present invention, and is not used to limit the scope of the rights of the present invention. The various embodiments described are not limited to individual applications, but can also be used in combination. For example, two or more embodiments can be used in combination, and part of the components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the present invention refers to "processing or calculating or generating an output result according to a certain signal", which is not limited to the signal itself, but also includes, when necessary, converting the signal to voltage and current, current and voltage, and / or ratio conversion, and then processing or calculating according to the converted signal to generate an output result. It can be seen that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not listed one by one here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A conversion control circuit for controlling a stackable sub-converter, wherein a plurality of stackable sub-converters are configured as a stackable multi-phase power converter, wherein each of the plurality of stackable sub-converters comprises a power stage circuit and a corresponding conversion control circuit, wherein the plurality of power stage circuits corresponding to the plurality of stackable sub-converters are coupled in parallel to each other to generate an output power to a load, wherein the output power comprises an output current, wherein the conversion control circuit is used to control at least one switch of the power stage circuit to switch a corresponding inductor, thereby generating the output power, wherein the conversion control circuit is configured as a master circuit or a slave circuit, wherein the plurality of stackable sub-converters have a total number of phases and a number of start-up phases, wherein the number of start-up phases is determined according to the level of the output current, and the conversion control circuit comprises: A current balancing terminal, wherein a current balancing signal is coupled to a plurality of current balancing terminals of a plurality of the conversion control circuits connected in parallel; a current balancing circuit for generating and / or receiving the current balancing signal, and for generating an adjustment signal according to a difference between the current balancing signal and a corresponding sub-current sensing signal, so as to adjust at least one parameter of the conversion control circuit, so as to balance the current among the plurality of stackable sub-converters, wherein the sub-current sensing signal is related to an inductor current corresponding to the corresponding inductor; The current balancing circuit includes the following configuration: Configuration 1: wherein the current sharing signal is generated only according to the inductor current corresponding to one of the plurality of inductors of the plurality of stackable sub-converters; or Configuration 2: wherein the current sharing signal is generated based on a plurality of inductor currents corresponding to a plurality of inductors corresponding to a plurality of startup phases in the plurality of stackable sub-converters, wherein a ratio of a component of the current sharing signal generated by the master control circuit to a component generated by one of the slave circuits is k, wherein k is related to a difference between the total number of phases and the number of startup phases.

2. The conversion control circuit according to claim 1, wherein: In the first configuration, the current sharing signal is generated only according to the inductor current corresponding to the main control circuit.

3. The conversion control circuit according to claim 2, wherein: The current balancing circuit corresponding to the master control circuit does not generate the adjustment signal and does not adjust the at least one parameter of the conversion control circuit, wherein each corresponding current balancing circuit of the slave circuit generates the adjustment signal to adjust the corresponding at least one parameter to perform current balancing among the multiple stackable sub-converters.

4. The conversion control circuit according to claim 1, wherein: In the second configuration, each corresponding current balancing circuit of the master circuit and the slave circuit generates the corresponding adjustment signal to adjust the corresponding at least one parameter to balance the current among the plurality of stackable sub-converters.

5. The conversion control circuit according to claim 1, wherein: The conversion control circuit controls the at least one switch of one of the plurality of stackable sub-converters at a fixed time, wherein the fixed time is determined according to a threshold voltage, an integrated capacitance value or an integrated current; The adjustment signal is used to adjust the at least one parameter to adjust the fixed time, thereby performing current sharing among the plurality of stackable sub-converters, wherein the at least one parameter includes at least one of the threshold voltage, the integration capacitance value and the integration current.

6. The conversion control circuit according to claim 5, wherein: It also includes a transduction circuit and a filtering circuit, wherein the transduction circuit is used to generate a transduction current according to the difference between the corresponding sub-current sensing signal and the current equalizing signal, and the filtering circuit is used to generate an amplified output signal according to the transduction current, wherein the adjustment signal corresponds to the amplified output signal, and the amplified output signal corresponds to the threshold voltage.

7. The conversion control circuit according to claim 2, wherein: The conversion control circuit also includes: a synchronization terminal, wherein a synchronization signal is coupled to a plurality of synchronization terminals of a plurality of the conversion control circuits connected in parallel; The synchronization signal includes a plurality of pulses, the plurality of pulses are counted continuously as a count value, and the synchronization signal includes a reset signal for resetting and starting the count value; When the count value is related to a phase sequence number corresponding to the conversion control circuit, the conversion control circuit enables the corresponding power stage circuit to generate the output power; The master control circuit is used to generate the synchronization signal via the synchronization end, and the slave circuit is used to receive the synchronization signal via the synchronization end.

8. The conversion control circuit according to claim 7, wherein: When the count value reaches the start phase number, the reset signal is generated, wherein a pulse of the synchronization signal with a higher voltage level is used to indicate the reset signal.

9. The conversion control circuit according to claim 7, wherein: The stackable sub-converter is activated by being triggered by a corresponding pulse of the synchronization signal.

10. The conversion control circuit according to claim 6, wherein: The conversion control circuit is configured as an integrated circuit, the synchronization end corresponds to a synchronization pin of the integrated circuit, and the current balancing end corresponds to a current balancing pin of the integrated circuit.

11. A control method for controlling a stackable sub-converter, wherein a plurality of stackable sub-converters are configured as a stackable multi-phase power converter, wherein each of the plurality of stackable sub-converters comprises a power stage circuit, wherein the plurality of power stage circuits corresponding to the plurality of stackable sub-converters are coupled in parallel to each other to generate an output power to a load, wherein the power stage circuit comprises at least one switch to switch an inductor to generate the output power, wherein one of the plurality of stackable sub-converters is configured as a master stackable sub-converter, and the other of the plurality of stackable sub-converters is configured as a slave stackable sub-converter, wherein the plurality of stackable sub-converters have a total number of phases and a start-up number of phases, the control method comprising: Controlling the at least one switch of the power stage circuit to switch the corresponding inductor; Each of the plurality of stackable sub-converters is used to generate or receive a current sharing signal; and Performing current sharing among the plurality of stackable sub-converters according to the current sharing signal; The step of generating the current sharing signal includes one of the following methods: Method 1: The current sharing signal is generated only according to an inductor current corresponding to one of the plurality of inductors of the plurality of stackable sub-converters; or Method 2: The current sharing signal is generated according to a plurality of inductor currents corresponding to a plurality of inductors corresponding to a plurality of startup phases in the plurality of stackable sub-converters, wherein a ratio of a component of the current sharing signal generated by the master stackable sub-converter to a component generated by one of the slave stackable sub-converters is k, wherein k is related to a difference between the total number of phases and the number of startup phases.

12. The control method according to claim 11, wherein: In the first approach, the current sharing signal is generated only according to the inductor current corresponding to the master stackable sub-converter.

13. The control method according to claim 12, wherein: The master stackable sub-converter does not adjust the corresponding power stage circuit, wherein each of the slave stackable sub-converters adjusts the corresponding power stage circuit to adjust the corresponding at least one parameter to perform current sharing among the plurality of stackable sub-converters.

14. The control method according to claim 11, wherein: In the second method, an adjustment signal corresponding to each of the master stackable sub-converter and the slave stackable sub-converter is generated to adjust at least one parameter corresponding to each of the master stackable sub-converters to perform current sharing among the plurality of stackable sub-converters.

15. The control method according to claim 11, wherein: Also includes: Controlling the at least one switch of a corresponding one of the plurality of stackable sub-converters with a fixed time, wherein the fixed time is determined according to a threshold voltage, an integrated capacitance value or an integrated current; as well as At least one parameter of the plurality of stackable sub-converters is adjusted according to the current sharing signal to adjust the fixed time, thereby performing current sharing among the plurality of stackable sub-converters, wherein the at least one parameter includes at least one of the threshold voltage, the integration capacitance value and the integration current.

16. The control method according to claim 15, wherein: It also includes: generating a transduction current according to the difference between a corresponding sub-current sensing signal and the current averaging signal, and generating an amplified output signal according to the transduction current, wherein the amplified output signal corresponds to the threshold voltage, and the sub-current sensing signal is related to the inductor current.

17. The control method according to claim 12, wherein: Also includes: Controlling the master stackable sub-converter to generate a synchronization signal; Controlling the slave stackable sub-converter to receive the synchronization signal; wherein the synchronization signal includes a plurality of pulses, the plurality of pulses are counted continuously as a count value, wherein the synchronization signal includes a reset signal for resetting and starting the count value; as well as When the count value is related to a corresponding phase sequence number, a corresponding power stage circuit is enabled to generate the output power.

18. The control method according to claim 17, wherein: The method further comprises: using a pulse of the synchronization signal with a higher voltage level to indicate the reset signal, wherein when the count value reaches the start-up phase number, the reset signal is generated.

19. The control method according to claim 17, wherein: The invention also includes: starting the stackable sub-converter according to the triggering of a corresponding pulse of the synchronization signal.

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