FPGA (Field Programmable Gate Array) signal processing method and system based on multi-term filter

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) signal processing method based on a multi-term filter, which comprises a multi-term decimation filtering method and a multi-term interpolation filtering method, and the multi-term decimation filtering method specifically comprises the following steps: performing FPGA sampling to obtain 16 paths of AD sampling data, filtering each path of AD sampling data through a sub-filter, and summing filtering results to obtain single-path data; the multi-term interpolation filtering method specifically comprises the step of enabling single-path DA data to pass through a 16-time interpolation filtering multi-phase filter to obtain 16-path DA data. According to the invention, multi-path AD signals are changed into single-path AD signals, single-path DA data are changed into multi-path DA data meeting the requirements of a DAC module, and multi-path to single-path signal extraction and single-path to multi-path signal interpolation can be flexibly supported so as to adapt to the requirements of different sampling rates and data paths.

Description

Technical Field

[0001] The invention belongs to the technical field of FPGA signal processing, and in particular relates to an FPGA signal processing method based on multiple filters and a system thereof. Background Art

[0002] In modern signal processing, communication, radar and electronic countermeasure systems, polyphase filtering technology has been widely used in data extraction and interpolation processing. Polyphase filters have the advantages of parallel processing, frequency reduction and anti-aliasing, so they are particularly important in high data rate and complex signal environments. Especially in high-performance field programmable gate arrays (FPGAs), polyphase filters can significantly improve data processing efficiency. However, there are many limitations in the design and implementation of existing polyphase filters, which makes it difficult to fully meet the needs of multi-channel signal conversion in FPGAs.

[0003] In FPGA application scenarios, especially in systems with sampling rates as high as several GHz, the ADC sampling module usually decomposes a single-channel signal into multiple low-rate signals, such as outputting 16 channels of 150M data at a 2.4G sampling rate. However, these multiple channels of data need to be reintegrated into a single channel in subsequent processing of the FPGA, or the single channel signal needs to be converted into the multiple channels required by the DAC, which requires a multi-phase filtering technology that can effectively support the conversion of multiple channels to single channels (or single channels to multiple channels) signals. Summary of the invention

[0004] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution:

[0005] A FPGA signal processing method based on multiple filters includes multiple extraction filtering methods and multiple interpolation filtering methods.

[0006] The multi-channel decimation filtering method is specifically as follows: FPGA sampling obtains 16 channels of AD sampling data, each channel of AD sampling data is then filtered by a sub-filter, and the filtering results are summed to obtain a single channel of data;

[0007] The multi-phase interpolation filtering method is specifically as follows: a single channel of DA data is passed through a 16-fold interpolation filtering multi-phase filter to obtain 16 channels of DA data.

[0008] The technical solution of the present invention is further defined as follows: in the multi-decimation filtering method, the processing method for 16-channel AD sampling data is specifically:

[0009] (1) The coefficients of the polyphase filter are stored in a two-dimensional array in advance to obtain an array a[15:0][7:0] with 16 rows and 8 columns. The filter coefficients are stored in sequence starting from the first row of the first column of the array. After storing one column, the next column is stored.

[0010] (2) The 16 channels of AD sampling data are sequentially passed through an array b[15:0][7:0] with 16 rows and 8 columns. Each channel of 150M clock AD sampling data advances one column in array b, and the numbers in the corresponding positions of array a and array b are multiplied. The results of the multiplication are summed to obtain a single channel of data.

[0011] Furthermore, in the multi-phase interpolation filtering method, the specific method of passing the single-channel DA data through a 16-fold interpolation filtering multi-phase filter is:

[0012] (1) The coefficients of the polyphase filter are stored in a two-dimensional array in advance to obtain an array c[15:0][7:0] with 16 rows and 8 columns. The filter coefficients are stored in sequence starting from the first row of the first column of the array. After storing one column, the next column is stored.

[0013] (2) Let the single-channel DA data pass through an 8-row array d[7:0] in sequence. Each DA data advances one column in array d[7:0]. Multiply the numbers in array d with the numbers in the corresponding positions of each row in array a in sequence. The results of the multiplication of each row are summed up to obtain the DA data of the channel.

[0014] Beneficial effects:

[0015] The method of the present invention proposes a solution based on polyphase filtering to meet the needs of two scenarios in FPGA, realizes the conversion of multi-channel AD signals into single-channel AD signals and the conversion of single-channel DA data into multi-channel DA data that meets the needs of DAC modules, and can flexibly support multi-channel to single-channel signal extraction and single-channel to multi-channel signal interpolation to meet the requirements of different sampling rates and data paths. At the same time, the solution should be able to achieve efficient parallel processing in limited FPGA resources, reduce clock frequency requirements, ensure real-time performance, and provide effective support for data processing in high-speed signal systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 An example diagram of a polyphase decimation filter in an FPGA signal processing method based on multiple filters;

[0017] Figure 2 This is an example diagram of a multi-phase interpolation filter in an FPGA signal processing method based on multiple filters. DETAILED DESCRIPTION

[0018] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0019] Embodiment 1

[0020] This embodiment provides an FPGA signal processing method based on multiple filters, including a multiple extraction filtering method and a multiple interpolation filtering method.

[0021] The multi-channel decimation filtering method is specifically as follows: FPGA sampling obtains 16 channels of AD sampling data, each channel of AD sampling data is then filtered by a sub-filter, and the filtering results are summed to obtain a single channel of data;

[0022] The multi-phase interpolation filtering method is specifically as follows: a single channel of DA data is passed through a 16-fold interpolation filtering multi-phase filter to obtain 16 channels of DA data.

[0023] The specific implementation method of this embodiment is:

[0024] 1. Multi-item decimation filtering method

[0025] The ADC sampling module in the FPGA obtains 16 channels of sampling data. These 16 channels of data are obtained by the ADC module delaying and extracting the single channel of sampling data. For example, if the sampling rate of the ADC module is 2.4G, it delays and extracts the single channel of sampling data to obtain 16 channels with a sampling rate of 150M. Figure 1 If you want to perform 16-fold decimation on the 16 sampling data output by the ADC sampling module, you need to perform multi-phase filtering and summing. This embodiment takes a 128-order multi-phase filter as an example.

[0026] The 16-channel sampling data output by the ADC module only needs to pass through the sub-filters of each branch separately, and then sum the filtering results to obtain data with a single sampling rate of 150M. Figure 1 As shown, the details are as follows: (1) The coefficients of the polyphase filter (taking the 128th order as an example) are stored in a two-dimensional array in advance to obtain an array a[15:0][7:0] with 16 rows and 8 columns. The filter coefficients are stored in sequence from the first row of the first column of the array. After storing one column, the next column is stored. (2) The 16 channels of AD data are sequentially passed through an array b[15:0][7:0] with 16 rows and 8 columns. Each 150M clock AD data advances one column in array b, and the numbers in the corresponding positions of array a and array b are multiplied. The multiplication results are summed to obtain data with a single channel sampling rate of 150M.

[0027] 2. Multi-item interpolation filtering method

[0028] The sampling rate of the input data is 150M and the DAC module needs 16 channels of 150M DA signals, which requires delaying and extracting the interpolated 2.4G sampling rate data to get the data required by the DAC module. However, this is obviously unreasonable and does a lot of invalid processing. In fact, only a multi-phase filter is needed to get 16 channels of 150M signals.

[0029] In this embodiment, the single-channel DA data is passed through a 16-fold interpolation filter, and the multi-phase difference filter is as follows: Figure 2 As shown, the details are as follows: (1) Store the coefficients of the polyphase filter (taking 128th order as an example) in a two-dimensional array in advance to obtain an array c[15:0][7:0] with 16 rows and 8 columns. Store the filter coefficients in sequence from the first column and the first row of the array. After storing one column, store the next column. (2) Let the single-channel DA data pass through an 8-row array d[7:0] in sequence. Each DA data advances one column in the array d[7:0]. Let the numbers in array d be multiplied with the numbers in the corresponding positions of each row of a in sequence. The results of the multiplication of each row are summed up to obtain the DA data of the channel. There are 16 rows in total, so 16 channels of DA data are obtained.

[0030] In this embodiment, the multi-phase filter can reduce the clock frequency requirement and FPGA resource usage by decomposing the filter structure into multiple branches for parallel processing. In multi-channel to single-channel extraction, the multi-phase extraction filter can integrate the data output by multiple ADCs into a single signal while maintaining signal integrity; in single-channel to multi-channel interpolation, the multi-phase interpolation filter can add delay and interpolation to the single signal in order to output a data stream that meets the multi-channel requirements of the DAC. Therefore, flexible conversion from multi-channel to single channel and single channel to multi-channel is achieved: multi-channel to single channel extraction and single channel to multi-channel interpolation are achieved through multi-phase filters to meet the requirements of different signal channels.

[0031] Through the parallel branch and weighted summation method, the clock frequency requirement of FPGA is reduced and the signal processing efficiency is improved.

[0032] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any form, and any technical solution obtained by equivalent replacement or equivalent transformation falls within the protection scope of the present invention.

Claims

1. A FPGA signal processing method based on multiple filters, including multiple extraction filtering methods and multiple interpolation filtering methods, characterized in that: The multi-channel decimation filtering method is specifically as follows: FPGA sampling obtains 16 channels of AD sampling data, each channel of AD sampling data is then filtered by a sub-filter, and the filtering results are summed to obtain a single channel of data; The multi-phase interpolation filtering method is specifically as follows: a single channel of DA data is passed through a 16-fold interpolation filtering multi-phase filter to obtain 16 channels of DA data.

2. The FPGA signal processing method based on multiple filters according to claim 1 is characterized in that: In the multi-decimation filtering method, the processing method for 16-channel AD sampling data is specifically as follows: The coefficients of the polyphase filter are stored in a two-dimensional array in advance to obtain an array a[15:0][7:0] with 16 rows and 8 columns. The filter coefficients are stored sequentially from the first row of the first column of the array. After storing one column, the next column is stored. The 16 channels of AD sampling data are sequentially passed through an array b[15:0][7:0] with 16 rows and 8 columns. Each channel of 150M clock AD sampling data advances one column in array b, and the numbers in the corresponding positions of array a and array b are multiplied. The results of the multiplication are summed to obtain single-channel data.

3. The FPGA signal processing method based on multiple filters according to claim 1 is characterized in that: In the multi-phase interpolation filtering method, the specific method of passing the single-channel DA data through a 16-fold interpolation filtering multi-phase filter is: (1) The coefficients of the polyphase filter are stored in a two-dimensional array in advance to obtain an array c[15:0][7:0] with 16 rows and 8 columns. The filter coefficients are stored in sequence starting from the first row of the first column of the array. After storing one column, the next column is stored. (2) Let the single-channel DA data pass through an 8-row array d[7:0] in sequence. Each DA data advances one column in array d[7:0]. Multiply the numbers in array d with the numbers in the corresponding positions of each row in array a in sequence. The results of the multiplication of each row are summed up to obtain the DA data of the channel.

Images