Driving circuit and pre-charging circuit system and operation method thereof

Abstract

A driving circuit includes a driving stage and a first sub-circuit. The driving stage includes a first driving device and a second driving device configured to drive the power device. The first sub-circuit is electrically connected to the driver stage. The first sub-circuit comprises a first pre-charging circuit and a first pre-driving circuit. The first pre-driving circuit is electrically connected to the first pre-charging circuit and the first driving device. The first pre-charge circuit is configured to generate a first pre-charge voltage in response to an input signal of the driving circuit having a first signal level. The first pre-charge circuit is further configured to fully turn on a first pre-driving device in the first pre-driving circuit to drive the first driving device based on the first pre-charge voltage in response to the input signal having a second signal level different from the first signal level. The embodiment of the invention further discloses a multi-stage pre-charging circuit of the driving circuit and a method for operating the driving circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to a drive circuit, a pre-charging circuit system of the drive circuit, and a method of operating the drive circuit. Background Art

[0002] GaN-on-Si technology represents a promising advancement for next-generation power devices. GaN-based high electron mobility transistors (HEMTs) offer improved performance compared to silicon-based transistors, including the ability to operate at higher frequencies, supply voltages, and temperatures. However, due to the lack of P-type GaN-based HEMTs in GaN processes, it will be challenging for designers to develop GaN-based drive circuits. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a driving circuit is provided, comprising: a driving stage, comprising a first driving device and a second driving device configured to drive a power device; and a first sub-circuit, electrically connected to the driving stage, the first sub-circuit comprising: a first pre-charging circuit; and a first pre-driving circuit, electrically connected to the first pre-charging circuit and the first driving device, wherein the first pre-charging circuit is configured to: generate a first pre-charging voltage in response to an input signal of the driving circuit having a first signal level, and fully turn on the first pre-driving device in the first pre-driving circuit based on the first pre-charging voltage to drive the first driving device in response to the input signal having a second signal level different from the first signal level.

[0004] According to one aspect of an embodiment of the present application, a multi-stage pre-charging circuit of a driving circuit is provided, the multi-stage pre-charging circuit comprising: a first pre-charging circuit, configured to generate a first boost driving voltage higher than a power supply voltage provided to the multi-stage pre-charging circuit in response to an input signal having a first signal level; and a second pre-charging circuit, electrically connected to the first pre-charging circuit, and configured to generate a second boost driving voltage based on the first boost driving voltage in response to an input signal having a first signal level.

[0005] According to another aspect of the embodiments of the present application, a method for operating a driving circuit is provided, wherein the driving circuit includes a first pre-charging circuit, a first pre-driving circuit and a driving stage, and the method includes: in response to an input signal being in a first logic state: storing a first pre-charging voltage through a first capacitor in the first pre-charging circuit; and in response to the input signal being in a second logic state different from the first logic state: boosting a first driving voltage for the first pre-driving circuit using the stored first pre-charging voltage through the first pre-charging circuit, and driving a first driving device in the driving stage with the boosted first driving voltage through the first pre-driving circuit to provide a first voltage corresponding to the supply voltage to the power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic diagram of a driving circuit according to an embodiment of the present disclosure.

[0008] Figure 2 is a schematic diagram of a driving circuit according to another embodiment of the present disclosure.

[0009] Figure 3 It is a waveform diagram of the output voltage of various driving circuits.

[0010] Figure 4A-4C are cross sections of different HEMTs according to embodiments of the present disclosure.

[0011] Figure 4D-4E are cross sections of HEMTs in different diode connection configurations according to different embodiments of the present disclosure.

[0012] Figure 5 is a cross section of a silicon-based transistor according to an embodiment of the present disclosure.

[0013] Figure 6 is a schematic diagram of a driving circuit according to yet another embodiment of the present disclosure.

[0014] Figure 7 is a flowchart of a method of operating a driving circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0017] Further, it will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it can be directly connected or coupled to the other element or intervening elements may be present.

[0018] Source / drain may be referred to individually or collectively as source or drain, depending on the context.

[0019] The embodiments or examples shown in the drawings are disclosed as follows using specific language. However, it should be understood that the embodiments and examples are not intended to be limiting. Any changes or modifications in the disclosed embodiments, as well as any further applications of the principles disclosed in this document, are generally contemplated by those of ordinary skill in the relevant art.

[0020] Furthermore, it will be appreciated that several processing steps and / or features of the device may be briefly described. Furthermore, additional processing steps and / or features may be added, and certain of the following processing steps and / or features may be deleted or altered while still implementing the present application. Therefore, it should be appreciated that the following description represents examples only and does not imply that one or more steps or features are required.

[0021] In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity, and does not in itself determine the relationship between the various embodiments and / or configurations discussed.

[0022] Compared to silicon-based metal oxide semiconductor field effect transistors (silicon-based MOSFETs), GaN-based HEMTs have lower threshold voltages and smaller source-drain on-resistances. These characteristics result in reduced gate drive power requirements and increased current and switching frequency capabilities. However, according to some embodiments, the low mobility of P-type HEMTs in integrated circuits manufactured using GaN processes has prompted the inclusion of enhancement-mode N-type HEMTs and depletion-mode N-type EMTs in the drive circuit.

[0023] Figure 1 is a schematic diagram of a driving circuit according to an embodiment of the present disclosure.

[0024] In some embodiments, the driving circuit 100 may be provided in an integrated circuit (IC) manufactured using a III-V process (eg, a GaN process). Figure 1 As shown, the driver circuit 100 can be configured to drive a power E-HEMT PQe (i.e., an enhanced N-type power HEMT) provided with a high voltage (HV) (e.g., about 650V). The driver circuit 100 may include inverters 110 and 120 in the same power domain (i.e., the supply voltage VDD), pre-charge circuits 112 and 122, pre-driver circuits 114 and 124, and a driver stage 130. More specifically, the driver circuit 100 may include a balanced pre-charge circuit system to provide a high boosted drive voltage to the pre-driver circuits 114 and 124, the details of which will be described later. In at least one embodiment, the transistors in the pre-driver circuits 114, 124 and other pre-driver circuits described herein are examples of pre-driver devices, and the transistors in the driver stage 130 and other driver stages shown herein are also examples of driver devices.

[0025] In some embodiments, since the driving circuit 100 does not include any P-type (ie, P-channel) HEMT, the type of the HEMT (ie, the channel type within the HEMT) is Figure 1 There is no specific marking in the figure. In addition, the enhancement-mode HEMT (abbreviated as E-HEMT) and the depletion-mode HEMT (abbreviated as D-HEMT) are represented by lowercase letters "e" and "d" in the reference numerals of the HEMT, respectively. In addition, the two enhancement-mode HEMTs of the same transistor pair may include a high-side HEMT and a low-side HEMT, which are represented by uppercase letters "U" and "D" at the end of the reference numerals of the HEMT, respectively. For example, Q1e and Q1d may represent the E-HEMT and D-HEMT of transistor pair 1, while Q2eU and Q2eD may represent the high-side E-HEMT and the low-side E-HEMT of transistor pair 2, respectively. Figure 1 The positions and / or patterns of other HEMTs in the can be determined in a similar manner. It should be noted that Figure 1 Each D-HEMT in the circuit may have a gate connected to its source, causing each D-HEMT to turn on due to its negative threshold voltage. In this case, each D-HEMT may act as a resistor to cause a current resistance (IR) voltage drop between its drain and source.

[0026] In some embodiments, the capacitors C1 and C2 may be fabricated using metal-insulator-metal (MIM) or metal-oxide-metal (MOM) technology at the BEOL (back-end-of-line) stage of a GaN process, but the present disclosure is not limited thereto.

[0027] In some embodiments, the inverter 110 may be an input stage of the upper portion of the driving circuit 100, which includes an E-HEMT Qinv1e and a D-HEMT Qinv1d. Although the two N-type HEMTs are in different modes, the E-HEMT Qinv1e and the D-HEMT Qinv1d may operate as inverters similar to a CMOS inverter, which includes an N-type transistor and a P-type transistor. The inverter 110 may receive an input signal S IN , which may be a control signal or an oscillation signal, and generates a voltage Vinv1 at its output terminal (e.g., node N1). The voltage Vinv1 may be used to control the E-HEMTs Q1e, Q2eD, and Q3eD in a subsequent stage. In addition, the voltage Vinv1 may be provided to the inverter 120 as an input stage of the lower portion of the driver circuit 100. In some embodiments, the voltage Vinv1 and other voltages with a label “Vinv” described herein are examples of voltage signals.

[0028] In some embodiments, the precharge circuit 112 can be configured to generate a boost voltage (eg, a voltage vout2 at the node N4) for the pre-driver circuit 114. IN is a digital signal in one of a low logic state (e.g., logic 0) or a high logic state (e.g., logic 1). IN When in a low logic state, the E-HEMT Qinv1e is turned off. Since the D-HEMT Qinv1d is turned on, the voltage Vinv1 at the node N1 may be equal to the supply voltage VDD minus the voltage drop across the D-HEMT Qinv1d, and it is in a high logic state capable of turning on the E-HEMTs Q1e, Q2eD, and Q3eD. Therefore, the voltage vout2 at the node N4 is pulled down to the ground voltage VSS, and the voltage vbs1 at the node N2 may be equal to the supply voltage VDD (e.g., 6V) minus the threshold voltage (e.g., 0.2V) VD of the diode D1. Therefore, the capacitor C1 may store a voltage approximately equal to VDD-VD (e.g., 5.8V) between its two terminals. In at least one embodiment, the low logic state is an example of one of the first signal level and the second signal level, and the high logic state is an example of the other of the first signal level and the second signal level. In some embodiments, voltage vbs1 and other voltages labeled “vbs” described herein are examples of pre-charge voltages, and voltage vout2 and other voltages labeled “vout” described herein are examples of boosted drive voltages, drive voltages, or boosted voltages.

[0029] When the input signal S INWhen switching from a low logic state to a high logic state, the E-HEMT Qinv1e is turned on, and the voltage Vinv1 at the node N1 can be pulled down to the ground voltage VSS through the E-HEMT Qiv1e. Therefore, the E-HEMTs Q1e, Q2eD, and Q3eD are turned off. Since the D-HEMT Q1d is turned on, the voltage vout1 at the node N3 is pulled up from the ground voltage to a voltage approximately equal to the voltage vbs1 at the node N2 minus the voltage drop across the D-HEMT Q1d (e.g., VDS Q1d ) voltage level, thereby turning on the E-HEMT Q2eU. Therefore, the voltage level vout2 at the node N4 is pulled up from the ground voltage to a voltage approximately equal to the supply voltage VDD minus the voltage drop of the E-HEMT Q2eU (e.g., VDS Q2eU ) voltage level.

[0030] Since the voltage vout2 at the lower end of the capacitor C1 (eg, node N4) is pulled up from the ground voltage to the supply voltage VDD minus the voltage drop of the E-HEMT Q2eU (eg, VDS Q2eU ), so the voltage vbs1 at the upper end of the capacitor C1 (e.g., node N2) is boosted to approximately equal to (VDD–VD)+(VDD–VDS Q2eU )=2*VDD–VD–VDS Q2eU Therefore, the voltage level vout1 at the node N3 is also boosted, enabling it to fully turn on the E-HEMT Q2eU. Therefore, the voltage VDS across the E-HEMT Q2eU is higher than the supply voltage VDD. Q2eU can be ignored, resulting in a voltage vout2 at node N4 being substantially equal to the supply voltage VDD. Since the E-HEMT Q3eU is driven by a voltage vout2 substantially equal to the supply voltage, the E-HEMT Q3eU can also be fully turned on to result in a voltage vout3 at node N5 also being substantially equal to the supply voltage VDD. In one or more embodiments, since the E-HEMT Q7eU is driven by a voltage vout3 substantially equal to the supply voltage VDD, the output voltage SOUT at node N11 can also be substantially equal to the supply voltage VDD, thereby providing a high driving capability to the power E-HEMT PQe during the voltage push-up duration. In some embodiments, a voltage is substantially equal to the supply voltage when the difference between the voltage and the supply voltage is negligible, for example, equal to or less than the voltage across a fully turned-on transistor. In at least one embodiment, “substantially equal to the supply voltage” includes “equal to the supply voltage.”

[0031] Specifically, in one or more embodiments, the upper portion of the driver circuit 100, including the inverter 110, the pre-charge circuit 112, the pre-driver circuit 114, and the E-HEMT Q7eU of the driver stage, can provide a high driving capability for the power E-HEMT PQe during the voltage push-up duration, thereby IN Reduce the voltage push-up duration when switching or oscillating between low and high logic states.

[0032] The lower part of the driving circuit 100 includes transistors Qinv2d, Qinv2e, Q4d, Q4e, Q5eU, Q5eD, Q6eU, Q6eD, diode D2, capacitor C2, nodes N6, N7, N8, N9, N10, voltages Vinv2, vbs2, vout4, vout5, vout6, which correspond to the transistors Qinv1d, Qinv1e, Q1d, Q1e, Q2eU, Q2eD, Q3eU, Q3eD, diode D1, capacitor C1, nodes N1, N2, N3, N4, N5, voltages Vinv1, vbs1, vout1, vout2, vout3 in the upper part of the driving circuit 100. The operation of the lower portion of the driver circuit 100 (including the inverter 120, the pre-charge circuit 122, the pre-driver circuit 124, and the E-HEMT Q7eD of the driver stage) can be similar to the operation of the upper portion of the driver circuit 100, except that the input signal of the lower portion of the driver circuit 100 is the voltage Vinv1 at the node N1, whose logic state is the same as the input signal S IN Therefore, in one or more embodiments, the lower portion of the driver circuit 100 can provide a high driving capability to the power E-HEMT PQe during the voltage pull-down duration, thereby IN Reduce the voltage push-up duration when switching or oscillating between low and high logic states.

[0033] Therefore, since the boosted voltage generated by the capacitors C1 and C2 in the pre-charge circuits 112 and 122 can be used to fully turn on the E-HEMTs (e.g., Q7eU and Q7eD in the driver stage) in the last stage before the power E-HEMT PQe, in one or more embodiments, this allows the driver circuit 100 to be fully turned on when the input signal S INThe invention provides a higher driving capability for the power E-HEMTPQe during the positive and negative voltage cycles, thereby reducing and balancing the voltage push-up duration and the voltage pull-down duration of the power E-HEMT PQe and increasing its switching frequency. In at least one embodiment, the pre-charging circuit or pre-charging circuit system of the driving circuit for achieving the balance between the voltage push-up duration and the voltage pull-down duration of the power device (such as the power e-HEMTPQe) (for example, the difference between the voltage push-up duration and the voltage pull-down duration is equal to or lower than a predetermined threshold) is referred to as a balanced pre-charging circuit or a balanced pre-charging circuit system.

[0034] Figure 1 The driving circuit 100 shown can have N-type E-mode and D-mode HEMTs, and does not use P-type HEMTs, which is convenient for designers to simulate the driving circuit 100. In addition, one supply voltage VDD is used in the driving circuit 100, which reduces the design complexity of the driving circuit 100. Since all components in the driving circuit 100, including E-HEMTs, D-HEMTs, power E-HEMTs, and diodes, can be manufactured using GaN processes, in one or more embodiments, the die for manufacturing the driving circuit 100 does not need to be connected to an external CMOS driver IC using existing co-packaging or wire bonding technology.

[0035] Figure 2 is a schematic diagram of a driving circuit according to another embodiment of the present disclosure.

[0036] Figure 2 The driving circuit 200 shown in FIG. 2 may be similar to Figure 1 The driver circuit 100 shown in FIG. 1 is different in that the driver circuit 200 includes a balanced two-stage pre-charging circuit system, wherein the pre-charging circuits 210 and 230 can form a first stage of the balanced two-stage pre-charging circuit system, and the pre-charging circuits 220 and 240 form a second stage of the balanced two-stage pre-charging circuit system. In addition, the pre-charging circuits 210 and 230 in the first stage can be similar to Figure 1 The difference between the pre-charge circuits 112 and 122 shown is that Figure 2 The gates of the E-HEMTs Q3e and Q6e shown in FIG. 2 are connected to nodes N4 and N9, respectively, instead of nodes N1 and N6. In addition, the precharge circuits 220 and 240 in the second stage include E-HEMTs (e.g., transistor pairs 20 to 21 and 30 to 31; transistor pair 20 represents Q20eU and Q20eD, transistor pair 21 represents Q21eU and Q21eD, and so on), and do not use D-HEMTs. The operation of the drive circuit 200 is described as follows.

[0037] In some embodiments, when the input signal S INWhen in a low logic state, the E-HEMT Qinv1e of the inverter 202 is turned off. Since the D-HEMT Qinv1d is turned on, the voltage Vinv1 generated by the inverter 202 at the node N1 may be equal to the supply voltage VDD minus the voltage drop across the D-HEMT Qinv1d, and the voltage Vinv1 is in a high logic state capable of turning on the E-HEMTs Q1e and Q2eD. Therefore, the voltage vout2 at the node N4 is pulled down to the ground voltage VSS through the E-HEMT Q2eD, and the voltage vbs1 at the node N2 may be equal to the supply voltage VDD (e.g., about 6V) minus the threshold voltage VD of the diode D1 (e.g., about 0.2V). Therefore, the capacitor C1 may store a voltage equal to VDD-VD (e.g., about 5.8V) between its two terminals (e.g., nodes N2 and N4).

[0038] With respect to the precharge circuit 220, since the voltage at the node N4 is pulled down to the ground voltage VSS, the HEMT Q3e is turned off. In addition, since the D-HEMT Q3d is turned on, the voltage at the node N20 can be pulled up to be equal to the supply voltage VDD minus the voltage drop VDS across the D-HEMT Q3d. Q3d The voltage level of the E-HEMT Q20eD, Q21eD and Q22eD is increased to cause the E-HEMTs Q20eD, Q21eD and Q22eD to turn on. Therefore, the voltages vout20, vout21 and vout22 at the nodes N21, N23 and N24 may be pulled down to the ground voltage VSS. It should be noted that the voltage vbs20 at the node N22 may be equal to the supply voltage VDD (e.g., about 6V) minus the threshold voltage VD of the diode D2 (e.g., about 0.2V). Therefore, the capacitor C3 may store a voltage equal to VDD-VD (e.g., about 5.8V) between its two terminals.

[0039] When the input signal S IN When switching from a low logic state to a high logic state, the E-HEMT Qinv1e turns on, causing the voltage Vinv1 at the node N1 to be pulled down to the ground voltage VSS through the E-HEMT Qiv1e. Therefore, the E-HEMTs Q1e and Q2eD are turned off. Since the D-HEMT Q1d is turned on, the voltage vout1 at the node N3 is pulled up from the ground voltage through the D-HEMT Q1d to approximately equal the voltage vbs1 at the node N2 minus the voltage drop VDS across the D-HEMT Q1d. Q1d Thus, the voltage at node N4 can be pulled up from the ground voltage to a voltage level approximately equal to the supply voltage VDD minus the voltage drop of the E-HEMT Q2eU (e.g., VDS Q2eU ) voltage level.

[0040] Since the voltage vout2 at the lower end of the capacitor C1 (eg, node N4) is pulled up from the ground voltage to the supply voltage VDD minus the voltage drop VDS of the E-HEMT Q2eU, Q2eU Therefore, the voltage vbs1 at the upper end of the capacitor C1 (e.g., node N2) is increased to approximately (VDD-VD)+(VDD-VDS Q2eU )=2*VDD-VD-VDS Q2eU Therefore, the voltage vout1 at the node N3 can also be boosted to a higher voltage level (eg, 2*VDD-VD-VDS). Q2eU -VDS Q1d ), this voltage level is provided to the E-HEMT Q20eU of the precharge circuit 220, thereby completely turning on the E-HEMT Q20eU.

[0041] It should be noted that since the voltage at the node N4 is pulled up to a high voltage (eg, VDD-VDS Q2eU ), the E-HEMT Q3e in the control circuit 212 is turned on, and the voltage at the node N20 may be pulled down to the ground voltage VSS, causing the E-HEMTs Q20eD, Q21eD, and Q22eD to be turned off. In addition, since the E-HEMT Q21eU is turned on, the voltage vout21 at the node N23 may be pulled up to a value equal to the supply voltage VDD minus the voltage drop VDS across the E-HEMT Q21eU. Q21eU Since the voltage vout21 at the lower end of the capacitor C3 (eg, node N23) is pulled up from the ground voltage to the supply voltage VDD minus the voltage drop VDS of the E-HEMTQ21eU, Q21eU Therefore, the voltage vbs20 at the upper end of the capacitor C3 (eg, the node N22) can be boosted to approximately equal to (VDD-VD)+(VDD-VDS Q21eU )=2*VDD-VD-VDS Q21eU Therefore, the voltage vout20 at the node N21 can also be boosted to a higher voltage level (eg, 2*VDD-VD-VDS). Q21eU -VDS Q20eU ), where the voltage drop VDS of E-HEMTQ20eU Q20eUThe voltage vout22 at the node N24 may be pulled up to a voltage level substantially equal to the supply voltage VDD, thereby fully turning on the E-HEMT Q33eU in the driver stage 250. In one or more embodiments, since the E-HEMT Q33eU is driven by the voltage vout22 substantially equal to the supply voltage VDD, the output voltage SOUT2 at the node N35 may also be substantially equal to the supply voltage VDD, thereby providing a high driving capability to the power E-HEMT PQe during the voltage push-up duration.

[0042] It is worth noting that the driving voltage of the high-side E-HEMT Q22eU in the pre-driver circuit 222 (e.g., vout21 at the node N23) can be raised to a voltage level higher than the voltage vout1 at the node N3 (before the voltage vout1 is boosted by the capacitor C1) because the high-side E-HEMT Q20eU of the pre-charge circuit 220 (e.g., the second stage) can have a very low voltage drop VDS. Q21eU This is because the voltage vout1 at the node N3 in the pre-charge circuit 210 completely turns on the high-side E-HEMTQ21eU.

[0043] Specifically, in one or more embodiments, Figure 2 The upper portion of the driving circuit 200 shown can provide high driving capability for the power E-HEMT PQe during the voltage push-up duration, thereby IN Shortens the voltage push-up duration when switching to a high logic state.

[0044] Similarly, Figure 2The lower portion of the driver circuit 200 shown may include an inverter 204 , a pre-charge circuit 230 , a control circuit 232 , a pre-charge circuit 240 , and a pre-driver circuit 242 . Specifically, the lower part of the driving circuit 200 includes transistors Q6d, Q6e, Q30eU, Q30eD, Q31eU, Q31eD, Q32eU, Q32eD, diode D4, capacitor C4, nodes N30, N31, N32, N33, N34, voltages vbs30, vout30, vout31, vout32, which correspond to the transistors Q3d, Q3e, Q20eU, Q20eD, Q21eU, Q21eD, Q22eU, Q22eD, diode D3, capacitor C3, nodes N20, N21, N22, N23, N24, voltages vbs20, vout20, vout21, vout22 of the upper part of the driving circuit 200. Figure 2 The operation of the lower portion of the driving circuit 200 shown may be similar to the operation of the upper portion of the driving circuit, except that the input signal of the lower portion of the driving circuit 200 is the voltage Vinv1 at the node N1, whose logic state is different from the input signal S IN Therefore, in one or more embodiments, the lower portion of the driver circuit 200 can provide a high driving capability for the power E-HEMT PQe during the voltage pull-down duration, thereby IN The voltage pull-down duration is reduced when switching to a low logic state. The described two-stage pre-charge circuitry is an example of a multi-stage pre-charge circuit. In some embodiments, the multi-stage pre-charge circuitry includes more than two stages.

[0045] A drive circuit according to one or more other methods of the first type includes an inverter chain including a plurality of inverters connected in series. Each inverter or stage includes a high-side D-HEMT and a low-side E-HEMT. Such a drive circuit may have one or more of the following disadvantages, such as a larger quiescent current, a longer voltage push-up and pull-down duration, and a lower drive capability. As described herein, a drive circuit according to some embodiments overcomes one or more of these disadvantages.

[0046] A drive circuit according to one or more other methods of the second type includes an inverter chain including a first stage and a last stage connected in series. The first stage includes a high-side D-HEMT and a low-side E-HEMT. The last stage of the driving power device includes a high-side E-HEMT and a low-side E-HEMT. Such a drive circuit may have one or more of the following disadvantages, such as a lower voltage swing range, a longer voltage push-up duration, and a lower driving capability. The drive circuit according to some embodiments overcomes one or more of these disadvantages, as described herein.

[0047] In addition, the driving circuit according to one or more other methods of the first type or the second type described above may have a longer voltage push-up duration, resulting in a larger push-pull time ratio Tr / Tf for the voltage push-up duration (Tr) and the voltage pull-down duration (Tf). This may cause the voltage push-up duration (Tr) and the voltage pull-down duration (Tf) of the high-side HEMT and the low-side HEMT to overlap. The long push-pull time ratio Tr / Tf may cause a short-circuit current through the high-side HEMT and the low-side HEMT, increase the hot carrier injection into the HEMT, reduce the switching frequency of the power HEMT, and increase the conduction loss. For example, the short-circuit current through the high-side HEMT and the low-side HEMT may burn out the high-side HEMT and the low-side HEMT. Increasing the hot carrier injection into the HEMT may result in reduced reliability. The lower switching frequency of the power HEMT may result in a larger form factor (e.g., a larger product size). Higher conduction losses may indicate that the impedance of the high-side HEMT and the low-side HEMT is higher, which may be caused by the low driving capability of the half-bridge rectifier.

[0048] Figure 3 It is a waveform diagram of the output voltage of various driving circuits.

[0049] Curve 302 may show the output voltage (e.g., gate voltage of the power E-HEMT) of a first type of driver circuit including an inverter chain for driving a power E-HEMT. Each stage or inverter includes a high-side D-HEMT and a low-side E-HEMT. Due to the limited driving capability of the high-side D-HEMT in the last stage, the voltage push-up duration of the power E-HEMT may be much longer than the pull-down duration, which is attributed to the gate of the power E-HEMT not reaching the full voltage swing and the limited driving capability of the last stage high-side D-HEMT. Figure 3 As shown, the voltage push-up duration from point 3021 to point 3022 may be about 120 ns, where points 3021 and 3022 may represent time points at 10% and 90% of the maximum voltage swing (e.g., about 5.8 V). The voltage drop duration from point 3023 to point 3024 may be about 9.9 ns, where points 3023 and 3024 may represent time points at 90% and 10% of the maximum voltage swing (e.g., about 5.8 V).

[0050] Curve 304 may show the output voltage (e.g., gate voltage of the power E-HEMT) of a second type of driving circuit for driving a power E-HEMT, the driving circuit including a first stage of a high-side D-HEMT and a low-side E-HEMT, and a last stage of a high-side E-HEMT and a low-side E-HEMT. The voltage drop across the last stage of the high-side E-HEMT may be quite large, which may be approximately equal to the threshold voltage Vt (e.g., 1.4V) of the high-side E-HEMT at the last stage. Therefore, the maximum voltage for driving the power E-HEMTPQe may be limited to approximately VDD-Vt=6-1.4=4.6V. Figure 3 As shown, the voltage push-up duration from point 3041 to point 3042 may be about 18.2 ns, where points 3041 and 3042 may represent time points at 10% and 90% of the maximum voltage swing (e.g., about 4.6 V). The voltage push-down duration from point 3043 to point 3044 may be about 6.9 ns, where points 3043 and 3044 may represent time points at 90% and 10% of the maximum voltage swing (e.g., about 4.6 V).

[0051] In one or more embodiments, curve 306 may show Figure 1 . For example, for the pre-charge circuits 112 and 122 and the pre-driver circuits 114 and 124, the gate voltages of the E-HEMTs Q7eU and Q7eD in the driver stage 130 are approximately equal to the supply voltage. In addition, as the driving capability of the pre-driver circuits 114 and 124 is improved, when the input signal S IN When the voltage SOUT of the node N11 (e.g., the gate voltage of the power E-HEMT PQe) is positive and negative, respectively, the E-HEMT Q7eU and Q7eD in the driver stage 130 can be fully turned on. Therefore, the voltage SOUT at the node N11 (e.g., the gate voltage of the power E-HEMT PQe) can be approximately equal to the supply voltage, resulting in a shorter voltage push-up duration and a shorter voltage pull-down duration. Figure 3 As shown, the voltage push-up duration from point 3061 to point 3062 may be approximately 0.49 ns, where points 3061 and 3062 may represent time points at 10% and 90% of the maximum voltage swing (e.g., approximately 6V) of the driver circuit 100. The voltage push-down duration from point 3063 to point 3064 may be approximately 0.40 ns, where points 3063 and 3064 may represent time points at 90% and 10% of the maximum voltage swing (e.g., approximately 6V) of the driver circuit 100. In one or more embodiments, since the voltage push-up duration and the voltage pull-down duration of the driver circuit 100 are relatively faster than the voltage push-up duration and the voltage pull-down duration of the driver circuit described in the method associated with curves 302 and 304, Figure 1The switching time of the power E-HEMT PQe in the drive circuit 100 is faster and the operating frequency is higher. The voltage push-up duration (eg, 0.49 ns) and the voltage pull-down duration (eg, 0.40 ns) are substantially equal, which is an example result that can be achieved by the balanced pre-charging circuit of the drive circuit 100.

[0052] It should be noted that Figure 3 The curves 302 to 306 in FIG. 3 are for illustration only, and they may vary depending on the actual specifications of the HEMT in the driving circuit, such as the supply voltage used, the channel width, the thickness of the p-GaN layer, etc.

[0053] Figure 4A-4C are cross sections of different HEMTs according to embodiments of the present disclosure.

[0054] In some embodiments, Figure 4A The HEMT 400 shown in FIG. 4 may be a GaN-based D-HEMT for high voltage applications (eg, 12 V). The HEMT 400 may be implemented using a Schottky gate structure including a substrate 414, a GaN layer 412, and an AlGaN layer 410, such as Figure 4A As shown. The GaN layer 412 and the AlGaN layer 410 may form a heterojunction. The gate electrode 402, the drain electrode 404, and the source electrode 406 (e.g., metal) may be formed on the top surface 410s1 of the AlGaN layer 410. When a voltage bias VDS is applied between the drain 404 and the source 406 of the HEMT 400, a lateral electric field is established, and the two-dimensional electron gas (2DEG) 411 under the gate electrode 402 may serve as a current ID of the HEMT 400. S Flow along the channel of the AlGaN / GaN heterojunction. It should be noted that HEMT 400 may have a negative threshold voltage and it is inherently in a normally-on state. When a negative voltage lower than the threshold voltage of HEMT 400 is applied to gate electrode 402, HEMT 4000 may be turned off. It should be noted that in Figure 4A In the structure of the HEMT 400 shown, the positions of the drain 404 and the source 406 relative to the gate electrode 402 may be symmetrical. In some embodiments, Figure 1 and Figure 2 The D-HEMT shown in the figure can be used Figure 4A This is achieved using the HEMT 400 shown in FIG.

[0055] In some embodiments, Figure 4B The HEMT 420 shown in FIG. 4 may be a GaN-based E-HEMT for high voltage applications (eg, 12 V). Figure 4B The structure of the HEMT 420 shown is similar to Figure 4AThe structure of HEMT 400 is shown, except that a p-type GaN (p-GaN) layer 428 is inserted between the gate electrode 422 and the AlGaN layer 430. Therefore, HEMT 420 can be regarded as an E-HEMT. By high p-type doping (e.g., Mg) in the p-GaN layer 428, the 2DEG 431 under the gate electrode 422 will be depleted, which may result in a positive threshold voltage of HEMT 420. In some embodiments, Figure 1 and Figure 2 The E-HEMT shown in the Figure 4B This is achieved using the HEMT 420 shown in FIG.

[0056] In some embodiments, Figure 4C The structure of the HEMT 440 shown is similar to Figure 4B The structure of HEMT 420 shown is different in that Figure 4C The positions of the drain 444 and source 446 relative to the gate 442 in the HEMT 440 structure shown in FIG. 4 may be asymmetric. Specifically, the gate electrode 442 and the P-type GaN layer 448 may be closer to the drain electrode 444, and the gate electrode 442 and the P-type GaN layer 448 may be closer to the drain electrode 444. Figure 4C The structure in FIG. 4 applies a very high voltage (e.g., 650 V) to the drain electrode 444 of the HEMT 440. In some embodiments, Figure 1 and Figure 2 The power E-HEMT shown in the Figure 4C This is achieved using the HEMT 440 shown in FIG.

[0057] Figure 4D-4E are cross sections of HEMTs in different diode connection configurations according to different embodiments of the present disclosure.

[0058] In some embodiments, Figure 1 and Figure 2 Each of the diodes D1 to D4 shown in FIG. Figure 4B For example, Figure 4D As shown, the drain 424 can be electrically connected to the source 426 through the metal 460, so that the interface between the p-GaN layer 428 and the AlGaN layer 430 forms a pN junction of a diode, the anode is the gate electrode 442, and the cathode is the drain 424 and the source 426. Alternatively, as Figure 4E As shown, the gate electrode 422 can be electrically connected to the drain 424 through the metal line 462. Figure 4E In the configuration shown, the HEMT 420 can be used as a diode, with the anodes being the gate electrode 422 and the drain 424 , and the cathode being the source 426 .

[0059] It should be noted that FIG. 4A to FIG. 4EThe cross sections of the GaN-based E-HEMT, D-HEMT, and power E-HEMT depicted in FIG. are for illustration purposes only. Figure 1 and Figure 2 The embodiments described in the present invention may be implemented using existing or future developed structures in GaN-based E-HEMTs, D-HEMTs, and power E-HEMTs.

[0060] Figure 5 is a cross-sectional view of a silicon-based transistor according to an embodiment of the present disclosure.

[0061] exist Figure 5 In the example configuration of FIG. 5 , a cross section of a silicon-based N-type transistor 500 is shown. It should be noted that Figure 5 In the structure of the silicon-based transistor 500 shown, the positions of the drain 512 and the source 510 relative to the gate electrode 508 can be symmetrical. For example, the substrate 518 can be or include a semiconductor wafer, such as a silicon wafer. Alternatively, the substrate 518 can include other elemental semiconductors, such as germanium. The substrate 518 can also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. The substrate 518 can include alloy semiconductors, such as silicon germanium, silicon carbide, gallium arsenic phosphide, or gallium indium phosphide. In the present embodiment, the substrate 518 includes a P-type silicon wafer, which can be regarded as a P-type substrate (PSUB). The well region 516 can be a P-type well region. The body terminal 514 and the source terminal 510 can be separated by a shallow trench isolation (STI) region 502.

[0062] The transistor 500 may include a gate structure disposed on a well region 516 (P-well, PW), and the gate structure may include a gate dielectric 506 and a gate electrode 508 disposed on the gate dielectric 506. The gate dielectric 506 includes a silicon dioxide layer formed by thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition, atomic layer deposition (ALD), or other suitable processes or combinations thereof. Alternatively, the gate dielectric 506 may include a high dielectric constant (high-k) material, silicon oxynitride, other suitable materials, or combinations thereof. The gate dielectric 506 may be, for example, a multilayer of silicon oxide and a high-k material.

[0063] The gate electrode 508 can be designed to be coupled to a metal interconnect and disposed on the gate dielectric 506. The gate electrode 508 may include doped polysilicon (or polysilicon). Alternatively, the gate electrode 508 may include a metal such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof. The gate electrode 508 may be formed by CVD, PVD, plating, and other acceptable processes. The gate electrode 508 may be multi-layered and formed by a multi-step process. In some embodiments, the thickness of the gate dielectric 506 may be designed for applications using a voltage of about 1.8V, which is lower than Figure 4A-4C The HEMTs 400, 420 and 440 shown in FIG. 4 are respectively used with a voltage (eg, 12 V).

[0064] In some embodiments, the body terminal 514 may be a highly doped P-type implant region (e.g., P+), and the source terminal 510 and the drain terminal 512 may be highly doped N-type implant regions, such as N+. In addition, another STI region 504 may be formed next to the drain terminal 512. The configuration of the silicon-based P-type transistor is similar and differs from the N-type transistor 500 in different materials, dopants, etc.

[0065] Figure 6 is a schematic diagram of a driving circuit according to yet another embodiment of the present disclosure.

[0066] Figure 6 The driving circuit 600 shown in FIG. Figure 1, in which the D-HEMT and E-HEMT in the driver circuit 100 are replaced by silicon-based P-type and N-type transistors, respectively. Specifically, the driver circuit 600 includes inverters 610, 620, pre-charge circuits 612, 622, pre-driver circuits 614, 624, and a driver stage 630, which correspond to the inverters 110, 120, pre-charge circuits 112, 122, pre-driver circuits 114, 124, and driver stage 130 in the driver circuit 100. The upper part of the driving circuit 600 includes transistors QinvP1, QinvN1, resistor R1, transistors Q1N, Q2NU, Q2ND, Q3NU, Q3ND, Q7NU, diode D61, capacitor C61, nodes N61, N62, N63, N71, voltages Vinv61, vbs61, vout61, vout62, vout63, SOUT3, which correspond to transistors Qinv1d, Qinv1e, Q1d, Q1e, Q2eU, Q2eD, Q3eU, Q3eD, Q7eU, diode D1, capacitor C1, nodes N1, N2, N3, N4, N5, N11, voltages Vinv1, vbs1, vout1, vout2, vout3, SOUT in the upper part of the driving circuit 100. The lower part of the driving circuit 600 includes transistors QinvP2, QinvN2, resistor R2, transistors Q4N, Q5NU, Q5ND, Q6NU, Q6ND, diode D62, capacitor C62, nodes N66, N67, N68, N69, N70, voltages Vinv62, vbs62, vout64, vout65, vout66, which correspond to the transistors Qinv2d, Qinv2e, Q4d, Q4e, Q5eU, Q5eD, Q6eU, Q6eD, diode D2, capacitor C2, nodes N6, N7, N8, N9, N10, voltages Vinv2, vbs2, vout4, vout5, vout6 of the lower part of the driving circuit 100.

[0067] Figure 6 The configuration of inverters 610 and 620 shown may be similar to Figure 1 The inverter circuits 110 and 120 shown are slightly different. For example, Figure 1 Each D-HEMT (e.g., Qinv1d and Qinv2d) in the illustrated inverters 110 and 120 may have a gate connected to its drain, causing the D-HEMT to be in an on state and act as a resistor. When the inverter is implemented using CMOS transistors, Figure 6 The gates of the P-type transistors (eg, QinvP1 and QinvP2) of the inverters 610 and 620 shown in FIG. 6 can be connected to their respective input signals (eg, S of the inverter 610). INand Vinv1 of inverter 620). In addition, when the D-HEMTs (e.g., Q1d and Q4d) in transistor pairs 1 and 4 in driver circuit 100 are replaced by corresponding resistors R1 and R2. In some embodiments, resistors R1 and R2 may be implemented using respective P-type transistors, each of which may have a gate connected to its source, causing the P-type transistor to be in an on state due to its negative threshold voltage. In some embodiments, resistors R1 and R2 may be implemented using SiCr or TiN in the BEOL stage of the GaN process, but the present disclosure is not limited thereto. Figure 6 The operation of the driver circuit 600 shown in FIG. 6 can be similar to Figure 1 The operation of the driving circuit 100 is shown in FIG. 1 , and thus its details are not repeated here.

[0068] Specifically, in one or more embodiments, the technology of the balanced pre-charging circuit used in the GaN-based driving circuit 100 can also be applied to the silicon-based driving circuit 600 to provide improved and balanced driving capabilities (e.g., for positive and negative input signals S IN ). It should be noted that for descriptive purposes, Figure 6 The power device shown in can be made similar to Figure 1 In this case, in one or more embodiments, the driver circuit 600 can be manufactured in a first die using a silicon-based CMOS process, and the power E-HEMT PQe can be manufactured in a second die using a GaN process. In one or more embodiments, the first die and the second die can be stacked or wire-bonded, for example, one of which is flipped. In some embodiments, Figure 6 The power E-HEMT PQe shown may be replaced with a power FET fabricated on a first die using a silicon-based CMOS process, thus requiring no chip stacking or wire bonding.

[0069] It should be noted that in one or more embodiments, the balanced two-stage pre-charging circuit technology used in the GaN-based driving circuit 200 may also be applied to another silicon-based driving circuit (not explicitly shown) to provide further improved and balanced driving capability.

[0070] Figure 7 is a flow chart of a method 700 for improving the driving capability of a driving circuit according to an embodiment of the present disclosure. Figure 1 and Figure 7 .

[0071] In operation 710, in response to an input signal (eg, S IN) is in a low logic state, and the first precharge voltage is stored by a first capacitor (e.g., C1) in a first precharge circuit (e.g., precharge circuit 112). For example, in response to the input signal being in a low logic state, the E-HEMT Qinv1e is turned off. Since the D-HEMT Qinv1d is turned on, the voltage Vinv1 at the node N1 may be equal to the power supply voltage VDD minus the voltage drop of the D-HEMT Qinv1d, and it is in a high logic state capable of turning on the E-HEMTs Q1e, Q2eD, and Q3eD. Therefore, the voltage vout2 at the node N4 is pulled down to the ground voltage VSS, and the voltage vbs1 at the node N2 may be equal to the power supply voltage VDD (e.g., 6V) minus the threshold voltage (e.g., 0.2V) VD of the diode D1. Therefore, the capacitor C1 may store a voltage (e.g., the first precharge voltage) approximately equal to VDD-VD (e.g., 5.8V) between its two terminals.

[0072] In operation 720, in response to the input signal being in a high logic state, the first pre-charge circuit boosts the first driving voltage (e.g., vout2) of the first pre-driver circuit (e.g., 114) using the stored first pre-charge voltage, and the high-side driver device (e.g., E-HEMT Q7eU) in the driver stage is driven by the first pre-charge circuit using the boosted first driving signal to provide the power device (e.g., PQe) with a first voltage (e.g., SOUT) corresponding to the supply voltage (e.g., VDD). For example, the pre-charge circuit 112 may be responsive to the input signal S IN Switching from a low logic state to a high logic state, the capacitor C1 is used to boost the voltage vout2 at the node N4, so that the E-HEMT Q3eU is fully turned on to provide a voltage substantially equal to the supply voltage VDD to the high-side driver device (e.g., Q7eU). Therefore, the high-side driver device (e.g., Q7eU) can provide a first voltage substantially equal to the supply voltage VDD to the power device (e.g., PQe) with high driving capability during the voltage push-up duration.

[0073] In some embodiments, method 700 also includes operation of the lower portion of driver circuit 100, which may be similar to operation of the upper portion of driver circuit 100, except that the input signal of the lower portion of driver circuit 100 is a voltage Vinv1 at node N1, whose logic state is different from the input signal S INFor example, in response to the input signal being in a high logic state, the second pre-charge voltage is stored by a second capacitor (e.g., C2) in a second pre-charge circuit (e.g., pre-charge circuit 122). In response to the input signal being in a low logic state, a second drive voltage (e.g., vout5) for a second pre-driver circuit (e.g., 124) is boosted by the second pre-charge circuit using the stored second pre-charge voltage, and a low-side driver device (e.g., Q7eD) in a driver stage is driven by a second pre-driver circuit having a boosted second drive voltage to provide a ground voltage (e.g., VSS).

[0074] One aspect of the present invention provides a driving circuit, which includes a driving stage and a first sub-circuit. The driving stage includes a first driving device and a second driving device configured to drive a power device. The first sub-circuit is electrically connected to the driving stage. The first sub-circuit includes a first pre-charging circuit and a first pre-driving circuit. The first pre-driving circuit is electrically connected to the first pre-charging circuit and the first driving device. The first pre-charging circuit is configured to generate a first pre-charging voltage in response to an input signal of the driving circuit having a first signal level. The first pre-charging circuit is also configured to fully turn on the first pre-driving device in the first pre-driving circuit based on the first pre-charging voltage to drive the first driving device in response to the input signal having a second signal level different from the first signal level.

[0075] In some embodiments, the driving circuit also includes: a second sub-circuit, electrically connected to the driving stage, the second sub-circuit includes: a second pre-charging circuit; and a second pre-driving circuit, electrically connected to the second pre-charging circuit and the second driving device, wherein the second pre-charging circuit is configured to: generate a second pre-charging voltage in response to the input signal having a second signal level, and fully turn on the second pre-driving device in the second pre-driving circuit based on the second pre-charging voltage to drive the second driving device in response to the input signal having a first signal level.

[0076] In some embodiments, in response to the input signal having a second signal level, the first pre-charge circuit is configured to boost the first pre-charge voltage to be higher than the supply voltage provided to the driving circuit, and in response to the input signal having the first signal level, the second pre-charge circuit is configured to boost the second pre-charge voltage to be higher than the supply voltage.

[0077] In some embodiments, the first driving device and the second driving device include GaN-based enhancement mode high electron mobility transistors (E-HEMTs).

[0078] In some embodiments, the first driving device and the second driving device include silicon-based enhancement-type N-type transistors.

[0079] In some embodiments, the first sub-circuit also includes a first inverter, which is configured to convert the input signal into a first voltage signal for controlling the first pre-charging circuit, and the second sub-circuit also includes a second inverter, which is configured to convert the first voltage signal into a second voltage signal for controlling the second pre-charging circuit.

[0080] In some embodiments, the first inverter includes: a first enhancement-mode high electron mobility transistor (E-HEMT) having a gate connected to an input signal, a drain connected to a first node, and a source connected to a ground voltage; and a first depletion-mode HEMT (D-HEMT) having a gate connected to the first node, a drain connected to a supply voltage, and a source connected to the first node, and the second inverter includes: a second E-HEMT having a gate connected to the first voltage signal, a drain connected to a second node, and a source connected to the ground voltage; and a second D-HEMT having a gate connected to a second node, a drain connected to the supply voltage, and a source connected to the second node.

[0081] In some embodiments, the first precharge circuit includes: a first diode coupled between a supply voltage and a first node; a first enhancement-mode high electron mobility transistor (E-HEMT) having a gate connected to a first voltage signal, a drain connected to a second node, and a source connected to a ground voltage; a first depletion-mode HEMT (D-HEMT) having a gate connected to the second node, a drain connected to the first node, and a source connected to the second node; a second E-HEMT having a gate connected to the first voltage signal, a drain connected to a third node, and a source connected to the ground voltage; a third E-HEMT having a gate connected to the second node, a drain connected to the supply voltage, and a source connected to a third node; and a first capacitor having a first terminal connected to the first node, and a second terminal connected to the third node.

[0082] In some embodiments, the first pre-driver circuit includes: a fourth E-HEMT having a gate connected to the first voltage signal, a drain connected to a fourth node, and a source connected to a ground voltage; and a fifth E-HEMT having a gate connected to the third node, a drain connected to a supply voltage, and a source connected to a fourth node, and the first driver device includes a gate connected to the fourth node, a drain connected to the supply voltage, and a source connected to an output terminal of the driver circuit.

[0083] In some embodiments, the second precharge circuit includes: a second diode coupled between the supply voltage and the fifth node; a sixth E-HEMT having a gate connected to the second voltage signal, a drain connected to the sixth node, and a source connected to the ground voltage; a second D-HEMT having a gate connected to the sixth node, a drain connected to the fifth node, and a source connected to the sixth node; a seventh E-HEMT having a gate connected to the second voltage signal, a drain connected to the seventh node, and a source connected to the ground voltage; an eighth E-HEMT having a gate connected to the sixth node, a drain connected to the supply voltage, and a source connected to the seventh node; and a second capacitor having a first terminal connected to the fifth node and a second terminal connected to the seventh node.

[0084] In some embodiments, the second pre-driver circuit includes: a ninth E-HEMT having a gate connected to the second voltage signal, a drain connected to an eighth node, and a source connected to a ground voltage; and a tenth E-HEMT having a gate connected to a seventh node, a drain connected to a supply voltage, and a source connected to an eighth node, and the second driver device includes a gate connected to the eighth node, a drain connected to an output terminal of the driver circuit, and a source connected to the ground voltage.

[0085] In some embodiments, the first diode and the second diode include an eleventh E-HEMT and a twelfth E-HEMT, respectively, in a diode-connected configuration.

[0086] In some embodiments, the first capacitor and the second capacitor include metal insulator metal (MIM) or metal oxide metal (MOM) capacitors.

[0087] Another aspect of the present invention provides a multi-stage pre-charge circuit system for a drive circuit. The multi-stage pre-charge circuit system includes a first pre-charge circuit and a second pre-charge circuit. The first pre-charge circuit is configured to generate a first boost drive voltage higher than the supply voltage provided to the multi-stage pre-charge circuit in response to an input signal having a first signal level. The second pre-charge circuit is electrically connected to the first pre-charge circuit and is configured to generate a second boost drive voltage based on the first boost drive voltage in response to an input signal having a first signal level.

[0088] In some embodiments, the multi-stage pre-charging circuit system further includes: a first pre-driver circuit electrically connected to the second pre-charging circuit and configured to drive a first driver device of the driver circuit, wherein the first pre-driver circuit includes a first pre-driver device configured to be fully turned on by a second boosted driver voltage in response to an input signal having a first signal level.

[0089] In some embodiments, the multi-stage pre-charging circuit system also includes: a third pre-charging circuit, configured to generate a third boost driving voltage higher than the supply voltage in response to an input signal having a second signal level different from the first signal level; and a fourth pre-charging circuit, electrically connected to the third pre-charging circuit and configured to generate a fourth boost driving voltage based on the third boost driving voltage in response to an input signal having a second signal level.

[0090] In some embodiments, the multi-stage pre-charging circuit system further includes: a first pre-driver circuit, electrically connected to the second pre-charge circuit and configured to drive a first driver device of the driver circuit, wherein the first pre-driver circuit includes a first pre-driver device, and the first pre-driver device is configured to be a first pre-driver device that is fully turned on by a second boosting driving voltage in response to an input signal having a first signal level; and a second pre-driver circuit, electrically connected to the fourth pre-charge circuit and configured to drive a second driver device of the driver circuit, wherein the second pre-driver circuit includes a second pre-driver device that is configured to be a second pre-driver device that is fully turned on by a fourth boosting driving voltage in response to an input signal having a second signal level.

[0091] In some embodiments, the multi-stage pre-charging circuit system also includes: a first inverter configured to convert the input signal into a first voltage signal for controlling the first pre-charging circuit; and a second inverter configured to convert the first voltage signal into a second voltage signal for controlling the third pre-charging circuit.

[0092] Another aspect of the present disclosure provides a method for operating a drive circuit. The drive circuit includes a first pre-charge circuit, a first pre-driver circuit, and a driver stage. The method includes the following steps. In response to an input signal being in a first logic state: storing a first pre-charge voltage through a first capacitor in the first pre-charge circuit. In response to the input signal being in a second logic state different from the first logic state: boosting a first drive voltage for the first pre-driver circuit using the stored first pre-charge voltage through the first pre-charge circuit, and driving a first driver device in the driver stage with the boosted first drive voltage through the first pre-driver circuit to provide a first voltage corresponding to a supply voltage to the power device.

[0093] In some embodiments, the driving circuit also includes a second pre-charging circuit and a second pre-driving circuit, and the method also includes: in response to the input signal being in a second logic state: storing a second pre-charging voltage through a second capacitor in the second pre-charging circuit; and in response to the input signal being in a first logic state: using the stored second pre-charging voltage to boost a second driving voltage for the second pre-driving circuit through the second pre-charging circuit, and using the boosted second driving voltage by the second pre-driving circuit to drive a second driving device in the driving stage to provide a ground voltage to the power device.

[0094] The methods and features of the present disclosure have been fully described in the examples and descriptions provided. It should be understood that any modifications or changes are intended to be included in the scope of protection of the present disclosure without departing from the spirit of the present disclosure. The various low levels and high levels described herein are examples. Within the scope of various embodiments, one or more of the circuits or signals are modified to include a low level instead of the high level, and vice versa. The described methods include example operations, but they do not necessarily need to be performed in the order shown. According to the spirit and scope of the embodiments of the present disclosure, operations can be appropriately added, replaced, changed in order, and / or eliminated. Embodiments combining different features and / or different embodiments are within the scope of the present disclosure, and will be apparent to those of ordinary skill in the art after reading the present disclosure.

[0095] In addition, the scope of the present application is not intended to be limited to the particular embodiments of the processes, machines, manufactures, and compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will readily understand from this disclosure that, in accordance with this disclosure, processes, machines, manufactures, compositions of matter, means, methods, or steps currently existing or later developed that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein may be utilized.

[0096] Therefore, the appended claims are intended to include within their scope the process, machine, manufacture, composition of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the present disclosure.

Claims

1. A driving circuit, comprising: a driver stage, comprising a first driver device and a second driver device configured to drive the power device; and A first sub-circuit is electrically connected to the driving stage, the first sub-circuit comprising: a first pre-charge circuit; and a first pre-driving circuit electrically connected to the first pre-charging circuit and the first driving device, Wherein, the first pre-charging circuit is configured as: In response to an input signal of the driving circuit having a first signal level, generating a first precharge voltage, and In response to the input signal having a second signal level different from the first signal level, a first pre-driving device in the first pre-driving circuit is fully turned on based on the first pre-charge voltage to drive the first driving device.

2. The driving circuit according to claim 1, further comprising: A second sub-circuit is electrically connected to the driver stage, the second sub-circuit comprising: a second precharge circuit; and a second pre-driving circuit electrically connected to the second pre-charging circuit and the second driving device, Wherein, the second pre-charging circuit is configured as follows: generating a second precharge voltage in response to the input signal having the second signal level, and In response to the input signal having the first signal level, a second pre-driving device in the second pre-driving circuit is fully turned on based on the second pre-charging voltage to drive the second driving device.

3. The driving circuit according to claim 2, wherein: In response to the input signal having a second signal level, the first precharge circuit is configured to boost the first precharge voltage to be higher than a supply voltage provided to the drive circuit, and In response to the input signal having the first signal level, the second precharge circuit is configured to boost the second precharge voltage to be higher than the supply voltage.

4. The driving circuit according to claim 2, wherein: The first sub-circuit further includes a first inverter configured to convert the input signal into a first voltage signal for controlling the first pre-charging circuit, and The second sub-circuit further includes a second inverter configured to convert the first voltage signal into a second voltage signal for controlling the second pre-charging circuit.

5. The driving circuit according to claim 4, wherein: The first inverter comprises: a first E-HEMT having a gate connected to the input signal, a drain connected to the first node, and a source connected to a ground voltage; and a first D-HEMT having a gate connected to the first node, a drain connected to a supply voltage, and a source connected to the first node, and The second inverter comprises: a second E-HEMT having a gate connected to the first voltage signal, a drain connected to the second node, and a source connected to a ground voltage; and The second D-HEMT has a gate connected to the second node, a drain connected to a supply voltage, and a source connected to the second node.

6. The driving circuit according to claim 4, wherein: The first pre-charging circuit comprises: a first diode coupled between a supply voltage and a first node; a first E-HEMT having a gate connected to the first voltage signal, a drain connected to the second node, and a source connected to a ground voltage; a first D-HEMT having a gate connected to the second node, a drain connected to the first node, and a source connected to the second node; a second E-HEMT having a gate connected to the first voltage signal, a drain connected to a third node, and a source connected to a ground voltage; a third E-HEMT having a gate connected to the second node, a drain connected to the supply voltage, and a source connected to the third node; and The first capacitor has a first terminal connected to the first node and a second terminal connected to the third node.

7. The driving circuit according to claim 6, wherein: The first pre-driving circuit comprises: a fourth E-HEMT having a gate connected to the first voltage signal, a drain connected to a fourth node, and a source connected to a ground voltage; and a fifth E-HEMT having a gate connected to the third node, a drain connected to the supply voltage, and a source connected to the fourth node, and The first driving device includes a gate connected to the fourth node, a drain connected to the supply voltage, and a source connected to an output terminal of the driving circuit.

8. The driving circuit according to claim 7, wherein: The second pre-charging circuit comprises: a second diode coupled between the supply voltage and a fifth node; a sixth E-HEMT having a gate connected to the second voltage signal, a drain connected to a sixth node, and a source connected to a ground voltage; a second D-HEMT having a gate connected to the sixth node, a drain connected to the fifth node, and a source connected to the sixth node; a seventh E-HEMT having a gate connected to the second voltage signal, a drain connected to a seventh node, and a source connected to a ground voltage; an eighth E-HEMT having a gate connected to the sixth node, a drain connected to the supply voltage, and a source connected to the seventh node; and A second capacitor has a first terminal connected to the fifth node and a second terminal connected to the seventh node.

9. A multi-stage pre-charging circuit system for a driving circuit, the multi-stage pre-charging circuit system comprising: a first pre-charging circuit configured to generate a first boosted driving voltage higher than a supply voltage provided to the multi-stage pre-charging circuit system in response to an input signal having a first signal level; and The second pre-charging circuit is electrically connected to the first pre-charging circuit and is configured to generate a second boosting driving voltage based on the first boosting driving voltage in response to the input signal having the first signal level.

10. A method of operating a drive circuit, wherein: The driving circuit comprises a first pre-charging circuit, a first pre-driving circuit and a driving stage, and the method comprises: In response to the input signal being in a first logic state: storing a first precharge voltage by a first capacitor in a first precharge circuit; and In response to the input signal being in a second logic state different from the first logic state: boosting a first drive voltage of the first pre-drive circuit using the stored first pre-charge voltage by the first pre-charge circuit, and The first pre-driver circuit drives the first driver device in the driver stage using the boosted first driver voltage to provide the power device with a first voltage corresponding to the supply voltage.

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