Frequency division output method, frequency division output device and storage medium

Abstract

The invention discloses a frequency division output method, a frequency division output device and a storage medium, the frequency division output method is applied to the frequency division output device, the method comprises the following steps: sampling based on a preset sampling frequency to obtain a first pulse signal and a second pulse signal, the phase difference between the first pulse signal and the second pulse signal being a preset phase difference; performing filtering processing on the first pulse signal and the second pulse signal based on a preset filtering coefficient; obtaining a first level signal and a second level signal based on the filtered first pulse signal, the filtered second pulse signal and a preset reference voltage value; determining a counting direction of the count value based on the first level signal and the second level signal; and outputting a first frequency division signal and a second frequency division signal based on the counting direction, a preset period value and a preset comparison value. The frequency division function is achieved through the frequency division output method, namely, the frequency division function is achieved through a software algorithm, the requirement for extra hardware is low, and the system cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of motor technology, and in particular to a frequency division output method, a frequency division output device and a storage medium. Background Art

[0002] In the use of general-purpose inverter products and servo drive products, the orthogonal pulse signals provided by the incremental photoelectric encoder are usually relied on to detect the position or speed of the motor. However, due to the high speed of the motor, the orthogonal pulse signals output by the incremental photoelectric encoder are easily interfered, and the frequency of the output orthogonal pulse signals is high, which makes it difficult to accurately calculate the frequency and number of the orthogonal pulse signals, thereby affecting the actual operating performance of the motor drive.

[0003] Therefore, the inverter or servo drive that drives the motor needs to use an additional position encoder feedback card, also called a PG card, to perform frequency division processing on the output quadrature pulse signal of the incremental photoelectric encoder. Frequency division processing can filter and reduce noise, and reduce the frequency of the output quadrature pulse signal according to the preset frequency division ratio, which is conducive to accurate signal detection.

[0004] The existing frequency division processing method usually uses a complex programmable logic device (CPLD) or a field programmable gate array (FPGA) as the core device of the PG card frequency division function, and uses a microcontroller unit (MCU) or a digital signal processor (DSP) as the core device of the motor drive control. The two core devices communicate information through a serial peripheral interface (SPI) communication mechanism. The existing frequency division processing method requires at least two core devices to form a complete drive system, which has high requirements for hardware configuration, increases system cost, and the communication between the two core devices may cause communication failure or communication loss in harsh environments, reducing the stability, accuracy and reliability of the motor drive. Summary of the invention

[0005] The present application mainly provides a frequency division output method and a frequency division output device, and a storage medium to solve the problem of high system cost.

[0006] The present application provides a frequency division output method, which is applied to a frequency division output device, and the method comprises:

[0007] Sampling based on a preset sampling frequency to obtain a first pulse signal and a second pulse signal, wherein a phase difference between the first pulse signal and the second pulse signal is a preset phase difference;

[0008] Based on a preset filter coefficient, filtering the first pulse signal and the second pulse signal;

[0009] Obtaining a first level signal and a second level signal based on the first pulse signal after filtering, the second pulse signal and a preset reference voltage value;

[0010] determining a counting direction of a count value based on the first level signal and the second level signal;

[0011] A first frequency-divided signal and a second frequency-divided signal are output based on the counting direction, a preset period value, and a preset comparison value.

[0012] In some embodiments, the step of determining the counting direction of the count value based on the first level signal and the second level signal comprises:

[0013] When the first level signal is at a high level and the second level signal changes from a low level to a high level, the first level signal is at a low level and the second level signal changes from a high level to a low level, the second level signal is at a high level and the first level signal changes from a high level to a low level, or the second level signal is at a low level and the first level signal changes from a low level to a high level, determining that the counting direction of the count value is increasing;

[0014] When the first level signal is at a high level and the second level signal changes from a high level to a low level, the first level signal is at a low level and the second level signal changes from a low level to a high level, the second level signal is at a high level and the first level signal changes from a low level to a high level, or the second level signal is at a low level and the first level signal changes from a high level to a low level, it is determined that the counting direction of the count value is decreasing.

[0015] In some embodiments, the step of outputting the first frequency division signal and the second frequency division signal based on the counting direction, the preset period value and the preset comparison value comprises:

[0016] Setting the period value and the comparison value based on a preset frequency division coefficient and / or the counting direction;

[0017] outputting the first frequency-divided signal and the second frequency-divided signal according to the period value;

[0018] When the count value is equal to the comparison value, the output level of the first frequency-divided signal is reversed; when the count value is equal to the period value, the output level of the second frequency-divided signal is reversed.

[0019] In some embodiments, the step of setting the period value based on a preset frequency division coefficient and / or the counting direction includes:

[0020] The period value is set to the frequency division factor multiplied by two and then minus one.

[0021] In some embodiments, the step of setting the comparison value based on a preset frequency division coefficient and / or the counting direction includes:

[0022] When the counting direction is increasing, setting the comparison value to the frequency division coefficient;

[0023] When the counting direction is decreasing, the comparison value is set to the frequency division coefficient minus one.

[0024] In some embodiments, the step of obtaining a first level signal and a second level signal based on the first pulse signal, the second pulse signal and a preset reference voltage value comprises:

[0025] Comparing the first pulse signal with the preset reference voltage value to obtain the first level signal;

[0026] The second pulse signal is compared with the preset reference voltage value to obtain the second level signal.

[0027] In some embodiments, the step of comparing the first pulse signal with the preset reference voltage value to obtain the first level signal includes:

[0028] When the first pulse signal is greater than or equal to the reference voltage value, the first level signal is a high level;

[0029] When the first pulse signal is less than the reference voltage value, the first level signal is at a low level.

[0030] In some embodiments, the step of comparing the second pulse signal with the preset reference voltage value to obtain the second level signal includes:

[0031] When the second pulse signal is greater than or equal to the reference voltage value, the second level signal is a high level;

[0032] When the second pulse signal is less than the reference voltage value, the second level signal is at a low level.

[0033] The present application also provides a frequency division output device, comprising: an encoder and a control unit, the control unit being used to sample a first pulse signal and a second pulse signal of the encoder;

[0034] The control unit includes a first voltage comparator, a second voltage comparator and a counter, the first voltage comparator is used to receive the first pulse signal, and output a first level signal to the counter based on a preset reference voltage value and the first pulse signal; the second voltage comparator is used to receive the second pulse signal, and output a second level signal to the counter based on the preset reference voltage value and the second pulse signal; the counter is used to determine the counting direction of the counting value based on the first level signal and the second level signal, and output a first frequency division signal and a second frequency division signal based on the counting direction, a preset period value and a preset comparison value.

[0035] The present application also provides a computer-readable storage medium, in which program data is stored. When the program data is executed by a processor, it is used to execute the above method.

[0036] The beneficial effects of the present application are as follows: the present application provides a frequency division output method, which is applied to a frequency division output device, and the method includes: sampling based on a preset sampling frequency to obtain a first pulse signal and a second pulse signal; filtering the first pulse signal and the second pulse signal based on a preset filter coefficient; obtaining a first level signal and a second level signal based on the filtered first pulse signal, the second pulse signal and a preset reference voltage value; determining the counting direction of the count value based on the first level signal and the second level signal; outputting the first frequency division signal and the second frequency division signal based on the counting direction, the preset period value and the preset comparison value. The present application realizes the frequency division function through the frequency division output method, that is, the frequency division function is realized through a software algorithm, which has low requirements for additional hardware and reduces system costs; and the frequency division output method is not affected by harsh environments, reduces the problems of communication failure or communication loss, and improves the stability, accuracy and reliability of motor drive. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0038] Figure 1 is a structural example diagram of an embodiment of a frequency division output device provided by the present application;

[0039] Figure 2 It is a flow chart of an embodiment of a frequency division output method provided by the present application;

[0040] Figure 3It is a waveform diagram of the first pulse signal, the second pulse signal, the first frequency division signal and the second frequency division signal when the counting direction is increasing provided by the present application;

[0041] Figure 4 It is a waveform diagram of the first pulse signal, the second pulse signal, the first frequency division signal and the second frequency division signal when the counting direction is decreasing provided by the present application;

[0042] Figure 5 yes Figure 2 FIG. 5 is a flow chart of an embodiment of step S500 in FIG. DETAILED DESCRIPTION

[0043] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0045] In the description of the embodiments of the present application, technical terms such as "first" and "second" are only used to distinguish different objects and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features.

[0046] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0047] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0048] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0049] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0050] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be connected between, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0051] The existing frequency division processing method usually uses a complex programmable logic device (CPLD) or a field programmable gate array (FPGA) as the core device of the PG card frequency division function, and uses a microcontroller unit (MCU) or a digital signal processor (DSP) as the core device of the motor drive control. The two core devices communicate information through a serial peripheral interface (SPI) communication mechanism. The existing frequency division processing method requires at least two core devices to form a complete drive system, which has high requirements for hardware configuration, increases system cost, and the communication between the two core devices may cause communication failure or communication loss in harsh environments, reducing the stability, accuracy and reliability of the motor drive.

[0052] This application provides a frequency division output device, see Figure 1 As shown, Figure 11 is a schematic structural diagram of an embodiment of a frequency division output device provided in the present application. The frequency division output device 1 of the present embodiment includes: an encoder 10 and a control unit 20 .

[0053] The encoder 10 is a device that converts a signal into an electrical signal, including but not limited to a magnetic encoder, a photoelectric encoder, a fiber optic encoder, a linear encoder, and the like.

[0054] Optionally, the encoder 10 is an incremental photoelectric encoder for outputting two orthogonal pulse signals A and B which differ from each other by 90° electrical angle.

[0055] The control unit 20 refers to a device in the frequency division output device 1 that is responsible for receiving input signals, processing information, and generating output signals, including but not limited to MCU, DSP, programmable logic controller, electronic control unit, etc. Optionally, the control unit 20 is an MCU.

[0056] The control unit 20 is used to sample the first pulse signal and the second pulse signal of the encoder 10 .

[0057] Optionally, the first pulse signal is an A-phase quadrature pulse signal output by the encoder 10, and the second pulse signal is a B-phase quadrature pulse signal output by the encoder 10. In other embodiments, the first pulse signal is a B-phase quadrature pulse signal output by the encoder 10, and the second pulse signal is an A-phase quadrature pulse signal output by the encoder 10.

[0058] The control unit 20 includes a first voltage comparator 21, a second voltage comparator 22 and a counter 23. The first voltage comparator 21 is used to receive a first pulse signal, and output a first level signal to the counter 23 based on a preset reference voltage value and the first pulse signal; the second voltage comparator 22 is used to receive a second pulse signal, and output a second level signal to the counter 23 based on a preset reference voltage value and the second pulse signal; the counter 23 is used to determine the counting direction of the counting value based on the first level signal and the second level signal, and output a first frequency division signal and a second frequency division signal based on the counting direction, a preset period value and a preset comparison value.

[0059] A voltage comparator is an electronic circuit whose main function is to compare the sizes of two voltages and output a specific level signal based on the comparison result.

[0060] The counter 23 is an electronic device or a computer program for counting the number of occurrences of an event.

[0061] Optionally, the first voltage comparator 21 is a peripheral integrated in the control unit 20, used to compare the voltage size of the first pulse signal and the preset reference voltage value, and output a digital signal, that is, output a first level signal to the counter 23 based on the preset reference voltage value and the first pulse signal; the second voltage comparator 22 is a peripheral integrated in the control unit 20, used to compare the voltage size of the second pulse signal and the preset reference voltage value, and output a digital signal, that is, output a second level signal to the counter 23 based on the preset reference voltage value and the second pulse signal.

[0062] Optionally, the counter 23 is a peripheral integrated in the control unit 20, including a timer module and a counter module. Among them, the timer module is used to count up or down through an internal clock source, and is often used to generate accurate time delays or measure time intervals; the counter module is used to record the number of external times, such as receiving external pulses; the timer module is implemented by the counter module. For example, the counter 23 is TIMER A, which is a peripheral of the control unit 20.

[0063] The cycle value refers to the maximum value of a timing cycle in the counter 23, that is, the value to which the counter 23 will reset to 0 and restart counting after counting from 0 to the maximum value. The comparison value refers to the value that can generate a comparison match event, such as changing the output level, when the current count value of the counter 23 matches the value during the counting process.

[0064] Optionally, the counting clock of counter 23 selects a universal orthogonal encoded input signal, and counter 23 determines its counting direction by monitoring two level signals, and generates and outputs a first frequency division signal and a second frequency division signal according to the counting direction and a preset period value and a preset comparison value, thereby realizing a frequency division function.

[0065] In this embodiment, the control unit 20 samples the first pulse signal and the second pulse signal of the encoder 10, and the control unit 20 outputs the first frequency division signal and the second frequency division signal through the first voltage comparator 21, the second voltage comparator 22 and the counter 23 to realize the frequency division function. By using the control unit 20 as a core component, both the motor driving function and the frequency division function can be realized; not only the number of core components is optimized and the cost is saved, but also the problem of communication failure or communication loss can be reduced.

[0066] This application provides a frequency division output method, see Figure 2 As shown, Figure 2 1 is a flow chart of an embodiment of a frequency division output method provided by the present application. The frequency division output method of this embodiment is applied to a frequency division output device 1, and the method includes:

[0067] Step S100: Sampling is performed based on a preset sampling frequency to obtain a first pulse signal and a second pulse signal, wherein a phase difference between the first pulse signal and the second pulse signal is a preset phase difference.

[0068] Optionally, the first voltage comparator 21 of the control unit 20 obtains a first pulse signal by sampling based on a preset sampling frequency, and the second voltage comparator 22 obtains a second pulse signal by sampling based on a preset sampling frequency.

[0069] The sampling frequency refers to the number of times samples are collected per unit time when sampling an analog signal in digital signal processing.

[0070] Optionally, the control unit 20 performs software configuration on the first voltage comparator 21 and the second voltage comparator 22, and selects an external clock line inside the control unit 20 as the clock source of the first voltage comparator 21 and the second voltage comparator 22, that is, the first voltage comparator 21 and the second voltage comparator 22 will operate according to the clock frequency of this external clock line.

[0071] Optionally, the preset sampling frequency refers to the clock frequency of the peripheral clock line. For example, the preset sampling frequency includes but is not limited to 25MHZ, 48MHZ, 50MHZ, 100MHZ, etc.

[0072] Optionally, the first pulse signal and the second pulse signal are A and B two-phase orthogonal pulse signals output by the encoder 10, and a preset phase difference between the first pulse signal and the second pulse signal is 90°.

[0073] Step S200: filtering the first pulse signal and the second pulse signal based on a preset filter coefficient.

[0074] The filter coefficient is a specific digital weight used to control the filter function of the voltage comparator. The filter coefficient includes but is not limited to 1, 2, 3, 4, 5, etc.

[0075] Optionally, the first voltage comparator 21 and the second voltage comparator 22 have a filtering function, and the filtering function of the first voltage comparator 21 and the second voltage comparator 22 is enabled by selecting a filtering coefficient according to demand.

[0076] Specifically, the first voltage comparator 21 performs filtering processing on the sampled first pulse signal based on a preset filtering coefficient, and the second voltage comparator 22 performs filtering processing on the sampled second pulse signal based on a preset filtering coefficient.

[0077] Step S300: obtaining a first level signal and a second level signal based on the filtered first pulse signal, the second pulse signal and a preset reference voltage value.

[0078] The reference voltage value is the reference point for comparison by the voltage comparator. The voltage comparator compares the voltage of the input signal with the reference voltage value to determine the output signal.

[0079] Optionally, the preset reference voltage value is provided by a digital-to-analog converter (DAC) inside the control unit 20 .

[0080] In some embodiments, the first pulse signal after filtering is used as input to the first input terminal of the first voltage comparator 21, the preset reference voltage value is used as input to the second input terminal of the first voltage comparator 21, and the output terminal of the first voltage comparator 21 outputs a first level signal; the second pulse signal after filtering is used as input to the first input terminal of the second voltage comparator 22, the preset reference voltage value is used as input to the second input terminal of the second voltage comparator 22, and the output terminal of the second voltage comparator 22 outputs a second level signal.

[0081] Specifically, the first voltage comparator 21 compares the first pulse signal with a preset reference voltage value to obtain a first level signal.

[0082] In some embodiments, when the first pulse signal is greater than or equal to a reference voltage value, the first level signal is a high level; when the first pulse signal is less than the reference voltage value, the first level signal is a low level.

[0083] Specifically, the second voltage comparator 22 compares the second pulse signal with a preset reference voltage value to obtain a second level signal.

[0084] In some embodiments, when the second pulse signal is greater than or equal to the reference voltage value, the second level signal is a high level; when the second pulse signal is less than the reference voltage value, the second level signal is a low level.

[0085] Step S400: determining a counting direction of a counting value based on a first level signal and a second level signal.

[0086] In some embodiments, the first voltage comparator 21 outputs a first level signal to one pin of the quadrature coding input clock of the counter 23, and the second voltage comparator 22 outputs a second level signal to another pin of the quadrature coding input clock of the counter 23. For example, the first level signal is sent to the CLKA pin of the counter 23, and the second level signal is sent to the CLKB pin of the counter 23.

[0087] The count value is the value recorded by the counter 23 at a specific moment, which represents the result accumulated after a certain number of counting events starting from a certain initial value. For example, the initial value is 0.

[0088] The counting direction refers to the trend of the count value change of the counter 23 when the counter 23 performs the counting operation, which determines whether the count value of the counter 23 is incremented (increased) or decremented (decreased).

[0089] In some embodiments, the counting direction of the count value of the counter 23 is determined by the first level signal and the second level signal input by the first voltage comparator 21 and the second voltage comparator 22 .

[0090] In some embodiments, when the first level signal is high and the second level signal changes from low level to high level, the first level signal is low and the second level signal changes from high level to low level, the second level signal is high and the first level signal changes from high level to low level, or the second level signal is low and the first level signal changes from low level to high level, the counting direction of the count value is determined to be increasing.

[0091] In some embodiments, when the first level signal is high and the second level signal changes from high level to low level, the first level signal is low and the second level signal changes from low level to high level, the second level signal is high and the first level signal changes from low level to high level, or the second level signal is low and the first level signal changes from high level to low level, the counting direction of the count value is determined to be decreasing.

[0092] Among them, the transition from high level to low level is called the falling edge, and the transition from low level to high level is called the rising edge; the counting direction of increasing is also called the positive direction, and the counting direction of decreasing is also called the reverse direction.

[0093] Positive direction means that when the phase difference between the first pulse signal and the second pulse signal is 90°, the first pulse signal leads the second pulse signal, that is, the first pulse signal occurs before the second pulse signal. Reverse direction means that when the phase difference between the first pulse signal and the second pulse signal is 90°, the first pulse signal lags behind the second pulse signal, that is, the second pulse signal occurs before the first pulse signal.

[0094] Step S500: outputting a first frequency-divided signal and a second frequency-divided signal based on a counting direction, a preset period value, and a preset comparison value.

[0095] In some embodiments, the counter 23 selects two channels to respectively output the first frequency-divided signal and the second frequency-divided signal. For example, the channel channle1 of the counter 23 outputs the first frequency-divided signal, and the channel channel2 outputs the second frequency-divided signal.

[0096] The first frequency-divided signal refers to a signal output after the first pulse signal is processed by frequency division. The second frequency-divided signal refers to a signal output after the second pulse signal is processed by frequency division.

[0097] For further information, see Figure 5 As shown, Figure 5yes Figure 2 The flowchart of an embodiment of step 500 is shown in FIG. 5 , wherein step S500 includes:

[0098] Step S501: setting a period value and a comparison value based on a preset frequency division coefficient and / or counting direction.

[0099] The frequency division coefficient refers to the proportional relationship between the input signal frequency and the output signal frequency during the frequency division process. Optionally, the frequency division coefficient is selected according to the needs, and the frequency division coefficient includes but is not limited to 1, 2, 4, 8, etc. For example, the frequency division coefficient is 2, also called 2-frequency division, and the input signal frequency is 100KHZ, then the output signal frequency is 50KHZ.

[0100] In some embodiments, the control unit 20 is pre-configured with a frequency division coefficient, and sets the period value and comparison value of the counter 23 according to the frequency division coefficient and / or counting direction, so as to output a first frequency division signal and a second frequency division signal, thereby realizing frequency division processing of the first pulse signal and the second pulse signal.

[0101] Specifically, the step of setting the period value based on the preset frequency division coefficient and / or counting direction includes: setting the period value to the frequency division coefficient multiplied by two and then minus one. For example, when the frequency division coefficient is 2, the period value is 3.

[0102] Specifically, the step of setting the comparison value based on the preset frequency division coefficient and / or counting direction includes: when the counting direction is increasing, setting the comparison value to the frequency division coefficient; when the counting direction is decreasing, setting the comparison value to the frequency division coefficient minus one.

[0103] For example, when the frequency division coefficient is 2 and the counting direction is increasing, the comparison value is 2; when the frequency division coefficient is 2 and the counting direction is decreasing, the comparison value is 1.

[0104] Since the setting of the comparison value is divided into two cases, the two cases are that when the counting direction is increasing, the comparison value is the frequency division coefficient; when the counting direction is decreasing, the comparison value is the frequency division coefficient minus 1. Optionally, the counter 23 adaptively identifies the counting direction of the orthogonal pulse signal, that is, the counter 23 determines the setting value of the comparison value by identifying whether the counting direction is increasing or decreasing.

[0105] Step S502: outputting a first frequency-divided signal and a second frequency-divided signal according to the period value.

[0106] Optionally, the counter 23 sets a period value according to the frequency division coefficient, and uses the period value as the period for outputting the first frequency division signal and the second frequency division signal.

[0107] Specifically, when the count value is equal to the comparison value, the output level of the first frequency-divided signal is reversed; when the count value is equal to the period value, the output level of the second frequency-divided signal is reversed.

[0108] Level flipping refers to changing the level state of a signal from high level to low level, or from low level to high level.

[0109] Specifically, the counter 23 increases or decreases its count value in the increasing or decreasing counting direction. When the count value reaches the comparison value, that is, the count value is equal to the comparison value, the level of the first frequency-divided signal output by the counter 23 is flipped; when the count value reaches the period value, that is, the count value is equal to the period value, the level of the second frequency-divided signal output by the counter 23 is flipped.

[0110] See also Figure 3 As shown, Figure 3 The waveform diagram of the first pulse signal, the second pulse signal, the first frequency division signal and the second frequency division signal provided by the present application when the counting direction is increasing. Among them, since the counting direction is increasing and the frequency division coefficient is 2, the period value is 3 and the comparison value is 2; for example, when the first counting value is equal to the comparison value, the output level of the first frequency division signal changes from a low level to a high level, and the first frequency division signal realizes a level flip, and when the first counting value is equal to the period value, the second frequency division signal changes from a low level to a high level, and the second frequency division signal realizes a level flip.

[0111] See also Figure 4 As shown, Figure 4 The waveform diagram of the first pulse signal, the second pulse signal, the first frequency division signal and the second frequency division signal provided by the present application when the counting direction is decreasing. Among them, since the counting direction is decreasing and the frequency division coefficient is 2, the period value is 3 and the comparison value is 1; for example, when the first counting value is equal to the comparison value, the first frequency division signal changes from a low level to a high level, and the first frequency division signal achieves a level flip. When the first counting value is equal to the period value, the second frequency division signal changes from a low level to a high level, and the first frequency division signal achieves a level flip.

[0112] The frequency division output method of this embodiment utilizes the first voltage comparator 21, the second voltage comparator 22 and the counter 23 of the control unit 20 to automatically identify the orthogonal pulse signal. The control unit 20 can automatically achieve the correct frequency division frequency of the orthogonal pulse signal based on the relationship between the preset frequency division coefficient and the period value and comparison value of the counter 23, and can maintain the correct phase sequence of the orthogonal pulse signal after frequency division.

[0113] Another embodiment of the present application further provides a computer-readable storage medium, in which program data is stored. When the program data is executed by a processor, it is used to execute the frequency division output method of the above embodiment, which will not be described in detail here.

[0114] In summary, the present application provides a frequency division output method, which is applied to a frequency division output device 1, and the method includes: sampling based on a preset sampling frequency to obtain a first pulse signal and a second pulse signal; filtering the first pulse signal and the second pulse signal based on a preset filter coefficient; obtaining a first level signal and a second level signal based on the filtered first pulse signal, the second pulse signal and a preset reference voltage value; determining the counting direction of the count value based on the first level signal and the second level signal; outputting the first frequency division signal and the second frequency division signal based on the counting direction, the preset period value and the preset comparison value. The present application implements the frequency division function through the frequency division output method, that is, the frequency division function is implemented through a software algorithm, which has low requirements for additional hardware and reduces system costs; and the frequency division output method is not affected by harsh environments, reduces the problems of communication failure or communication loss, and improves the stability, accuracy and reliability of motor drive.

[0115] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A frequency division output method, characterized in that: Applied to a frequency division output device, the method comprises: Sampling based on a preset sampling frequency to obtain a first pulse signal and a second pulse signal, wherein a phase difference between the first pulse signal and the second pulse signal is a preset phase difference; Based on a preset filter coefficient, filtering the first pulse signal and the second pulse signal; Obtaining a first level signal and a second level signal based on the first pulse signal after filtering, the second pulse signal and a preset reference voltage value; determining a counting direction of a count value based on the first level signal and the second level signal; A first frequency-divided signal and a second frequency-divided signal are output based on the counting direction, a preset period value, and a preset comparison value.

2. The frequency division output method according to claim 1, characterized in that: The step of determining the counting direction of the count value based on the first level signal and the second level signal comprises: When the first level signal is at a high level and the second level signal changes from a low level to a high level, the first level signal is at a low level and the second level signal changes from a high level to a low level, the second level signal is at a high level and the first level signal changes from a high level to a low level, or the second level signal is at a low level and the first level signal changes from a low level to a high level, determining that the counting direction of the count value is increasing; When the first level signal is at a high level and the second level signal changes from a high level to a low level, the first level signal is at a low level and the second level signal changes from a low level to a high level, the second level signal is at a high level and the first level signal changes from a low level to a high level, or the second level signal is at a low level and the first level signal changes from a high level to a low level, it is determined that the counting direction of the count value is decreasing.

3. The frequency division output method according to claim 2, characterized in that: The step of outputting a first frequency division signal and a second frequency division signal based on the counting direction, a preset period value and a preset comparison value comprises: Setting the period value and the comparison value based on a preset frequency division coefficient and / or the counting direction; outputting the first frequency-divided signal and the second frequency-divided signal according to the period value; When the count value is equal to the comparison value, the output level of the first frequency-divided signal is reversed; when the count value is equal to the period value, the output level of the second frequency-divided signal is reversed.

4. The frequency division output method according to claim 3, characterized in that: The step of setting the period value based on a preset frequency division coefficient and / or the counting direction comprises: The period value is set to the frequency division factor multiplied by two and then minus one.

5. The frequency division output method according to claim 3, characterized in that: The step of setting the comparison value based on the preset frequency division coefficient and / or the counting direction comprises: When the counting direction is increasing, setting the comparison value to the frequency division coefficient; When the counting direction is decreasing, the comparison value is set to the frequency division coefficient minus one.

6. The frequency division output method according to claim 1, characterized in that: The step of obtaining a first level signal and a second level signal based on the filtered first pulse signal, the second pulse signal and a preset reference voltage value comprises: Comparing the first pulse signal with the preset reference voltage value to obtain the first level signal; The second pulse signal is compared with the preset reference voltage value to obtain the second level signal.

7. The frequency division output method according to claim 6, characterized in that: The step of comparing the first pulse signal with the preset reference voltage value to obtain the first level signal comprises: When the first pulse signal is greater than or equal to the reference voltage value, the first level signal is a high level; When the first pulse signal is less than the reference voltage value, the first level signal is at a low level.

8. The frequency division output method according to claim 6, characterized in that: The step of comparing the second pulse signal with the preset reference voltage value to obtain the second level signal comprises: When the second pulse signal is greater than or equal to the reference voltage value, the second level signal is a high level; When the second pulse signal is less than the reference voltage value, the second level signal is at a low level.

9. A frequency division output device, characterized in that: include: An encoder and a control unit, wherein the control unit is used to sample a first pulse signal and a second pulse signal of the encoder; The control unit includes a first voltage comparator, a second voltage comparator and a counter, wherein the first voltage comparator is used to receive the first pulse signal and output a first level signal to the counter based on a preset reference voltage value and the first pulse signal; The second voltage comparator is used to receive the second pulse signal, and output a second level signal to the counter based on the preset reference voltage value and the second pulse signal; The counter is used to determine a counting direction of a count value based on the first level signal and the second level signal, and output a first frequency division signal and a second frequency division signal based on the counting direction, a preset period value and a preset comparison value.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program data, and when the program data is executed by a processor, it is used to execute the method according to any one of claims 1 to 8.

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