Time skew suppression sampling circuit of time domain interleaving analog-to-digital converter

Abstract

The invention discloses a time skew suppression sampling circuit of a time domain interleaved analog-to-digital converter. The time skew suppression sampling circuit comprises a clock generation circuit and a plurality of sub-channel ADC circuits, each of the plurality of sub-channel ADC circuits comprises a clock control sampling switch circuit and a sub-channel ADC analog-to-digital converter; the input end of the clock control sampling switch circuit inputs a Vin signal, and the output end of the clock control sampling switch circuit is electrically connected with the input end of the sub-channel ADC analog-to-digital converter; the output end of the clock generation circuit is electrically connected with the clock end of the clock control sampling switch circuit and provides a clock signal for the clock control sampling switch circuit; the clock control sampling switch circuit is controlled through a time sequence of a clock signal, and when sampling is finished, the plurality of sub-channel ADC analog-to-digital converters uniformly adopt global clock control to finish sampling; the problem of stray caused by sampling clock time sequence deflection is solved, the sampling precision of a TI-ADC system is improved, the design difficulty is reduced, and the chip area power consumption is saved.

Description

Technical Field

[0001] The invention relates to the technical field of digital integrated circuits, and in particular to a time skew suppression sampling circuit of a time-domain interleaved analog-to-digital converter. Background Art

[0002] The time-interleaved analog-to-digital converter (TI-ADC) consists of multiple parallel sub-channel ADCs, which are sampled in sequence under the control of the sampling clock. The mismatch in sampling time intervals caused by the inconsistent sampling clock routing lengths or path interference of each sub-channel ADC and the mismatch between the channel devices is called time skew error. This error will affect the sampling accuracy of the entire TI-ADC, which is specifically manifested as spurious related to the input signal frequency in the output spectrum of the TI-ADC.

[0003] The traditional solution to the spurious problem caused by time skew error is to calibrate the time skew error; Figure 4 As shown in the figure, the time error between the ADCs of each channel is detected, and the second step is to compensate for the error in some way; however, the detection method of time skew error is relatively complicated, and often requires the introduction of additional calibration circuits for assistance, which increases the chip area and increases the design difficulty of TI-ADC. In addition, the compensation circuit of the time error may introduce additional design problems and consume a lot of power. Figure 5 As shown, an ultra-high-speed track-and-hold amplifier (THA) is used to sample and hold the input analog signal, and then the held signal is distributed to each sub-channel for sampling; in order to achieve high bandwidth and high linearity within the entire sampling bandwidth, huge power consumption is inevitably consumed. Usually, THA uses a higher power supply voltage to ensure sufficient linearity, and its output common mode is also higher; and the sub-ADC generally uses a lower power supply voltage to achieve high-efficiency conversion. Therefore, the signal swing output by the THA generally cannot fully utilize the dynamic range of the sub-ADC, which puts higher requirements on the noise performance of the sub-ADC. Summary of the invention

[0004] Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention provides a time skew suppression sampling circuit for a time-domain interleaved analog-to-digital converter, which fundamentally solves the spurious problem caused by the timing skew of the sampling clock by uniformly controlling the sampling end time of the interleaved channels with a global clock; thereby achieving the effect of improving the sampling accuracy of the TI-ADC system, reducing the design difficulty and saving chip area and power consumption.

[0005] Technical solution: To achieve the above-mentioned purpose, a time skew suppression sampling circuit of a time-domain interleaved analog-to-digital converter of the present invention includes a clock generating circuit and a plurality of sub-channel ADC circuits; the plurality of sub-channel ADC circuits each include a clock-controlled sampling switch circuit and a sub-channel ADC analog-to-digital converter; the input end of the clock-controlled sampling switch circuit inputs a Vin signal, and the output end of the clock-controlled sampling switch circuit is electrically connected to the input end of the sub-channel ADC analog-to-digital converter; the output end of the clock generating circuit is electrically connected to the clock end of the clock-controlled sampling switch circuit to provide a clock signal for the clock-controlled sampling switch circuit; the clock-controlled sampling switch circuit is controlled by the timing of the clock signal, and at the end of sampling, the plurality of sub-channel ADC analog-to-digital converters uniformly adopt a global clock control to end sampling.

[0006] Furthermore, the clock-controlled sampling switch circuit includes an MN9 transistor, an MN7 transistor, an MP6 transistor, an MN10 transistor and an MN11 transistor; the gate of the MN9 transistor is electrically connected to the drain of the MP6 transistor and the drain of the MN10 transistor, and the source of the MN10 transistor is electrically connected to the drain of the MN11 transistor; the drain of the MN9 transistor is electrically connected to the drain of the MN7 transistor, the drain of the MN9 transistor inputs the Vin signal, and the source of the MN9 transistor serves as the output end of the clock-controlled sampling switch circuit; the gate of the MN10 transistor inputs the CLK_SEL[1] clock signal; the MN9 transistor is controlled to be turned on and off by turning on and off the MN7 transistor, the MP6 transistor, the MN10 transistor and the MN11 transistor.

[0007] Furthermore, the clock-controlled sampling switch circuit also includes an MP4 transistor, an MN4 transistor and a Cb bootstrap capacitor; the drain of the MP4 transistor is electrically connected to one plate of the Cb bootstrap capacitor and the substrate of the MP4 transistor, and the drain of the MN4 transistor is electrically connected to the other plate of the Cb bootstrap capacitor; the gate of the MP4 transistor inputs a VG voltage, the drain of the MP4 transistor is electrically connected to the source of the MP6 transistor, and the source of the MP6 transistor is electrically connected to the substrate of the MP6 transistor; the drain of the MN4 transistor is electrically connected to the source of the MN7 transistor.

[0008] Furthermore, the clock-controlled sampling switch circuit also includes an MP7 transistor, an MP8 transistor, an MN8 transistor, an MN5 transistor, an MN6 transistor and an MP6 transistor; the source of the MP7 transistor is electrically connected to the drain of the MP4 transistor, and the drain of the MP7 transistor is electrically connected to the source of the MP8 transistor; the drain of the MP8 transistor is electrically connected to the drain of the MN8 transistor, and the source of the MN8 transistor is electrically connected to the drain of the MN4 transistor; the gate of the MP7 transistor inputs the CLK_TRACK[1] clock signal, and the gate of the MN8 transistor inputs the CLK_GLB clock signal; the drain of the MP8 transistor and the drain of the MN8 transistor are electrically connected to the gate of the MP6 transistor, and the VP voltage is output to the gate of the MP6 transistor.

[0009] Furthermore, the drain of the MN5 transistor is electrically connected to the source of the MN6 transistor, the drain of the MN6 transistor is electrically connected to the drain of the MP5 transistor, the source of the MP5 transistor is electrically connected to the drain of the MP4 transistor and the substrate of the MP5 transistor, and the gate of the MP5 transistor inputs the VP voltage; the drain of the MN6 transistor and the drain of the MP5 transistor are electrically connected to the gate of the MN7 transistor, and output the VN voltage to the gate of the MN7 transistor.

[0010] Furthermore, the clock-controlled sampling switch circuit includes a first group of MOS tube circuits, a second group of MOS tube circuits and a third group of MOS tube circuits; the input end of the first group of MOS tube circuits inputs the CLK_GLB clock signal, and the output end outputs the inverted CLK_GLBB clock signal, and the output end of the first group of MOS tube circuits is electrically connected to the gate of the MN11 transistor; the input end of the second group of MOS tube circuits inputs the CLK_SEL[1] clock signal, and the output end outputs the inverted CLK_SELB[1] clock signal, and the output end of the second group of MOS tube circuits is electrically connected to the gate of the MP8 transistor; the input end of the third group of MOS tube circuits inputs the CLK_TRACK[1] clock signal, and the output end outputs the inverted CLK_TRACKB[1] clock signal, and the output end of the third group of MOS tube circuits is electrically connected to the gate of the MN4 transistor and the gate of the MN5 transistor.

[0011] Furthermore, the first group of MOS tube circuits includes MP1 transistors and MN1 transistors; the second group of MOS tube circuits includes MP2 transistors and MN2 transistors; the third group of MOS tube circuits includes MP3 transistors and MN4 transistors; the drain of the MP1 transistor is electrically connected to the drain of the MN1 transistor, the drain of the MP2 transistor is electrically connected to the drain of the MN2 transistor, and the drain of the MP3 transistor is electrically connected to the drain of the MN3 transistor.

[0012] Furthermore, the clock-controlled sampling switch circuit includes four stages: a bootstrap switch reset stage, an input signal tracking stage, a global clock gating enable stage, and a global clock-controlled sampling shutdown stage. When the clock-controlled sampling switch circuit is in the bootstrap switch reset stage, the CLK_GLB clock signal, the CLK_SEL[1] clock signal, and the CLK_TRACK[1] clock signal are all low levels. When the clock-controlled sampling switch circuit is in the input signal tracking stage, the CLK_GLB clock signal and the CLK_SEL[1] clock signal are all low levels, and the CLK_TRACK[1] clock signal is high level. When the clock-controlled sampling switch circuit is in the global clock gating enable stage, the CLK_GLB clock signal, the CLK_SEL[1] clock signal, and the CLK_TRACK[1] clock signal are all high levels. When the clock-controlled sampling switch circuit is in the global clock-controlled sampling shutdown stage, the CLK_GLB clock signal is low level, and the CLK_SEL[1] clock signal and the CLK_TRACK[1] clock signal are all high levels.

[0013] Beneficial effects: The time skew suppression sampling circuit of a time-domain interleaved analog-to-digital converter of the present invention adopts a clock-controlled sampling switch circuit to perform special timing control on the sampling switch, thereby improving the sampling accuracy of the TI-ADC system, reducing the design difficulty and saving chip area and power consumption; no additional dedicated signal generating circuit is required, and the implementation method is relatively simple, which not only reduces the complexity of the design but also saves the chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A circuit diagram of a time-domain interleaved analog-to-digital converter for sampling with time skew suppression;

[0015] Figure 2 It is the circuit diagram of the clock-controlled sampling switch;

[0016] Figure 3 This is the global clock control timing diagram;

[0017] Figure 4 This is a diagram of the traditional time skew error calibration structure;

[0018] Figure 5 Figure 2 is a diagram of the non-calibrated TI-ADC architecture with THA. DETAILED DESCRIPTION

[0019] The present invention will be further described below in conjunction with the accompanying drawings.

[0020] like Figure 1As shown, a time skew suppression sampling circuit of a time-domain interleaved analog-to-digital converter includes a clock generating circuit 2 and a plurality of sub-channel ADC circuits; the plurality of sub-channel ADC circuits each include a clock-controlled sampling switch circuit 1 and a sub-channel ADC analog-to-digital converter 3; the input end of the clock-controlled sampling switch circuit 1 inputs a Vin signal, and the output end of the clock-controlled sampling switch circuit 1 is electrically connected to the input end of the sub-channel ADC analog-to-digital converter 3; the output end of the clock generating circuit 2 is electrically connected to the clock end of the clock-controlled sampling switch circuit 1 to provide a clock signal for the clock-controlled sampling switch circuit 1; the clock-controlled sampling switch circuit 1 controls the timing of the clock signal, and at the end of sampling, the plurality of sub-channel ADC analog-to-digital converters 3 uniformly use a global clock control to end sampling. The output ends of the plurality of sub-channel ADC analog-to-digital converters 3 are electrically connected to the input end of the MUX multiplexer, and the output end of the MUX multiplexer serves as the output end of the time-domain interleaved analog-to-digital converter.

[0021] Several sub-channel ADC analog-to-digital converters 3 are analog-to-digital converters as sub-channels in the time-domain interleaved analog-to-digital converter, and several analog-to-digital converters are connected in parallel. The clock generation circuit 2 provides clock signals for several clock-controlled sampling switch circuits 1; when several sub-channel ADCs are sampling, the clock generation circuit 2 outputs the corresponding clock signal to control the corresponding clock-controlled sampling switch circuit 1 to input the input signal Vin signal into the corresponding sub-channel ADC; when the sampling is ended, the clock generation circuit 2 outputs the clock signal to control the several clock-controlled sampling switch circuits 1 to all be closed, that is, the sampling is ended by using a unified sampling signal.

[0022] like Figure 2 As shown, the clock-controlled sampling switch circuit 1 includes a MN9 transistor 11, a MN7 transistor 12, a MP6 transistor 13, a MN10 transistor 14 and a MN11 transistor 15; the gate of the MN9 transistor 11 is electrically connected to the drain of the MP6 transistor 13 and the drain of the MN10 transistor 14, and the source of the MN10 transistor 14 is electrically connected to the drain of the MN11 transistor 15; the drain of the MN9 transistor 11 is electrically connected to the drain of the MN7 transistor 12, the drain of the MN9 transistor 11 inputs the Vin signal, and the source of the MN9 transistor 11 serves as the output end of the clock-controlled sampling switch circuit 1; the gate of the MN10 transistor 14 inputs the CLK_SEL[1] clock signal, and the source of the MN11 transistor 15 is grounded; the MN7 transistor 12, the MP6 transistor 13, the MN10 transistor 14 and the MN11 transistor 15 are turned on and off to control the turning on and off of the MN9 transistor.

[0023] like Figure 2As shown, the MN9 transistor 11 is a switch for sampling input signals, and the gate voltage VG of the MN9 transistor 11 is a switch control signal. When the MP6 transistor 13 is turned on, the VG voltage is connected to the upper plate of the Cb bootstrap capacitor 18; when the MN7 transistor 12 is turned on, the drain of the MN9 transistor 11 is connected to the lower plate of the Cb bootstrap capacitor 18; at this time, the MN9 transistor 11 is turned on at a constant gate and drain voltage VDD+VIN, and the CDAC terminal tracks the input signal Vin signal. When the sampling ends, the MN7 transistor 12 and the MP6 transistor 13 are turned off, the MN10 transistor 14 and the MN11 transistor 15 are turned on, and the VG voltage is short-circuited to GND, so that the MN9 transistor is turned off, and the sampled signal is kept on the CDAC; the CDAC terminal is the input terminal of several sub-channel ADCs.

[0024] like Figure 2 As shown, the clock-controlled sampling switch circuit 1 further includes an MP4 transistor 16, an MN4 transistor 17 and a Cb bootstrap capacitor 18; the drain of the MP4 transistor 16 is electrically connected to one plate of the Cb bootstrap capacitor 18 and the substrate of the MP4 transistor 16, and the drain of the MN4 transistor 17 is electrically connected to the other plate of the Cb bootstrap capacitor 18; the gate of the MP4 transistor 16 inputs a VG voltage, the drain of the MP4 transistor 16 is electrically connected to the source of the MP6 transistor 13, and the source of the MP6 transistor 13 is electrically connected to the substrate of the MP6 transistor 13; the drain of the MN4 transistor 17 is electrically connected to the source of the MN7 transistor 12. The source of the MP4 transistor 16 is electrically connected to the VDD power supply, and the source of the MN4 transistor 17 is grounded.

[0025] like Figure 2 As shown, the clock-controlled sampling switch circuit 1 further includes an MP7 transistor 24, an MP8 transistor 25, an MN8 transistor 26, an MN5 transistor 21, an MN6 transistor 22 and an MP6 transistor 23; the source of the MP7 transistor 24 is electrically connected to the drain of the MP4 transistor 16, and the drain of the MP7 transistor 24 is electrically connected to the source of the MP8 transistor 25; the drain of the MP8 transistor 25 is electrically connected to the drain of the MN8 transistor 26, and the source of the MN8 transistor 26 is electrically connected to the drain of the MN4 transistor 17; the gate of the MP7 transistor 24 inputs the CLK_TRACK[1] clock signal, and the gate of the MN8 transistor 24 inputs the CLK_GLB clock signal; the drain of the MP8 transistor 25 and the drain of the MN8 transistor 26 are electrically connected to the gate of the MP6 transistor 13, and output the VP voltage to the gate of the MP6 transistor 13, and the gate of the MP6 transistor 13 is turned on and off according to the magnitude of the VP voltage.

[0026] like Figure 2As shown, the drain of the MN5 transistor 21 is electrically connected to the source of the MN6 transistor 22, the drain of the MN6 transistor 22 is electrically connected to the drain of the MP5 transistor 23, the source of the MP5 transistor 23 is electrically connected to the drain of the MP4 transistor 16 and the substrate of the MP5 transistor 23, the gate of the MP5 transistor 23 inputs the VP voltage, and the source of the MN5 transistor 23 is grounded; the drain of the MN6 transistor 22 and the drain of the MP5 transistor 23 are electrically connected to the gate of the MN7 transistor 12, and the VN voltage is output to the gate of the MN7 transistor 12, and the gate of the MN7 transistor 12 is turned on and off according to the size of the VN voltage.

[0027] like Figure 2 As shown, the clock-controlled sampling switch circuit 1 includes a first group of MOS tube circuits, a second group of MOS tube circuits and a third group of MOS tube circuits; the first group of MOS tube circuits, the second group of MOS tube circuits and the third group of MOS tube circuits are connected in parallel; the input end of the first group of MOS tube circuits inputs the CLK_GLB clock signal, and the output end outputs the inverted CLK_GLBB clock signal, the output end of the first group of MOS tube circuits is electrically connected to the gate of the MN11 transistor 15, and the CLK_GLBB clock signal controls the conduction and shutdown of the MN11 transistor 15; the input end of the second group of MOS tube circuits inputs the CLK_SEL[1] ... The output end outputs an inverted CLK_SELB[1] clock signal, the output end of the second group of MOS tube circuits is electrically connected to the gate of the MP8 transistor 15, and the CLK_SELB[1] clock signal controls the on and off of the MP8 transistor 15; the input end of the third group of MOS tube circuits inputs the CLK_TRACK[1] clock signal, and the output end outputs an inverted CLK_TRACKB[1] clock signal, the output end of the third group of MOS tube circuits is electrically connected to the gate of the MN4 transistor 17 and the gate of the MN5 transistor 21, and the CLK_TRACKB[1] clock signal controls the on and off of the MN4 transistor 17 and the MN5 transistor 21.

[0028] like Figure 2As shown, the first group of MOS transistor circuits includes MP1 transistor 31 and MN1 transistor 34; the second group of MOS transistor circuits includes MP2 transistor 32 and MN2 transistor 35; the third group of MOS transistor circuits includes MP3 transistor 33 and MN4 transistor 36; the gates of the MP1 transistor 31 and MN1 transistor 34 serve as the input end of the first group of MOS transistor circuits, and the gates of the MP1 transistor 31 and MN1 transistor 34 input the CLK_GLB clock signal; the drain of the MP1 transistor 31 is electrically connected to the drain of the MN1 transistor 34, and the drains of the MP1 transistor 31 and MN1 transistor 34 serve as the output end of the first group of MOS transistor circuits. The gates of the MP2 transistor 32 and MN2 transistor 35 serve as the input end of the second group of MOS transistor circuits, and the gates of the MP2 transistor 32 and MN2 transistor 35 input the CLK_SEL[1] clock signal; the drain of the MP2 transistor 32 is electrically connected to the drain of the MN2 transistor 35, and the drains of the MP2 transistor 32 and MN2 transistor 35 serve as the output end of the second group of MOS transistor circuits. The gates of the MP3 transistor 33 and the MN3 transistor 36 serve as the input terminals of the third group of MOS transistor circuits, and the gates of the MP3 transistor 33 and the MN3 transistor 36 input the CLK_TRACK[1] clock signal; the drain of the MP3 transistor 33 is electrically connected to the drain of the MN3 transistor 36, and the drains of the MP3 transistor 33 and the MN3 transistor 36 serve as the output terminals of the third group of MOS transistor circuits. The sources of the MP1 transistor 31, the MP2 transistor 32, and the MP3 transistor 33 are all electrically connected to the VDD power supply, and the sources of the MN1 transistor 34, the MN2 transistor 35, and the MN4 transistor 36 are all grounded.

[0029] like Figure 3 As shown, the clock-controlled sampling switch circuit 1 includes four stages: a bootstrap switch reset stage, an input signal tracking stage, a global clock gating enable stage, and a global clock-controlled sampling shutdown stage; when the clock-controlled sampling switch circuit 1 is in the bootstrap switch reset stage, the CLK_GLB clock signal, the CLK_SEL[1] clock signal, and the CLK_TRACK[1] clock signal are all at a low level; the MP4 transistor 16 and the MN4 transistor 17 are both turned on, and the voltage across the Cb bootstrap capacitor 18 is charged to VDD, that is, the voltage of the Cb bootstrap capacitor 18 is charged to VDD.

[0030] When the clock-controlled sampling switch circuit 1 is in the input signal tracking stage, the CLK_GLB clock signal and the CLK_SEL[1] clock signal are both at low levels, and the CLK_TRACK[1] clock signal is at a high level; the MP6 transistor 13, the MN7 transistor 12, and the MN8 transistor 26 are turned on, and the two plates of the Cb bootstrap capacitor 18 are respectively connected to the gate and drain of the MN9 transistor 11, the upper plate of the Cb bootstrap capacitor 18 is electrically connected to the gate of the MN9 transistor 11, and the lower plate of the Cb bootstrap capacitor 18 is electrically connected to the drain of the MN9 transistor 11, and the VG voltage is input to the gate of the MN9 transistor 11; the MN9 transistor 11 is turned on, so that the Vin signal is input to the input ends of several sub-channel ADCs.

[0031] When the clock-controlled sampling switch circuit 1 is in the global clock gating enable stage, the CLK_GLB clock signal, the CLK_SEL[1] clock signal and the CLK_TRACK[1] clock signal are all high level; the VG voltage of the gate of the input MN9 transistor 11 remains unchanged, the switch MN9 transistor 11 remains turned on, and the MN10 transistor 14 and the MP8 transistor 25 are turned on, preparing for the next shutdown state.

[0032] When the clock control sampling switch circuit 1 is in the global clock control sampling shutdown stage, the CLK_GLB clock signal is changed from high level to low level, the CLK_GLB clock signal is low level, and the CLK_SEL[1] clock signal and the CLK_TRACK[1] clock signal are both high level; the control switch MN11 transistor 15 is turned on, the VG voltage is short-circuited to the ground GND, and at the same time, the MP6 transistor 13 is turned on when the switch MP6 transistor 24 and the MP8 transistor 25 are turned on, resulting in the MP6 transistor 13 gate and source being short-circuited, so that the switch MP6 transistor 13 is turned off; and because the VG voltage is short-circuited to GND, the switch MN9 transistor 11 is turned off, thereby causing the time domain interleaved analog-to-digital converter to end sampling. The clock generation circuit 2 outputs the CLK_TRACK[1] clock signal, the CLK_SEL[1] clock signal and the CLK_GLB clock signal.

[0033] The clock generating circuit 2 outputs CLK_TRACK[1], CLK_TRACK[2], ..., CLK_TRACK[N], and respectively inputs them into the clock-controlled sampling switch circuits corresponding to the sub-channel ADC1, sub-channel ADC2, ..., and sub-channel ADCN in the sub-channel ADC analog-to-digital converter 3, so as to start the sampling of each corresponding sub-channel ADC. The clock generating circuit 2 outputs CLK_SEL[1], CLK_SEL[2], ..., CLK_SEL[N], and respectively inputs them into the clock-controlled sampling switch circuits corresponding to the sub-channel ADC1, sub-channel ADC2, ..., and sub-channel ADCN in the sub-channel ADC analog-to-digital converter 3. The clock generating circuit 2 outputs the CLK_GLB clock signal to the clock-controlled sampling switch circuits corresponding to the sub-channel ADC analog-to-digital converters 3 in the sub-channel ADC circuits, and uses the same CLK_GLB clock signal to control the sub-channel ADC analog-to-digital converters 3 to uniformly end the sampling.

[0034] Through the bootstrap switch reset stage, input signal tracking stage, global clock gating enable stage and global clock controlled sampling shutdown stage, sampling is started under the control of the CLK_TRACK[1] clock signal and ended under the control of the CLK_GLB clock signal; therefore, in the multi-channel TI-ADC, the switch of each sub-channel in the time-domain interleaved analog-to-digital converter is controlled by the same high-speed clock CLK_GLB clock signal to control the sampling shutdown, which can unify the error source of the sampling clock to the same position, thereby suppressing the time skew error caused by different clock delays.

[0035] The above is only a description of the preferred embodiments of the present invention. Ordinary technicians in this technical field can make several modifications and optimizations based on the above disclosure without departing from the above basic principles. These improvements and optimizations should be regarded as the understood protection scope of the present invention.

Claims

1. A time skew suppression sampling circuit for a time-domain interleaved analog-to-digital converter, characterized in that: The invention comprises a clock generating circuit (2) and a plurality of sub-channel ADC circuits; the plurality of sub-channel ADC circuits each comprise a clock-controlled sampling switch circuit (1) and a sub-channel ADC analog-to-digital converter (3); a Vin signal is input to an input end of the clock-controlled sampling switch circuit (1), and an output end of the clock-controlled sampling switch circuit (1) is electrically connected to an input end of the sub-channel ADC analog-to-digital converter (3); an output end of the clock generating circuit (2) is electrically connected to a clock end of the clock-controlled sampling switch circuit (1) to provide a clock signal for the clock-controlled sampling switch circuit (1); the clock-controlled sampling switch circuit (1) is controlled by the timing of the clock signal, and when sampling is finished, the plurality of sub-channel ADC analog-to-digital converters (3) uniformly use a global clock control to finish sampling.

2. The time skew suppression sampling circuit of a time-domain interleaved analog-to-digital converter according to claim 1, characterized in that: The clock-controlled sampling switch circuit (1) comprises a MN9 transistor (11), a MN7 transistor (12), a MP6 transistor (13), a MN10 transistor (14) and a MN11 transistor (15); the gate of the MN9 transistor (11) is electrically connected to the drain of the MP6 transistor (13) and the drain of the MN10 transistor (14), and the source of the MN10 transistor (14) is electrically connected to the drain of the MN11 transistor (15); the drain of the MN9 transistor (11) is electrically connected to the drain of the MN7 transistor (12), the drain of the MN9 transistor (11) inputs a Vin signal, and the source of the MN9 transistor (11) serves as the output end of the clock-controlled sampling switch circuit (1); the gate of the MN10 transistor (14) inputs a CLK_SEL[1] clock signal; the MN7 transistor (12), the MP6 transistor (13), the MN10 transistor (14) and the MN11 transistor (15) are turned on and off to control the turning on and off of the MN9 transistor.

3. The time skew suppression sampling circuit of a time-domain interleaved analog-to-digital converter according to claim 2, characterized in that: The clock-controlled sampling switch circuit (1) further comprises an MP4 transistor (16), an MN4 transistor (17) and a Cb bootstrap capacitor (18); the drain of the MP4 transistor (16) is electrically connected to one plate of the Cb bootstrap capacitor (18) and the substrate of the MP4 transistor (16), and the drain of the MN4 transistor (17) is electrically connected to the other plate of the Cb bootstrap capacitor (18); the gate of the MP4 transistor (16) inputs a VG voltage, the drain of the MP4 transistor (16) is electrically connected to the source of the MP6 transistor (13), and the source of the MP6 transistor (13) is electrically connected to the substrate of the MP6 transistor (13); the drain of the MN4 transistor (17) is electrically connected to the source of the MN7 transistor (12).

4. The time skew suppression sampling circuit of a time-domain interleaved analog-to-digital converter according to claim 3, characterized in that: The clock-controlled sampling switch circuit (1) further comprises an MP7 transistor (24), an MP8 transistor (25), an MN8 transistor (26), an MN5 transistor (21), an MN6 transistor (22) and an MP6 transistor (23); the source of the MP7 transistor (24) is electrically connected to the drain of the MP4 transistor (16), and the drain of the MP7 transistor (24) is electrically connected to the source of the MP8 transistor (25); the drain of the MP8 transistor (25) is electrically connected to the drain of the MN8 transistor (26), and the source of the MN8 transistor (26) is electrically connected to the drain of the MN4 transistor (17); the gate of the MP7 transistor (24) inputs a CLK_TRACK[1] clock signal, and the gate of the MN8 transistor (24) inputs a CLK_GLB clock signal; the drain of the MP8 transistor (25) and the drain of the MN8 transistor (26) are electrically connected to the gate of the MP6 transistor (13), and output a VP voltage to the gate of the MP6 transistor (13).

5. The time skew suppression sampling circuit of a time-domain interleaved analog-to-digital converter according to claim 4, characterized in that: The drain of the MN5 transistor (21) is electrically connected to the source of the MN6 transistor (22), the drain of the MN6 transistor (22) is electrically connected to the drain of the MP5 transistor (23), the source of the MP5 transistor (23) is electrically connected to the drain of the MP4 transistor (16) and the substrate of the MP5 transistor (23), and the gate of the MP5 transistor (23) inputs the VP voltage; the drain of the MN6 transistor (22) and the drain of the MP5 transistor (23) are electrically connected to the gate of the MN7 transistor (12), and output the VN voltage to the gate of the MN7 transistor (12).

6. The time skew suppression sampling circuit of a time-domain interleaved analog-to-digital converter according to claim 5, characterized in that: The clock-controlled sampling switch circuit (1) comprises a first group of MOS tube circuits, a second group of MOS tube circuits and a third group of MOS tube circuits; the first group of MOS tube circuits inputs a CLK_GLB clock signal at an input end and outputs an inverted CLK_GLBB clock signal at an output end, and the output end of the first group of MOS tube circuits is electrically connected to the gate of the MN11 transistor (15); the second group of MOS tube circuits inputs a CLK_SEL[1] clock signal at an input end and outputs an inverted CLK_SELB[1] clock signal at an output end, and the output end of the second group of MOS tube circuits is electrically connected to the gate of the MP8 transistor (15); the third group of MOS tube circuits inputs a CLK_TRACK[1] clock signal at an input end and outputs an inverted CLK_TRACKB[1] clock signal at an output end, and the output end of the third group of MOS tube circuits is electrically connected to the gate of the MN4 transistor (17) and the gate of the MN5 transistor (21).

7. The time skew suppression sampling circuit of a time-domain interleaved analog-to-digital converter according to claim 6, characterized in that: The first group of MOS transistor circuits includes an MP1 transistor (31) and an MN1 transistor (34); the second group of MOS transistor circuits includes an MP2 transistor (32) and an MN2 transistor (35); the third group of MOS transistor circuits includes an MP3 transistor (33) and an MN4 transistor (36); the drain of the MP1 transistor (31) is electrically connected to the drain of the MN1 transistor (34), the drain of the MP2 transistor (32) is electrically connected to the drain of the MN2 transistor (35), and the drain of the MP3 transistor (33) is electrically connected to the drain of the MN3 transistor (36).

8. The time skew suppression sampling circuit of a time-domain interleaved analog-to-digital converter according to claim 7, characterized in that: The clock-controlled sampling switch circuit (1) comprises four stages: a bootstrap switch reset stage, an input signal tracking stage, a global clock gating enable stage and a global clock-controlled sampling shutdown stage. When the clock-controlled sampling switch circuit (1) is in the bootstrap switch reset stage, the CLK_GLB clock signal, the CLK_SEL[1] clock signal and the CLK_TRACK[1] clock signal are all at a low level. When the clock-controlled sampling switch circuit (1) is in the input signal tracking stage, the CLK_GLB clock signal and the CLK_SEL[1] clock signal are all at a low level, and the CLK_TRACK[1] clock signal is at a high level. When the clock-controlled sampling switch circuit (1) is in the global clock gating enable stage, the CLK_GLB clock signal, the CLK_SEL[1] clock signal and the CLK_TRACK[1] clock signal are all at a high level. When the clock-controlled sampling switch circuit (1) is in the global clock gating enable stage, the CLK_GLB clock signal, the CLK_SEL[1] clock signal and the CLK_TRACK[1] clock signal are all at a high level.

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