Comparator calibration circuit and comparator calibration method

Abstract

The invention relates to a comparator calibration circuit and a comparator calibration method. The comparator calibration circuit is characterized in that a chip test socket is connected with a chip to be tested; the chip to be tested comprises a plurality of comparator modules; the relay selection circuit is connected with the chip test socket and is used for determining a target comparator module from the plurality of comparator modules according to test requirements; the first converter is connected with the relay selection circuit and is used for determining input voltage; the second converter is connected with the relay selection circuit and is used for receiving the output voltage; and the controller is used for calibrating the target comparator module according to the input voltage and the output voltage of the target comparator module, so that the offset value of the target comparator module is smaller than a target threshold value. According to the comparator calibration circuit, the calibration precision of the comparator modules is improved while automatic calibration of the plurality of comparator modules is realized, and high-precision automatic calibration of the plurality of comparator modules can be realized based on the same comparator calibration circuit.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a comparator calibration circuit and a comparator calibration method. Background Art

[0002] The analog comparator has two input terminals (i.e., P terminal and N terminal) and one output terminal; the input terminal receives analog signals and the output terminal receives digital signals. Ideally, the analog comparator compares the input voltages of the P terminal and the N terminal, and outputs a high 3.3V voltage at the output terminal when the input voltage of the P terminal is greater than the input voltage of the N terminal; and outputs a low 0V voltage at the output terminal when the input voltage of the P terminal is less than the input voltage of the N terminal.

[0003] However, in actual applications, there is an offset value between the two input voltages of the analog comparator. That is, when the input voltage at the P terminal is greater than the input voltage at the N terminal, and the difference between the two is greater than or equal to the offset value, the output voltage at the output terminal of the analog comparator is 3.3V higher; if the difference between the two is less than the offset value, the output voltage will oscillate between 0 and 3.3V. If the offset value is too high, the output voltage of the analog comparator will be unstable, resulting in reduced accuracy of the analog comparator. Summary of the invention

[0004] Based on this, the embodiments of the present application provide a comparator calibration circuit and a comparator calibration method, which improve the calibration accuracy of the comparator modules while realizing automatic calibration of multiple comparator modules, and realize high-precision automatic calibration of multiple comparator modules based on the same comparator calibration circuit.

[0005] In order to achieve the above-mentioned purpose, on the one hand, some embodiments of the present application provide a comparator calibration circuit. The comparator calibration circuit includes a chip test socket, a relay selection circuit, a first converter, a second converter and a controller. The chip test socket is connected to the chip to be tested; the chip to be tested includes multiple comparator modules; the relay selection circuit is connected to the chip test socket, and is used to determine the target comparator module from multiple comparator modules according to the test requirements; the first converter is connected to the relay selection circuit, and is used to determine the input voltage of the target comparator module; the second converter is connected to the relay selection circuit, and is used to receive the output voltage of the target comparator module; the controller is configured to: calibrate the target comparator module according to the input voltage and output voltage of the target comparator module, so that the offset value of the target comparator module is less than the target threshold.

[0006] In some embodiments, the controller includes a sampling unit, a data processing unit, and a calibration unit. The sampling unit is connected to the chip test socket, the first converter, and the second converter, and is configured to: obtain multiple sets of input voltages corresponding to the target output voltages of the chip under test under different temperature environments; the data processing unit is connected to the sampling unit, and is configured to: determine multiple initial calibration models under different temperature environments according to the multiple sets of input voltages of the chip under test under different temperature environments; determine the initial calibration coefficients and initial calibration deviations corresponding to each initial calibration model; determine the target calibration model according to the multiple initial calibration coefficients and the multiple initial calibration deviations; the calibration unit is configured to: calibrate the target comparator module according to the target calibration model, so that the offset value of the target comparator module is less than the target threshold.

[0007] In some embodiments, the data processing unit is further configured to: determine the temperature weight according to the operating temperature of the chip to be tested; calculate the target calibration coefficient and the target calibration deviation according to the temperature weight, multiple initial calibration coefficients and multiple initial calibration deviations, and determine the target calibration model.

[0008] In some embodiments, the controller further includes a first memory; the first memory is connected to the data processing unit and is used to store temperature weights, a plurality of initial calibration coefficients, and a plurality of initial calibration deviations.

[0009] In some embodiments, the controller also includes a temperature sensor for acquiring temperature information of the chip to be tested in real time; the data processing unit is also configured to: determine a calibration coefficient model and a calibration deviation model based on multiple initial calibration coefficients and multiple initial calibration deviations; determine a target calibration coefficient and a target calibration deviation based on the current temperature information of the chip to be tested, the calibration coefficient model and the calibration deviation model, and determine the target calibration model.

[0010] In some embodiments, the controller also includes a second memory and a third memory; the second memory is connected to the temperature sensor and the data processing unit, and is used to store temperature information of the chip to be tested; the third memory is connected to the data processing unit, and is used to store a calibration coefficient model and a calibration deviation model.

[0011] In some embodiments, the comparator calibration circuit also includes a communication chip; the communication chip is connected to the host computer, the chip test socket, the first converter, the second converter and the controller, and is used to receive the automated test code sent by the host computer, and send control instructions to the chip test socket, the first converter, the second converter and the controller according to the automated test code; wherein the communication chip is multiplexed as a fault debugging chip.

[0012] On the other hand, the present application also provides a comparator calibration method according to some embodiments; the comparator calibration method includes: determining a target comparator module from multiple comparator modules of a chip to be tested according to test requirements; obtaining multiple groups of input voltages corresponding to the target output voltages of the chip to be tested under different temperature environments; determining multiple initial calibration models under different temperature environments based on the multiple groups of input voltages of the chip to be tested under different temperature environments; determining an initial calibration coefficient and an initial calibration deviation corresponding to each initial calibration model; determining a target calibration model based on multiple initial calibration coefficients and multiple initial calibration deviations; and calibrating the target comparator module according to the target calibration model so that the offset value of the target comparator module is less than a target threshold.

[0013] In some embodiments, a target calibration model is determined based on multiple initial calibration coefficients and multiple initial calibration deviations, including: determining a temperature weight based on the operating temperature of the chip to be tested; calculating a target calibration coefficient and a target calibration deviation based on the temperature weight, multiple initial calibration coefficients and multiple initial calibration deviations, and determining the target calibration model.

[0014] In some embodiments, determining a target calibration model based on multiple initial calibration coefficients and multiple initial calibration deviations also includes: determining a calibration coefficient model and a calibration deviation model based on multiple initial calibration coefficients and multiple initial calibration deviations; determining a target calibration coefficient and a target calibration deviation based on current temperature information of the chip to be tested, the calibration coefficient model and the calibration deviation model, and determining the target calibration model.

[0015] The embodiments of the present application may or at least have the following advantages:

[0016] In the embodiment of the present application, by connecting the chip to be tested to the chip test socket, different chips to be tested can be flexibly switched, effectively reducing the test interval time of different chips to be tested to improve the calibration efficiency; through the relay selection circuit, a target comparator module is selected from multiple comparator modules of the chip to be tested according to the test requirements to start the test, and switching between one-way comparator module and multiple comparator modules can be performed, thereby realizing separate testing or simultaneous testing of multiple comparator modules, thereby realizing automatic calibration; the first converter provides accurate input voltage, and the second converter accurately collects the output voltage, thereby improving the calibration accuracy; the controller calibrates the target comparator module according to the input voltage and output voltage of the target comparator module, which not only improves the versatility of the comparator calibration circuit, but also effectively improves the calibration accuracy.

[0017] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 is a structural block diagram of a comparator calibration circuit provided in some embodiments;

[0020] Figure 2 is a structural block diagram of another comparator calibration circuit provided in some embodiments;

[0021] Figure 3 is a structural block diagram of yet another comparator calibration circuit provided in some embodiments;

[0022] Figure 4 is a structural block diagram of yet another comparator calibration circuit provided in some embodiments;

[0023] Figure 5 A schematic flow chart of a comparator calibration method provided in some embodiments;

[0024] Figure 6 is a flowchart of step S500 provided in some embodiments;

[0025] Figure 7 is a flowchart of another step S500 provided in some embodiments;

[0026] Figure 8 FIG. 4 is a flow chart of another comparator calibration method provided in some embodiments.

[0027] Description of reference numerals:

[0028] 1-chip test socket, 2-chip to be tested, 21-comparator module, 22-working mode selector, 3-relay selection circuit, 31-first output end of the relay selection circuit, 32-second output end of the relay selection circuit, 33-third output end of the relay selection circuit, GPIO-general input / output interface, DAC0-internal analog-to-digital converter, 4-first converter, 5-second converter, 6-controller, 61-sampling unit, 62-data processing unit, 63-calibration unit, 7-communication chip, 8-host computer. DETAILED DESCRIPTION

[0029] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0031] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0032] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0034] The embodiments of the present application provide a comparator calibration circuit and a comparator calibration method, which improve the calibration accuracy of the comparator modules while realizing automatic calibration of multiple comparator modules, and realize high-precision automatic calibration of multiple comparator modules based on the same comparator calibration circuit.

[0035] In some embodiments, see Figure 1 The comparator calibration circuit includes a chip test socket 1, a relay selection circuit 3, a first converter 4, a second converter 5 and a controller 6. The chip test socket 1 is connected to the chip to be tested 2; the chip to be tested 2 includes a plurality of comparator modules 21; the relay selection circuit 3 is connected to the chip test socket 1, and is used to determine a target comparator module from a plurality of comparator modules 21 according to a test requirement; the first converter 4 is connected to the relay selection circuit 3, and is used to determine an input voltage of the target comparator module; the second converter 5 is connected to the relay selection circuit 3, and is used to receive an output voltage of the target comparator module; the controller 6 is configured to: calibrate the target comparator module according to the input voltage and output voltage of the target comparator module, so that the offset value of the target comparator module is less than a target threshold value.

[0036] By way of example, the comparator module 21 includes, but is not limited to, an analog comparator.

[0037] It should be noted that the target comparator module may be one comparator module or may include multiple comparator modules; that is, the multiple comparator modules in the embodiment of the present application may be tested individually or simultaneously.

[0038] By way of example, the first converter 4 includes but is not limited to an analog-to-digital converter (Digital to Analog Converter, DAC for short).

[0039] For example, the number of bits of the first converter 4 includes 8 bits, 10 bits, 12 bits, 14 bits or 16 bits, etc.; the number of bits of the first converter 4 may be 12 bits, for example.

[0040] By way of example, the second converter 5 includes but is not limited to an analog to digital converter (ADC).

[0041] For example, the number of bits of the second converter 5 includes 8 bits, 10 bits, 12 bits, 14 bits or 16 bits, etc.; the number of bits of the second converter 5 may be 12 bits, for example.

[0042] In the embodiment of the present application, by connecting the chip to be tested 2 with the chip test socket 1, different chips to be tested 2 can be flexibly switched, which effectively reduces the test interval time of different chips to be tested 2 and improves the calibration efficiency; through the relay selection circuit 3, a target comparator module is selected from multiple comparator modules 21 of the chip to be tested 2 according to the test requirements to start the test, and switching between one-way comparator module 21 and multiple-way comparator modules 21 can be performed, thereby realizing separate testing or simultaneous testing of multiple comparator modules 21, thereby realizing automatic calibration; the first converter 4 provides accurate input voltage, and the second converter 5 accurately collects the output voltage, thereby improving the calibration accuracy; the controller 6 calibrates the target comparator module according to the input voltage and output voltage of the target comparator module, which not only improves the versatility of the comparator calibration circuit, but also effectively improves the calibration accuracy.

[0043] In some embodiments, see Figure 2 , the first converter 4 has a first output terminal and a second output terminal; the comparator module 21 has a first input terminal, a second input terminal and an output terminal; the relay selection circuit 3 has a first output terminal, a second output terminal and a third output terminal.

[0044] By way of example, the first input terminal of the comparator module 21 is a P terminal (ie, a positive electrode), and the second input terminal of the comparator module 21 is an N terminal (ie, a negative electrode).

[0045] For example, please continue to see Figure 2 The first output end of the first converter 4 is connected to the first input end of the comparator module 21 via the first output end 31 of the relay selection circuit 3; the second output end of the first converter 4 is connected to the second input end of the comparator module 21 via the second output end 32 of the relay selection circuit 3; the output end of the comparator module 21 is connected to the input end of the second converter 5 via the third output end 33 of the relay selection circuit 3.

[0046] It should be noted that in the embodiment of the present application, the connection between the comparator module 21 and the first converter 4 and the second converter 5 is realized through the relay selection circuit 3. The path selection function of the relay selection circuit 3 can be used to select the target comparator module from the multiple comparator modules 21 of the chip to be tested 2 according to the test requirements to start the test. Switching between one-way comparator module 21 and multiple-way comparator modules 21 can be performed, thereby realizing separate testing or simultaneous testing of multiple comparator modules 21, thereby realizing automatic calibration.

[0047] In some embodiments, the operating modes of the comparator module 21 include a first operating mode (mode 0) and a second operating mode (mode 1); Figure 2The chip under test 2 further includes a working mode selector 22 ; the working mode selector 22 includes a first input terminal, a second input terminal and an output terminal. The working mode selector 22 is used to select the working mode of the comparator module 21 .

[0048] For example, the first input end of the working mode selector 22 is connected to the output of the internal analog-to-digital converter DAC0 of the chip under test 2; the second input end of the working mode selector 22 is connected to the second output end 32 of the relay selection circuit 3; and the output end of the working mode selector 22 is connected to the second input end of the comparator module 21.

[0049] For example, the bit number of the internal analog-to-digital converter DAC0 of the chip under test 2 includes 8 bits, 10 bits, 12 bits, 14 bits or 16 bits, etc.; the bit number of the analog-to-digital converter inside the chip under test 2 can be, for example, 12 bits.

[0050] For some examples, see Figure 2 The chip under test 2 includes a general purpose input / output interface GPIO (General Purpose Input Output, GPIO for short); the first output terminal 31 of the relay selection circuit 3 is connected to the first input terminal of the comparator module 21 via the input interface of the general purpose input / output interface GPIO; the second output terminal 32 of the relay selection circuit 3 is connected to the second input terminal of the working mode selector 22 via the general purpose input / output interface GPIO; the output terminal of the comparator module 21 is connected to the third output terminal 33 of the relay selection circuit 3 via the general purpose input / output interface GPIO.

[0051] In some examples, the input voltage of the comparator module 21 includes a first input voltage input from a first input terminal (P terminal) and a second input voltage input from a second input terminal (N terminal).

[0052] For example, the output voltage of the comparator module 21 has a value range of 0V to 3.3V.

[0053] It should be noted that when the comparator module 21 is in the first working mode (mode 0), the second input terminal (N terminal) of the comparator module 21 is connected to the internal analog-to-digital converter DAC0; when the value range of the output comparator is 0V ~3.3V, the value range of the code value (code) written by the corresponding internal analog-to-digital converter DAC0 is 0~4095.

[0054] For example, the code value (code) written into the internal analog-to-digital converter DAC0 is 2048, and the value of the second input voltage of the second input terminal (N terminal) of the comparator module 21 is 2048 / 4096*3.3V=1.65V.

[0055] In addition, when the comparator module 21 is in the second working mode (mode 1), the second input terminal (N terminal) of the comparator module 21 is connected to the general input / output interface GPIO; wherein the general input / output interface GPIO can be directly connected to the power supply voltage to provide a second input voltage.

[0056] In some embodiments, see Figure 3 , the controller 6 includes a sampling unit 61, a data processing unit 62 and a calibration unit 63. The sampling unit 61 is connected to the chip test socket 1, the first converter 4 and the second converter 5, and is configured to: obtain multiple groups of input voltages corresponding to the target output voltages of the chip under test 2 under different temperature environments; the data processing unit 62 is connected to the sampling unit 61, and is configured to: determine multiple initial calibration models under different temperature environments according to the multiple groups of input voltages of the chip under test 2 under different temperature environments; determine the initial calibration coefficients and initial calibration deviations corresponding to each initial calibration model; determine the target calibration model according to the multiple initial calibration coefficients and the multiple initial calibration deviations; the calibration unit 63 is configured to: calibrate the target comparator module according to the target calibration model, so that the offset value of the target comparator module is less than the target threshold.

[0057] Illustratively, the target output voltage is a high 3.3V.

[0058] It should be noted that the offset value refers to the difference between the first input voltage and the second input voltage when the output voltage is equal to the target output voltage (ie, 3.3V higher).

[0059] In the embodiment of the present application, for example, the target threshold is less than or equal to 20 mV.

[0060] In some embodiments, the different temperature environments of the chip under test 2 include: a first temperature environment, a second temperature environment, and a third temperature environment.

[0061] For example, the first temperature environment is, for example, a low temperature environment; the second temperature environment is, for example, a normal temperature environment; and the third temperature environment is, for example, a high temperature environment.

[0062] It should be noted that the process of the sampling unit 61 acquiring multiple groups of input voltages corresponding to the target output voltages under different temperature environments includes: taking the chip under test 2 under the first temperature environment as an example, the first converter 4 sequentially inputs the target number of first input point voltages (x a ), and while keeping the output voltage of the output terminal equal to the target output voltage (for example, 3.3V higher), adjusting the second input point voltage of the second input terminal to obtain a target number of second input point voltages (y a ), and obtain the target number of first voltage reference points (xa ,y a ); and so on, obtain the target number of second voltage reference points (x b ,y b ) and the target number of third voltage reference points under the third temperature environment (x c ,y c ).

[0063] For example, the target number may be 8, 10, 12, 14 or 16, etc.

[0064] It should be noted that the initial calibration model can be obtained by performing linear fitting on a target number of voltage reference points.

[0065] For example, the initial calibration model may be: y = Kx+B, wherein y is the first input voltage, x is the second input voltage, K is the initial calibration coefficient, and B is the initial calibration deviation.

[0066] In some examples, the process of the data processing unit 62 determining multiple initial calibration models under different temperature environments according to multiple groups of input voltages of the chip under test 2 under different temperature environments includes: setting the target number of first voltage reference points (x a ,y a ) to obtain a first initial calibration model under the first temperature environment; the target number of second voltage reference points (x b ,y b ) to obtain a second initial calibration model under the second temperature environment; the target number of third voltage reference points (x c ,y c ) to perform linear fitting to obtain the third initial calibration model under the third temperature environment.

[0067] In some examples, the process by which the data processing unit 62 determines the initial calibration coefficient and the initial calibration deviation corresponding to each initial calibration model includes: determining the first initial calibration coefficient Ka and the first initial calibration deviation Ba according to the first initial calibration model; determining the second initial calibration coefficient Kb and the second initial calibration deviation Bb according to the second initial calibration model; and determining the third initial calibration coefficient Kc and the third initial calibration deviation Bc according to the third initial calibration model.

[0068] For some examples, see Figure 3 The calibration unit 63 may be connected to the data processing unit 62 , the first converter 4 , the second converter 5 and the chip test socket 1 .

[0069] In some embodiments, the data processing unit 62 is further configured to: determine the temperature weight according to the operating temperature of the chip 2 to be tested; calculate the target calibration coefficient and the target calibration deviation according to the temperature weight, multiple initial calibration coefficients and multiple initial calibration deviations, and determine the target calibration model.

[0070] In some examples, the temperature weight may be a ratio between the first temperature parameter (u), the second temperature parameter (v), and the third temperature parameter (w), ie, u:v:w.

[0071] For example, the value of the temperature weight is determined according to the temperature environment of the chip under test 2. Specifically, the ratio among the first temperature parameter, the second temperature parameter and the third temperature parameter can be the ratio among the working time of the chip under test 2 in the first temperature environment, the working time in the second temperature environment and the working time in the third temperature environment.

[0072] In some examples, the target calibration coefficient may be determined according to the following calculation formula:

[0073] K0=( u*Ka +v*Kb + w*Kc) / (u + v + w);

[0074] Among them, K0 is the target calibration coefficient, Ka is the first initial calibration coefficient under the first temperature environment, Kb is the second initial calibration coefficient under the second temperature environment, Kc is the third initial calibration coefficient under the third temperature environment, u is the first temperature parameter, v is the second temperature parameter, and w is the third temperature parameter.

[0075] In some examples, the target calibration deviation may be determined according to the following calculation formula:

[0076] B0= (u*Ba+v*Bb+ w*Bc) / (u + v + w);

[0077] Among them, B0 is the target calibration deviation, Ba is the first initial calibration deviation under the first temperature environment, Bb is the second initial calibration deviation under the second temperature environment, Bc is the third initial calibration deviation under the third temperature environment, u is the first temperature parameter, v is the second temperature parameter, and w is the third temperature parameter.

[0078] In some embodiments, the target calibration model is: y = K0x+B0; wherein y is the first input voltage, x is the second input voltage, K0 is the target calibration coefficient, and B0 is the target calibration deviation.

[0079] In some embodiments, the controller 6 further includes a first memory; the first memory is connected to the data processing unit 62 and is used to store temperature weights, a plurality of initial calibration coefficients, and a plurality of initial calibration deviations.

[0080] By way of example, the first memory includes, but is not limited to, a flash memory (eflash).

[0081] For example, taking the comparator module 21 having two working modes (mode0, mode1) as an example, the storage contents in the storage space of the first memory and the bytes occupied by each storage content are shown in Table 1.

[0082] Table 1 Storage contents of the first memory and the bytes occupied by each storage content

[0083]

[0084] It should be noted that, in the 4 bytes used to store the temperature weight in a working mode, the first byte is empty, the second byte stores the first temperature parameter, the third byte stores the second temperature parameter, and the fourth byte stores the third temperature parameter.

[0085] In some embodiments, the controller 6 also includes a temperature sensor for acquiring temperature information of the chip under test 2 in real time; the data processing unit 62 is also configured to: determine a calibration coefficient model and a calibration deviation model based on multiple initial calibration coefficients and multiple initial calibration deviations; determine a target calibration coefficient and a target calibration deviation based on the current temperature information of the chip under test 2, the calibration coefficient model and the calibration deviation model, and determine the target calibration model.

[0086] In some examples, the process in which the data processing unit 62 determines the calibration coefficient model and the calibration deviation model based on multiple initial calibration coefficients and multiple initial calibration deviations includes: linearly fitting the first initial calibration coefficient Ka, the second initial calibration coefficient Kb, and the third initial calibration coefficient Kc to obtain the calibration coefficient model; linearly fitting the first initial calibration deviation Ba, the second initial calibration deviation Bb, and the third initial calibration deviation Bc to obtain the calibration deviation model.

[0087] In some embodiments, the calibration coefficient model is: K0=at+m; wherein K is the target calibration coefficient, a is the coefficient value of the coefficient calibration, t is the temperature of the chip 2 to be tested, and m is the deviation value of the coefficient calibration.

[0088] In some embodiments, the deviation coefficient model is: B0= ct +n; wherein B is the target calibration deviation, c is the coefficient value of the deviation calibration, t is the temperature of the chip 2 to be tested, and n is the deviation value of the deviation calibration.

[0089] In some embodiments, the controller 6 also includes a second memory and a third memory; the second memory is connected to the temperature sensor and the data processing unit 62, and is used to store the temperature information of the chip 2 to be tested; the third memory is connected to the data processing unit 62, and is used to store the calibration coefficient model and the calibration deviation model.

[0090] By way of example, the second memory includes but is not limited to a random access memory (Random Access Memory, RAM for short).

[0091] By way of example, the third memory includes, but is not limited to, a flash memory (eFlash).

[0092] In some embodiments, see Figure 4 The comparator calibration circuit also includes a communication chip 7; the communication chip 7 is connected to the host computer 8, the chip test socket 1, the first converter 4, the second converter 5 and the controller 6, and is used to receive the automatic test code sent by the host computer 8, and send control instructions to the chip test socket 1, the first converter 4, the second converter 5 and the controller 6 according to the automatic test code; wherein the communication chip 7 is multiplexed as a fault debugging chip.

[0093] By way of example, the communication chip 7 includes but is not limited to a Universal Asynchronous Receiver / Transmitter (UART for short).

[0094] By way of example, the fault debugging chip includes but is not limited to a J-Link debugger.

[0095] By way of example, the host computer 8 includes but is not limited to a personal computer (PC for short).

[0096] In the embodiment of the present application, through the automated test code in the host computer 8, calibration of all comparator modules 21 in the chip to be tested 2 can be achieved, and automated calibration can be achieved, and a test report can be automatically generated, thereby effectively improving the calibration efficiency.

[0097] In some embodiments, the comparator calibration circuit further includes a clock circuit and a power supply circuit; the clock circuit is used to perform timing control on the comparator calibration circuit; and the power supply circuit is used to supply power to the comparator calibration circuit.

[0098] The present application also provides a comparator calibration method according to some embodiments, and the comparator calibration method can be performed by the comparator calibration circuit in some of the above embodiments. The comparator calibration method also has the technical advantages of the above comparator calibration circuit. It should be noted that the parts that are the same or corresponding to the above embodiments can refer to the corresponding description of the above embodiments, and will not be described in detail below.

[0099] In some embodiments, see Figure 5 , the comparator calibration method includes the following steps S100~S600.

[0100] S100, determining a target comparator module from a plurality of comparator modules of a chip to be tested according to a test requirement.

[0101] S200, obtaining multiple groups of input voltages corresponding to target output voltages of the chip under test under different temperature environments.

[0102] Illustratively, the temperature environment includes a first temperature environment, a second temperature environment, and a third temperature environment.

[0103] For example, step S200 includes: taking the chip to be tested under the first temperature environment as an example, a target number of first input point voltages (xa) are sequentially input from the first input end of the comparator module through the first converter, and while keeping the output voltage of the output end equal to the target output voltage (for example, 3.3V higher), the second input point voltage of the second input end is adjusted to obtain a target number of second input point voltages (ya) corresponding to each first input point voltage one by one, and obtain a target number of first voltage reference points (xa, ya) under the first temperature environment; and so on, a target number of second voltage reference points (xb, yb) under the second temperature environment and a target number of third voltage reference points (xc, yc) under the third temperature environment are obtained.

[0104] S300, determining a plurality of initial calibration models under different temperature environments according to a plurality of groups of input voltages of the chip to be tested under different temperature environments.

[0105] For example, step S300 includes: setting a target number of first voltage reference points (x a ,y a ) to obtain a first initial calibration model under the first temperature environment; the target number of second voltage reference points (x b ,y b ) to obtain a second initial calibration model under the second temperature environment; the target number of third voltage reference points (x c ,y c ) to perform linear fitting to obtain the third initial calibration model under the third temperature environment.

[0106] S400, determining an initial calibration coefficient and an initial calibration deviation corresponding to each initial calibration model.

[0107] For example, step S200 includes: determining a first initial calibration coefficient Ka and a first initial calibration deviation Ba according to a first initial calibration model; determining a second initial calibration coefficient Kb and a second initial calibration deviation Bb according to a second initial calibration model; and determining a third initial calibration coefficient Kc and a third initial calibration deviation Bc according to a third initial calibration model.

[0108] S500: Determine a target calibration model according to a plurality of initial calibration coefficients and a plurality of initial calibration deviations.

[0109] S600, calibrating a target comparator module according to a target calibration model, so that an offset value of the target comparator module is less than a target threshold.

[0110] Illustratively, the target threshold is less than or equal to 20 mV.

[0111] In some embodiments, see Figure 6 , step S500 includes the following steps S511~S512.

[0112] S511, determining a temperature weight according to the operating temperature of the chip to be tested.

[0113] S512, calculating a target calibration coefficient and a target calibration deviation according to the temperature weight, a plurality of initial calibration coefficients and a plurality of initial calibration deviations, and determining a target calibration model.

[0114] In some embodiments, see Figure 7 , step S500 also includes the following steps S521~S522.

[0115] S521, determining a calibration coefficient model and a calibration deviation model according to a plurality of initial calibration coefficients and a plurality of initial calibration deviations.

[0116] For example, step S521 includes: linearly fitting the first initial calibration coefficient Ka, the second initial calibration coefficient Kb and the third initial calibration coefficient Kc to obtain a calibration coefficient model; linearly fitting the first initial calibration deviation Ba, the second initial calibration deviation Bb and the third initial calibration deviation Bc to obtain a calibration deviation model.

[0117] S522, determining a target calibration coefficient and a target calibration deviation, and determining a target calibration model according to the current temperature information of the chip to be tested, the calibration coefficient model, and the calibration deviation model.

[0118] It should be noted that in the embodiment of the present application, two calibration methods as described in steps S511~S512 and steps S521~S522 are used to calibrate the comparator module, which can perform comparator calibration on test chips in different usage scenarios, thereby improving the applicability of the comparator calibration method.

[0119] In some embodiments, taking the calibration of a target comparator module as an example, see Figure 8 The comparator calibration method also includes the following steps S1 to S7.

[0120] S1, host computer self-test.

[0121] S2, initializing the relay selection circuit, initializing the first converter, and initializing the second converter.

[0122] S3, select calibration mode.

[0123] It should be noted that the calibration mode includes the first calibration mode described in steps S511 to S512 in some of the aforementioned embodiments, and the second calibration mode described in steps S521 to S522 in some of the aforementioned embodiments.

[0124] S4, determine the input voltage through the first converter, obtain the output voltage through the second converter, and determine whether the output voltage is equal to the target output voltage; if not, execute step S5; if yes, execute step S6.

[0125] S5, calibrating the comparator module and adjusting the output of the first converter according to the target calibration model; and returning to step S4.

[0126] S6, record calibration data.

[0127] S7, when all comparator modules in the chip under test are calibrated, the calibration data is sorted out and a calibration report is automatically generated.

[0128] It should be noted that the calibration of the comparator module in step S5 includes the steps of the comparator calibration method provided in some of the aforementioned embodiments of the present application.

[0129] It should be understood that although Figure 5~Figure 8 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 5~Figure 8 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0130] In the description of this specification, the description with reference to the terms "some embodiments", "some examples", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0131] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A comparator calibration circuit, characterized in that: include: A chip test socket connected to a chip to be tested; the chip to be tested includes a plurality of comparator modules; A relay selection circuit, connected to the chip test socket, for determining a target comparator module from the plurality of comparator modules according to a test requirement; a first converter, connected to the relay selection circuit, for determining an input voltage of the target comparator module; a second converter, connected to the relay selection circuit, for receiving the output voltage of the target comparator module; The controller is configured to: calibrate the target comparator module according to the input voltage and the output voltage of the target comparator module, so that the offset value of the target comparator module is less than a target threshold.

2. The comparator calibration circuit according to claim 1, characterized in that: The controller comprises: A sampling unit is connected to the chip test socket, the first converter and the second converter, and is configured to: obtain multiple groups of input voltages corresponding to target output voltages of the chip under test under different temperature environments; A data processing unit is connected to the sampling unit and is configured to: determine a plurality of initial calibration models under different temperature environments according to the plurality of input voltages of the chip under test under different temperature environments; determine an initial calibration coefficient and an initial calibration deviation corresponding to each of the initial calibration models; and determine a target calibration model according to the plurality of initial calibration coefficients and the plurality of initial calibration deviations; The calibration unit is configured to calibrate the target comparator module according to the target calibration model so that the offset value of the target comparator module is less than a target threshold.

3. The comparator calibration circuit according to claim 2, characterized in that: The data processing unit is also configured to: determine the temperature weight according to the operating temperature of the chip to be tested; calculate the target calibration coefficient and the target calibration deviation according to the temperature weight, multiple initial calibration coefficients and multiple initial calibration deviations, and determine the target calibration model.

4. The comparator calibration circuit according to claim 3, characterized in that: The controller further comprises: The first memory is connected to the data processing unit and is used to store the temperature weight, a plurality of the initial calibration coefficients and a plurality of the initial calibration deviations.

5. The comparator calibration circuit according to claim 2, characterized in that: The controller also includes a temperature sensor for acquiring the temperature information of the chip to be tested in real time; the data processing unit is also configured to: determine a calibration coefficient model and a calibration deviation model based on a plurality of the initial calibration coefficients and a plurality of the initial calibration deviations; determine a target calibration coefficient and a target calibration deviation based on the current temperature information of the chip to be tested, the calibration coefficient model and the calibration deviation model, and determine the target calibration model.

6. The comparator calibration circuit according to claim 5, characterized in that: The controller further comprises: A second memory, connected to the temperature sensor and the data processing unit, for storing temperature information of the chip to be tested; The third memory is connected to the data processing unit and is used to store the calibration coefficient model and the calibration deviation model.

7. The comparator calibration circuit according to claim 1, characterized in that: Also includes: A communication chip, connected to the host computer, the chip test socket, the first converter, the second converter and the controller, for receiving the automated test code sent by the host computer, and sending control instructions to the chip test socket, the first converter, the second converter and the controller according to the automated test code; Wherein, the communication chip is multiplexed as a fault debugging chip.

8. A comparator calibration method, characterized in that: include: Determine a target comparator module from a plurality of comparator modules of the chip to be tested according to the test requirements; Acquire multiple groups of input voltages corresponding to target output voltages of the chip under test under different temperature environments; Determining a plurality of initial calibration models under different temperature environments according to a plurality of groups of input voltages of the chip under test under different temperature environments; Determining an initial calibration coefficient and an initial calibration deviation corresponding to each of the initial calibration models; Determining a target calibration model according to the plurality of initial calibration coefficients and the plurality of initial calibration deviations; The target comparator module is calibrated according to the target calibration model so that the offset value of the target comparator module is less than a target threshold value.

9. The comparator calibration method according to claim 8, characterized in that: The step of determining a target calibration model according to the plurality of initial calibration coefficients and the plurality of initial calibration deviations comprises: Determining a temperature weight according to the operating temperature of the chip to be tested; According to the temperature weight, the plurality of initial calibration coefficients and the plurality of initial calibration deviations, a target calibration coefficient and a target calibration deviation are calculated, and the target calibration model is determined.

10. The comparator calibration method according to claim 8, characterized in that: The determining of a target calibration model according to the plurality of initial calibration coefficients and the plurality of initial calibration deviations further comprises: Determining a calibration coefficient model and a calibration deviation model according to the plurality of initial calibration coefficients and the plurality of initial calibration deviations; According to the current temperature information of the chip to be tested, the calibration coefficient model and the calibration deviation model, a target calibration coefficient and a target calibration deviation are determined, and the target calibration model is determined.

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