Method and device for testing protocol consistency function of network switching chip

Abstract

The invention provides a method and a device for testing a protocol consistency function of a network switching chip. According to the method, a PGC module is arranged in each port of the network switching chip, and protocol consistency function testing is conducted on the network switching chip through the PGC modules. Wherein the PGC module is located in a core switch in the network switch chip and a sending path direction of each port, and the PGC module refers to packet generation and packet capture; the method specifically comprises the following steps of: configuring two ports of a network switching chip into a packet generation port and a packet capture port respectively by utilizing the PGC module; writing a protocol packet at the packet generation port by using the PGC module, sending out the protocol packet, and capturing the protocol packet passing through the core switching route at the packet capturing port; and determining connectivity and protocol consistency of all ports on a routing path according to a protocol packet written at the packet generation port and a protocol packet captured at the packet capture port.

Description

Technical Field

[0001] The present invention relates to the technical field of chip function debugging, and in particular to a method and device for testing the protocol consistency function of a network switching chip. Background Art

[0002] Protocol consistency functional testing is an important test indicator for high-speed network switching chips. The existing port protocol consistency testing method for network switching chips usually involves docking the chip under test with a protocol tester or standard equipment available on the market to verify the port protocol consistency of the chip under test.

[0003] At present, relevant testing technologies include chip built-in self-test (BIST) technology (such as CN116758968A and CN114036885A), technologies related to communication protocol consistency testing (such as CN116668346A), and technologies related to external standard test equipment or self-developed packet generators (such as FPGA-based software-defined traffic generators [J]).

[0004] Built-in self-test technology is a technology that implants relevant functional circuits in the circuit during design to provide self-test functions, thereby reducing the dependence of device testing on automatic test equipment (ATE). BIST technology can be roughly divided into two categories: logic BIST (LogicBIST, LBIST) and memory BIST (Memory BIST, MBIST). Built-in self-test technology can complete most of the defect tests of chips during the manufacturing process, but it cannot complete the functional tests inside the chip. Therefore, built-in self-test technology is usually used in chip screening.

[0005] CN116668346A provides a network protocol consistency testing method and system device, the method comprising: obtaining the image file of the target container, and constructing a target test topology environment according to the image file and the target device to be tested; in the target test topology environment, testing the network protocol consistency of the target device to be tested according to the test tool in the image file to obtain the target test result; however, the method depends on the image file in the target container and the network protocol consistency testing tool.

[0006] "FPGA-based software-defined traffic generator" proposes a software-defined traffic generator based on FPGA (field programmable gate array) or hardware implementation, which supports the configuration of the protocol type, quantity, length, interval, etc. of each port data packet, and has high speed, flexibility and scalability; but it is used as an external test tool to connect with the device under test for testing, while the traditional protocol function consistency test method of connecting with standard test instruments and equipment has made the test cost increasingly uncontrollable due to the complex test environment construction, long test time, limited I / O channels and expensive memory resources. Summary of the invention

[0007] The present invention provides a method and device for testing the protocol consistency function of a network switching chip, aiming to complete the functional test of the connectivity of each port of a high-speed network switching chip and the protocol function consistency test, and is independent of external testing tools.

[0008] In a first aspect, the present invention provides a method for testing the protocol consistency function of a network switching chip, wherein a PGC module is provided inside each port of the network switching chip, and the network switching chip is tested for protocol consistency function using the PGC module; wherein the PGC module is located in the core switching and the sending path direction of each port in the network switching chip, and PGC refers to packet generation and packet capture; the method specifically comprises: Using the PGC module, two ports of the network switch chip are configured as a packet generation port and a packet capture port respectively; Using the PGC module to write a protocol packet at the packet generation port and send it out, and capturing the protocol packet routed via the core switch at the packet capture port; The connectivity and protocol consistency of all ports on the routing path are determined according to the protocol packet written at the packet generation port and the protocol packet captured at the packet capture port.

[0009] Further, using the PGC module to write a protocol packet at the packet generation port and send it out, and capturing the protocol packet routed via the core switch at the packet capture port, specifically includes: Writing a protocol request packet at the packet generation port and sending it to the standard device at the other end of the link and receiving a response packet returned by the standard device at the other end of the link; The packet generation port forwards the response packet to the packet capture port via the core switch route, and the packet capture port captures the response packet via the core switch route.

[0010] Further, the PGC module is used to write a protocol packet at the packet generation port and send it out, and the protocol packet routed via the core switch is captured at the packet capture port, specifically including: Writing a request protocol packet at the packet generation port, and forwarding the request protocol packet to one of the ports C of the network switch chip through the core switch routing in a port loopback manner, so that the port C forwards the request protocol packet to the standard device at the other end of the link and receives a response packet returned by the standard device at the other end of the link; The port C forwards the response packet to the packet capture port via the core switch route, and the packet capture port captures the response packet via the core switch route.

[0011] Further, the PGC module is used to write a protocol packet at the packet generation port and send it out, and the protocol packet routed via the core switch is captured at the packet capture port, specifically including: A protocol data packet is written at the packet generation port, and the protocol data packet is forwarded to the packet capture port via the core switch routing in a port loopback manner, and the packet capture port captures the protocol data packet via the core switch routing.

[0012] Further, the PGC module is used to write a protocol packet at the packet generation port and send it out, and the protocol packet routed via the core switch is captured at the packet capture port, specifically including: A protocol data packet is written at the packet generation port, and the protocol data packet is forwarded to at least one port of the network switching chip through the core switching router by using a port loopback method. The last port forwards the protocol data packet to the packet capture port through the core switching router by using a port loopback method. The packet capture port captures the protocol data packet passing through the core switching router.

[0013] Further, the PGC module includes a configuration bus synchronization unit, a PGC register, a PG state machine, a PC state machine, a PGC cache and a multiplexer; wherein PG refers to packet generation, and PC refers to packet capture; The configuration bus synchronization unit is used to convert the AXI configuration bus to the local configuration bus; The PGC register includes a PGC control register and a PGC data register; the PGC controller is used to control the working mode of the current port, the working mode includes a normal data path mode and a PGC mode, and the PGC mode includes a PG mode and a PC mode; the PGC data register is used to store the protocol packet written to the current port in the PG mode, and to store the protocol packet read out of the current port in the PC mode; The PG state machine is used to write the protocol packet in the PGC data register into the PGC cache according to the configuration value of the PGC control register; The PC state machine is used to read the protocol packet sent by the core switch to the PGC cache into the PGC data register according to the configuration value of the PGC control register; The PGC cache is used to cache a protocol packet of a maximum length; The multiplexer is used to select a data path according to the configuration value of the PGC control register.

[0014] Further, the PGC control register includes five valid domain segments: TX_Start, RX_Done, SOP, EOP, Start_Port and End_Port; The TX_Start field is used to indicate whether the current port can send out the protocol packet written in the PGC cache in PG mode; The RX_Done field is used to indicate whether the current port can read the protocol packet in the PGC cache in PC mode; The SOP field is used to indicate whether the current port writes a protocol packet for the first time in PG mode, and indicates whether the current port reads a protocol packet for the first time in PC mode; The EOP field is used to indicate whether the current port has last written a protocol packet in PG mode, and whether the current port has last read a protocol packet in PC mode; The Start_Port field is used to indicate whether the current port's working mode is PG mode; The End_Port field is used to indicate whether the current port's working mode is PC mode.

[0015] In a second aspect, the present invention provides a device for testing the protocol consistency function of a network switching chip, comprising a PGC module and a test module arranged inside each port of the network switching chip; wherein the PGC module is located in the core switching of the network switching chip and the sending path direction of each port; PGC refers to packet generation and packet capture; The PGC module is used to configure two ports of the network switching chip as a packet generation port and a packet capture port respectively; and is used to write a protocol packet at the packet generation port and send it out, and capture the protocol packet routed via the core switch at the packet capture port; The test module is used to determine the connectivity and protocol consistency of all ports on the routing path according to the protocol packets written at the packet generation port and the protocol packets captured at the packet capture port.

[0016] Further, the PGC module includes a configuration bus synchronization unit, a PGC register, a PG state machine, a PC state machine, a PGC cache and a multiplexer; wherein PG refers to packet generation, and PC refers to packet capture; The configuration bus synchronization unit is used to convert the AXI configuration bus to the local configuration bus; The PGC register includes a PGC control register and a PGC data register; the PGC controller is used to control the working mode of the current port, the working mode includes a normal data path mode and a PGC mode, and the PGC mode includes a PG mode and a PC mode; the PGC data register is used to store the protocol packet written to the current port in the PG mode, and to store the protocol packet read out of the current port in the PC mode; The PG state machine is used to write the protocol packet in the PGC data register into the PGC cache according to the configuration value of the PGC control register; The PC state machine is used to read the protocol packet sent by the core switch to the PGC cache into the PGC data register according to the configuration value of the PGC control register; The multiplexer is used to select a data path according to the configuration value of the PGC control register.

[0017] Further, the PGC control register includes five valid domain segments: TX_Start, RX_Done, SOP, EOP, Start_Port and End_Port; The TX_Start field is used to indicate whether the current port can send out the protocol packet written in the PGC cache in PG mode; The RX_Done field is used to indicate whether the current port can read the protocol packet in the PGC cache in PC mode; The SOP field is used to indicate whether the current port writes a protocol packet for the first time in PG mode, and indicates whether the current port reads a protocol packet for the first time in PC mode; The EOP field is used to indicate whether the current port has last written a protocol packet in PG mode, and whether the current port has last read a protocol packet in PC mode; The Start_Port field is used to indicate whether the current port's working mode is PG mode; The End_Port field is used to indicate whether the current port's working mode is PC mode.

[0018] Beneficial effects of the present invention: 1. Simplifies the process of building a functional consistency test environment for network switching chips. By adopting the method and device provided by the present invention, after the chip is returned from the tape-out, without relying on external protocol test instruments and equipment, the functional debugging of the chip and the connectivity test of each port can be quickly completed in a laboratory environment, and it can be judged whether the design function of the chip to be tested meets expectations and whether there are defects in chip production and manufacturing, which can improve the chip testing efficiency.

[0019] 2. Connectivity and protocol function consistency tests can be completed using standard equipment at the other end of the link; or, in the absence of standard equipment at the other end of the link, port connectivity and protocol function consistency tests can be completed on an ATE machine in combination with a port loopback method. ATE is a system for testing electronic devices that can automatically execute test programs and compare test results with expected results. By using the method and device provided by the present invention, the preparation of the protocol function consistency offline test program is completed before the chip is returned, and the debugging of the test program is completed after the chip is returned. Automated testing of port connectivity and protocol function consistency is completed on an ATE machine, which helps to ensure that the chip performs tasks correctly under various working conditions, helps to discover and solve potential quality problems that may cause chip failure, improves the performance of the chip in actual applications, and meets the ever-changing market needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A flowchart of a method for testing the protocol consistency function of a network switch chip provided by an embodiment of the present invention; Figure 2 The location of the PGC module provided in the embodiment of the present invention in the network switching chip; Figure 3 A structural block diagram of a PGC module provided in an embodiment of the present invention; Figure 4 Schematic diagram of each field segment of the PGC register provided for the embodiment of the present invention: (a) PGC control register, (b) PGC data register; Figure 5 One of the typical application scenarios of PGC provided by the embodiment of the present invention; Figure 6 The second typical application scenario of PGC provided by the embodiment of the present invention; Figure 7 The third typical application scenario of PGC provided by the embodiment of the present invention; Figure 8 This is the fourth typical application scenario of PGC provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] Figure 1 A flowchart of a method for testing the protocol consistency function of a network switch chip is provided for an embodiment of the present invention. Figure 2 Describes the implementation structure diagram of the network switching chip and the location of the PGC module in the network switching chip. Figure 1 and Figure 2 As shown, an embodiment of the present invention provides a method for testing the protocol consistency function of a network switching chip, wherein a PGC module is arranged inside each port (Port) of the network switching chip, and the PGC module is used to perform a protocol consistency function test on the network switching chip; wherein the PGC module is located in the core switch (Switch Fabric) in the network switching chip and the sending path direction of each port, PGC: Packet Generation and Capture, refers to packet generation and packet capture; it can be understood that an embodiment of the present invention can implant a PGC module with packet generation and packet capture functions when designing the chip, so that the PGC module can be used subsequently to complete the generation and capture of protocol packets.

[0023] The method specifically comprises: S101: using the PGC module to configure two ports of the network switch chip as a packet generation port (also called a start port) and a packet capture port (also called an end port); S102: Using the PGC module to write a protocol packet at the packet generation port and send it out, and capturing the protocol packet routed via the core switch at the packet capture port; In this embodiment, a complete protocol packet is written word by word (32 bits) through I2C or JTAG at the Start Port and sent, and the protocol packet forwarded through the core switch is captured at the End Port, and the captured protocol packet is subsequently read out word by word in a 32-bit manner.

[0024] S103: Determine connectivity and protocol consistency of all ports on the routing path according to the protocol packet written at the packet generation port and the protocol packet captured at the packet capture port.

[0025] The method for testing the protocol consistency function of a network switching chip provided by an embodiment of the present invention utilizes the packet generation and packet capture functions of the PGC module to perform functional testing of port path connectivity and protocol consistency. After the chip is returned to the chip, the method of the present invention can be used to quickly complete the functional debugging of the chip and the connectivity test of each port in a laboratory environment without relying on standard protocol testing instruments and equipment, and to determine whether the design function of the chip to be tested meets expectations and whether there are defects in chip production and manufacturing. Therefore, the present invention greatly simplifies the construction process of the functional consistency test environment of the network switching chip. At the same time, the method of the present invention supports the completion of port connectivity and protocol function consistency testing on an ATE machine. ATE is a system for testing electronic devices, which can automatically execute test programs and compare test results with expected results. Using the method of the present invention, the preparation of the protocol function consistency offline test program is completed before the chip is returned to the chip, and the debugging of the test program is completed after the chip is returned to the chip, and the automated testing of port connectivity and protocol function consistency is completed on the ATE machine, which helps to ensure that the chip performs tasks correctly under various working conditions, helps to discover and solve potential quality problems that may cause chip failure, improves the performance of the chip in practical applications, and meets the ever-changing market needs. It should be noted that the protocol function consistency test method based on packet generation and packet capture provided by the present invention does not conflict with the built-in self-test technology, and the two can coexist in the same chip.

[0026] In one embodiment, Figure 3 An implementation structure of the PGA module is given, such as Figure 3 As shown in the figure, the implementation structure of the PGC module mainly includes five units: configuration bus synchronization unit, PGC register, PG state machine, PC state machine, PGC cache (also called PGC_buffer) and multiplexer; among them, PG: Packet Generation, refers to packet generation, PC: PacketCapture, refers to packet capture; Specifically, the configuration bus synchronization unit is used to convert the AXI configuration bus to the local configuration bus. The PGC register includes a PGC control register and a PGC data register; wherein the PGC controller is used to control the working mode of the current port, and the working mode includes a normal data path mode and a PGC mode, and the PGC mode includes a PG mode and a PC mode. The PGC data register is used to store the protocol packets written to the current port in the PG mode, and to store the protocol packets read out of the current port in the PC mode; the PG state machine is used to write the protocol packets in the PGC data register into the PGC cache according to the configuration value of the PGC control register; the PC state machine is used to read the protocol packets sent by the core exchange to the PGC cache into the PGC data register according to the configuration value of the PGC control register; the multiplexer is used to select a data path according to the configuration value of the PGC control register, such as a PG port mode path, a PC port mode path, and a normal data path (i.e., a non-PGC mode path).

[0027] In this embodiment, the PGC control register and the PGC data register are both 32-bit registers. It can be understood that the PGC mode is turned on or off according to the configuration values ​​of each field of the PGC control register, and in the PGC mode, it is distinguished whether the current port is used for PG (i.e., the current port is configured as Start Port) or PC (i.e., the current port is configured as End Port) and other functions. It can be understood that when a port is configured into PGC mode, the port can only be used in PG mode or PC mode at this time, and cannot be used for normal data exchange.

[0028] In this embodiment, according to the configuration value of the PGC control register, the PG state machine writes the data of the 32-bit PGC data register into the PGC_buffer module in sequence until a complete protocol packet (including the header and payload) is written. Similarly, according to the configuration value of the PGC control register, the PC state machine reads out a complete packet sent by the core exchange to the PGC_buffer module in sequence in 32-bit mode.

[0029] Further, Figure 4 The schematic diagram of each field segment of the PGC control register and the PGC data register is described. The meaning of the register field segments can make it easier to understand the functional implementation of the PGC. Figure 4(a) only lists the fields that are closely related to the PGC function, and the Reserved field [31:6] can be expanded according to the implementation needs. The valid fields of the PGC control register include TX_Start, RX_Done, SOP (Start of Packet), EOP (End of Packet), Start_Port and End_Port, a total of 5 fields.

[0030] Among them, the TX_Start field is used to indicate whether the current port can send out the protocol packet written in the PGC cache in PG mode. The RX_Done field is used to indicate whether the current port can read the protocol packet in the PGC cache in PC mode. The SOP field is used to indicate whether the current port writes a protocol packet for the first time in PG mode, and indicates whether the current port reads a protocol packet for the first time in PC mode. The EOP field is used to indicate whether the current port writes a protocol packet for the last time in PG mode, and indicates whether the current port reads a protocol packet for the last time in PC mode. The Start_Port field is used to indicate whether the working mode of the current port is PG mode. The End_Port field is used to indicate whether the working mode of the current port is PC mode.

[0031] Specifically, the TX_Start field is used in PG mode. After all protocol packets are written to PGC_buffer word by word in 32-bit mode, the TX_Start field can be configured to 1 to indicate that the current Start_Port can send out the protocol packet. The RX_Done field is a read-only field and is used in PC mode. In PC mode, the field is 1 to indicate that the current End_Port has received a complete protocol packet and can now read the protocol packet word by word in 32-bit mode from PGC_buffer. The SOP field is configured to 1 to indicate the first time the protocol packet data is written in 32-bit mode in PG mode or the first time the protocol packet is read from PGC_buffer in 32-bit mode in PC mode. The EOP field is configured to 1 to indicate the last time the protocol packet data is written in 32-bit mode in PG mode or the last time the protocol packet is read from PGC_buffer in 32-bit mode in PC mode. When the Start_Port field is configured to 1, it indicates that the port is configured in PG mode at this time. When the End_Port field is configured to 1, it indicates that the port is configured in PC mode at this time.

[0032] It is understandable that in PGC mode, one of the two fields Start_Port and End_Port must be configured as 1. When both the Start_Port and End_Port fields are configured as 0, it means that the port is in non-PGC mode, that is, the port is a common protocol packet forwarding port.

[0033] Figure 4 (b) lists the Data field of the PGC data register, where the Data field represents the 32-bit protocol packet data written word by word into the PGC_buffer in PG mode, or represents the 32-bit protocol packet data read from the PGC_buffer in PC mode.

[0034] By alternately configuring the PGC control register and the PGC data register multiple times, the generation of protocol packets in PG mode or the capture of protocol packets in PC mode can be completed.

[0035] In one embodiment, Figure 5 One of the typical application scenarios of PGC module is given. Figure 5 As shown in FIG. 1 , two ports (port A and port B) of the network switch chip and the standard equipment at the other end of the link are described. Port A is configured in PG mode, i.e., Start Port A; Port B is configured in PC mode, i.e., End Port B. A protocol request packet is written to Start Port A (in this embodiment, directly using Figure 3 The PGC module structure shown, correspondingly, the process of writing a protocol request packet includes: configuring the PGC control register and the PGC data register in sequence according to the packet generation method), then sending the protocol request packet to the standard device at the other end of the link, after receiving the protocol request packet, the standard device at the other end of the link sends a response packet to StartPort A, Start Port A forwards the response packet to End Port B through the core switching routing, and then reads out the response packet captured by End Port B in the form of register access, thereby verifying the connectivity and protocol consistency of Port A and Port B.

[0036] In one embodiment, Figure 6 Another typical application scenario of PGC module is given. Figure 5The application scenario is similar to that of , where port A is configured in PG mode, namely Start Port A; port B is configured in PC mode, namely End Port B. The difference is that this scenario also adds a port Port C, and port C is connected to the standard device at the other end of the link. In this scenario, StartPort A first forwards the protocol request packet generated in PG mode to port C through port loopback. Port C sends the received protocol request packet to the standard device at the other end of the link. The standard device at the other end of the link then sends the response packet to port C, and port C then forwards the response packet to End Port B through the core switching route. Finally, the response packet captured by port B is read out through register access to verify the connectivity and protocol consistency of ports A, B, and C.

[0037] In one embodiment, Figure 7 The application scenario of the PGC module in the absence of standard equipment on the link peer end is given, such as the application in the ATE machine test scenario. At this time, port A is configured to PG mode, that is, Start Port A; port B is configured to PC mode, that is, End Port B; port A adopts port loopback mode. At Start Port A, the PGC control register and PGC data register are configured in sequence according to the packet generation method, and the protocol data packet is sent out through the sending end, and then looped back to the receiving end of Start Port A through the port loopback mode, and then the protocol data packet of Start Port A is forwarded to End Port B through the core switching route, and then the protocol data packet captured by EndPort B is read out by register access, thereby verifying the connectivity and protocol consistency of Port A and Port B.

[0038] In one embodiment, Figure 7 The application scenario is similar. Figure 8The application scenario of the PGC module in the scenario where there is no standard equipment on the link peer end, and the port loopback mode is used to verify the connectivity and protocol consistency of multiple ports. At this time, port A is configured in PG mode, that is, Start Port A; port B is configured in PC mode, that is, End Port B; the difference is that two ports are added on the routing path in this scenario. Port A adopts port loopback mode. At Start Port A, the PGC control register and PGC data register are configured in sequence according to the packet generation method, and the protocol data packet is sent out through the sending end, and then looped back to the receiving end of Start Port A through the port loopback mode, and then the protocol data packet of Start Port A is forwarded to one of the newly added ports through the core switching route. This port also uses the port loopback method to forward the protocol data packet through the core switching route to another newly added port. The other port also uses the port loopback method to forward the protocol data packet through the core switching route to End Port B, and then the protocol data packet captured by End Port B is read out in the register access method, thereby verifying the connectivity and protocol consistency of Port A, Port B, and the two newly added ports.

[0039] The embodiment of the present invention also provides a device for testing the protocol consistency function of a network switching chip, comprising a PGC module and a test module arranged inside each port of the network switching chip; wherein the PGC module is located in the core switching of the network switching chip and the sending path direction of each port; PGC refers to packet generation and packet capture; Among them, the PGC module is used to configure two ports of the network switching chip as a packet generation port and a packet capture port respectively; and is used to write a protocol packet at the packet generation port and send it out, and capture the protocol packet routed via the core switch at the packet capture port; the test module is used to determine the connectivity and protocol consistency of all ports on the routing path based on the protocol packet written at the packet generation port and the protocol packet captured at the packet capture port.

[0040] In one embodiment, the structure of the PGC module in this embodiment is as follows: Figure 3 and Figure 4 It can be understood that the device for testing the protocol consistency function of a network switch chip provided in the embodiment of the present invention is to implement the above method, and its specific functions can be referred to the above method embodiments, which will not be described in detail here.

[0041] The method and device for testing the protocol consistency function of a network switching chip proposed in the present invention, by setting a PGC module with packet generation and packet capture functions inside each port of the network switching chip, and then using the PGC module to implement the chip protocol consistency function test, there is no need to connect to standard test equipment externally, thereby simplifying the construction of the test environment; and, it can be applicable to scenarios with link peer devices, and also supports automatic testing on ATE, that is, it can be applied to scenarios without link peer devices through port loopback mode.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for testing the protocol consistency function of a network switching chip, characterized in that: A PGC module is provided inside each port of the network switching chip, and the PGC module is used to perform a protocol consistency function test on the network switching chip; wherein the PGC module is located in the core switching and the sending path direction of each port in the network switching chip, and PGC refers to packet generation and packet capture; the method specifically comprises: Using the PGC module, two ports of the network switch chip are configured as a packet generation port and a packet capture port respectively; Using the PGC module to write a protocol packet at the packet generation port and send it out, and capturing the protocol packet routed via the core switch at the packet capture port; The connectivity and protocol consistency of all ports on the routing path are determined according to the protocol packet written at the packet generation port and the protocol packet captured at the packet capture port.

2. A method for testing the protocol consistency function of a network switch chip according to claim 1, characterized in that: Using the PGC module to write a protocol packet at the packet generation port and send it out, and capturing the protocol packet routed via the core switch at the packet capture port, specifically includes: Writing a protocol request packet at the packet generation port and sending it to the standard device at the other end of the link and receiving a response packet returned by the standard device at the other end of the link; The packet generation port forwards the response packet to the packet capture port via the core switch route, and the packet capture port captures the response packet via the core switch route.

3. A method for testing the protocol consistency function of a network switch chip according to claim 1, characterized in that: Using the PGC module to write a protocol packet at the packet generation port and send it out, and capturing the protocol packet routed via the core switch at the packet capture port, specifically also includes: Writing a request protocol packet at the packet generation port, and forwarding the request protocol packet to one of the ports C of the network switch chip through the core switch routing in a port loopback manner, so that the port C forwards the request protocol packet to the standard device at the other end of the link and receives a response packet returned by the standard device at the other end of the link; The port C forwards the response packet to the packet capture port via the core switch route, and the packet capture port captures the response packet via the core switch route.

4. A method for testing the protocol consistency function of a network switching chip according to claim 1, characterized in that: Using the PGC module to write a protocol packet at the packet generation port and send it out, and capturing the protocol packet routed via the core switch at the packet capture port, specifically also includes: A protocol data packet is written at the packet generation port, and the protocol data packet is forwarded to the packet capture port via the core switch routing in a port loopback manner, and the packet capture port captures the protocol data packet via the core switch routing.

5. A method for testing the protocol consistency function of a network switch chip according to claim 1, characterized in that: Using the PGC module to write a protocol packet at the packet generation port and send it out, and capturing the protocol packet routed via the core switch at the packet capture port, specifically also includes: A protocol data packet is written at the packet generation port, and the protocol data packet is forwarded to at least one port of the network switching chip through the core switching router by using a port loopback method. The last port forwards the protocol data packet to the packet capture port through the core switching router by using a port loopback method. The packet capture port captures the protocol data packet passing through the core switching router.

6. A method for testing the protocol consistency function of a network switch chip according to any one of claims 1 to 5, characterized in that: The PGC module includes a configuration bus synchronization unit, a PGC register, a PG state machine, a PC state machine, a PGC cache and a multiplexer; wherein PG refers to packet generation, and PC refers to packet capture; The configuration bus synchronization unit is used to convert the AXI configuration bus to the local configuration bus; The PGC register includes a PGC control register and a PGC data register; the PGC controller is used to control the working mode of the current port, the working mode includes a normal data path mode and a PGC mode, and the PGC mode includes a PG mode and a PC mode; the PGC data register is used to store the protocol packet written to the current port in the PG mode, and to store the protocol packet read out of the current port in the PC mode; The PG state machine is used to write the protocol packet in the PGC data register into the PGC cache according to the configuration value of the PGC control register; The PC state machine is used to read the protocol packet sent by the core switch to the PGC cache into the PGC data register according to the configuration value of the PGC control register; The PGC cache is used to cache a protocol packet of a maximum length; The multiplexer is used to select a data path according to the configuration value of the PGC control register.

7. A method for testing the protocol consistency function of a network switching chip according to claim 6, characterized in that: The PGC control register includes five valid domains: TX_Start, RX_Done, SOP, EOP, Start_Port and End_Port; The TX_Start field is used to indicate whether the current port can send out the protocol packet written in the PGC cache in PG mode; The RX_Done field is used to indicate whether the current port can read the protocol packet in the PGC cache in PC mode; The SOP field is used to indicate whether the current port writes a protocol packet for the first time in PG mode, and indicates whether the current port reads a protocol packet for the first time in PC mode; The EOP field is used to indicate whether the current port has last written a protocol packet in PG mode, and whether the current port has last read a protocol packet in PC mode; The Start_Port field is used to indicate whether the current port's working mode is PG mode; The End_Port field is used to indicate whether the current port's working mode is PC mode.

8. A device for testing the protocol consistency function of a network switching chip, characterized in that: It includes a PGC module and a test module arranged inside each port of the network switching chip; wherein the PGC module is located in the core switching of the network switching chip and the sending path direction of each port; PGC refers to packet generation and packet capture; The PGC module is used to configure two ports of the network switching chip as a packet generation port and a packet capture port respectively; and is used to write a protocol packet at the packet generation port and send it out, and capture the protocol packet routed via the core switch at the packet capture port; The test module is used to determine the connectivity and protocol consistency of all ports on the routing path according to the protocol packets written at the packet generation port and the protocol packets captured at the packet capture port.

9. The device for testing the protocol consistency function of a network switching chip according to claim 8, characterized in that: The PGC module includes a configuration bus synchronization unit, a PGC register, a PG state machine, a PC state machine, a PGC cache and a multiplexer; wherein PG refers to packet generation, and PC refers to packet capture; The configuration bus synchronization unit is used to convert the AXI configuration bus to the local configuration bus; The PGC register includes a PGC control register and a PGC data register; the PGC controller is used to control the working mode of the current port, the working mode includes a normal data path mode and a PGC mode, and the PGC mode includes a PG mode and a PC mode; the PGC data register is used to store the protocol packet written to the current port in the PG mode, and to store the protocol packet read out of the current port in the PC mode; The PG state machine is used to write the protocol packet in the PGC data register into the PGC cache according to the configuration value of the PGC control register; The PC state machine is used to read the protocol packet sent by the core switch to the PGC cache into the PGC data register according to the configuration value of the PGC control register; The multiplexer is used to select a data path according to the configuration value of the PGC control register.

10. The device for testing the protocol consistency function of a network switching chip according to claim 9, characterized in that: The PGC control register includes five valid domains: TX_Start, RX_Done, SOP, EOP, Start_Port and End_Port; The TX_Start field is used to indicate whether the current port can send out the protocol packet written in the PGC cache in PG mode; The RX_Done field is used to indicate whether the current port can read the protocol packet in the PGC cache in PC mode; The SOP field is used to indicate whether the current port writes a protocol packet for the first time in PG mode, and indicates whether the current port reads a protocol packet for the first time in PC mode; The EOP field is used to indicate whether the current port has last written a protocol packet in PG mode, and whether the current port has last read a protocol packet in PC mode; The Start_Port field is used to indicate whether the current port's working mode is PG mode; The End_Port field is used to indicate whether the current port's working mode is PC mode.

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