Semiconductor memory device

Abstract

Semiconductor memory devices may be provided herein. The semiconductor memory device includes: a stacked body including interlayer insulating layers and selection lines disposed between the interlayer insulating layers; a core insulating layer that penetrates through the laminate; a semiconductor pattern extending along a sidewall of the core insulating layer and including an undoped region disposed between the selection line and the core insulating layer; a doped semiconductor pattern disposed between the semiconductor pattern and the interlayer insulating layer; and a gate insulating layer disposed between the semiconductor pattern and the selection line.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202110183764.9 (application date: February 10, 2021, invention name: semiconductor memory device and method for manufacturing the semiconductor memory device). Technical Field

[0002] Various embodiments of the present disclosure relate to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a three-dimensional (3D) semiconductor memory device and a method of manufacturing the 3D semiconductor memory device. Background Art

[0003] A semiconductor memory device includes memory cells capable of storing data. A three-dimensional (3D) semiconductor memory device includes memory cells arranged in three dimensions, thereby reducing the area occupied by the memory cells per unit substrate area.

[0004] In order to improve the integration degree of the 3D semiconductor memory device, the number of stacked memory cells may be increased. As the number of stacked memory cells increases, the operational reliability of the 3D semiconductor memory device may be degraded. Summary of the invention

[0005] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include: a stacked body including an interlayer insulating layer and a selection line disposed between the interlayer insulating layers; a core insulating layer penetrating the stacked body; a semiconductor pattern extending along a sidewall of the core insulating layer and including an undoped region disposed between the selection line and the core insulating layer; a doped semiconductor pattern disposed between the semiconductor pattern and the interlayer insulating layer; and a gate insulating layer disposed between the semiconductor pattern and the selection line.

[0006] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include: a first stack including a first interlayer insulating layer and a first conductive pattern alternately arranged in a stacking direction; a first channel structure penetrating the first stack; a second stack overlapping the first stack and including a second interlayer insulating layer stacked in the stacking direction and a second conductive pattern arranged between the second interlayer insulating layers; a second channel structure penetrating the second stack to contact the first channel structure; and a gate insulating layer arranged between the second channel structure and the second conductive pattern. Here, the second channel structure may include: a semiconductor pattern including an undoped region surrounded by a gate insulating layer and penetrating the second stack; and a plurality of doped semiconductor patterns arranged between the semiconductor pattern and the second interlayer insulating layer and separated from each other by the gate insulating layer.

[0007] Embodiments of the present disclosure may provide a method for manufacturing a semiconductor memory device. The method may include the following steps: forming interlayer insulating layers and sacrificial layers that are alternately stacked; forming a hole that passes through the interlayer insulating layers and the sacrificial layers; forming a doped semiconductor layer on a surface defining the hole; forming an undoped semiconductor layer on the doped semiconductor layer; opening a gate region by removing the sacrificial layer; forming a gate insulating layer by oxidizing a portion of the doped semiconductor layer through the gate region; and forming a conductive pattern that surrounds the gate insulating layer and fills the gate region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 2 is a circuit diagram showing a cell string according to an embodiment of the present disclosure.

[0010] Figure 3 is a perspective view schematically showing a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 4A and Figure 4B is a cross-sectional view showing a channel structure according to an embodiment of the present disclosure.

[0012] Figure 5A and Figure 5B is a perspective view schematically showing a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 6 is a plan view showing a lower stacked body according to an embodiment of the present disclosure.

[0014] Fig. 7A, Figure 7B and Figure 7C is a cross-sectional view showing a step of forming a lower stack according to an embodiment of the present disclosure.

[0015] Figure 8 is a plan view showing an upper stacked body according to an embodiment of the present disclosure.

[0016] Fig. 9A , Fig. 9B , Fig. 9C , Fig.9D and Fig.9E is a cross-sectional view showing a step of forming an upper stacked body according to an embodiment of the present disclosure.

[0017] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig. 10E and Fig.10F is an enlarged cross-sectional view showing a step of forming an upper stack according to an embodiment of the present disclosure.

[0018] Fig.11 is a plan view showing a bit line according to an embodiment of the present disclosure.

[0019] Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D is an enlarged cross-sectional view showing a step of forming an upper stack according to an embodiment of the present disclosure.

[0020] Fig.13A and Fig. 13B is a cross-sectional view showing a channel structure according to an embodiment of the present disclosure.

[0021] Fig.14 is a cross-sectional view illustrating a step of forming a first channel structure according to an embodiment of the present disclosure.

[0022] Fig.15 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.

[0023] Fig.16 is a block diagram showing a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] For the purpose of describing the embodiments of the concept according to the present disclosure, the specific structural description or functional description disclosed herein is only illustrative. The embodiments of the concept according to the present disclosure can be implemented in various forms and should not be interpreted as limited to the specific embodiments set forth herein.

[0025] Hereinafter, the terms "first" and "second" are used to distinguish one component from another component. Therefore, the components should not be limited by these terms. For example, without departing from the scope of the concept of the present disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component.

[0026] Various embodiments of the present disclosure relate to a semiconductor memory device capable of improving operation reliability and a method of manufacturing the semiconductor memory device.

[0027] Figure 1 is a block diagram showing a semiconductor memory device 10 according to an embodiment of the present disclosure.

[0028] Reference Figure 1 , the semiconductor memory device 10 may include a peripheral circuit PC and a memory cell array 20 .

[0029] The peripheral circuit PC may control a program operation of storing data in the memory cell array 20 , a read operation of outputting the data stored in the memory cell array 20 , and an erase operation of erasing the data stored in the memory cell array 20 .

[0030] In an implementation, the peripheral circuit PC may include a voltage generator 31 , a row decoder 33 , a control circuit 35 , and a page buffer group 37 .

[0031] The memory cell array 20 may include a plurality of memory blocks. The memory cell array 20 may be coupled to a row decoder 33 through word lines WL, and may be coupled to a page buffer group 37 through bit lines BL.

[0032] The control circuit 35 may control the peripheral circuit PC in response to the command CMD and the address ADD.

[0033] The voltage generator 31 may generate various operating voltages such as a pre-erase voltage, an erase voltage, a ground voltage, a program voltage, a verification voltage, a pass voltage, and a read voltage for program operations, read operations, and erase operations under the control of the control circuit 35 .

[0034] The row decoder 33 may select a memory block under the control of the control circuit 35. The row decoder 33 may apply an operating voltage to a word line WL coupled to the selected memory block.

[0035] The page buffer group 37 may be coupled to the memory cell array 20 through the bit line BL. The page buffer group 37 may temporarily store data received from an input / output circuit (not shown) under the control of the control circuit 35 during a program operation. The page buffer group 37 may sense a voltage or current of the bit line BL under the control of the control circuit 35 during a read operation or a verification operation. The page buffer group 37 may select the bit line BL under the control of the control circuit 35.

[0036] Each memory block in the memory cell array 20 may include a plurality of cell strings.

[0037] Figure 2 is a circuit diagram showing a cell string CS according to an embodiment of the present disclosure.

[0038] Reference Figure 2 , the cell string CS may be coupled to the source layer SL and the bit line BL. The cell string CS may include a plurality of memory cells MC1 to MCn, one or more source selection transistors SSTa and SSTb, and one or more drain selection transistors DSTa and DSTb.

[0039] The plurality of memory cells MC1 to MCn may be coupled to one another in series. Gates of the plurality of memory cells MC1 to MCn may be respectively coupled to a plurality of word lines WL1 to WLn stacked to be spaced apart from one another.

[0040] One or more source select transistors SSTa and SSTb may control the electrical connection between the cell string CS and the source layer SL. In an embodiment, the cell string CS may include one source select transistor SSTa disposed between the source layer SL and the plurality of memory cells MC1 to MCn. In an embodiment, the cell string CS may include two or more source select transistors SSTa and SSTb disposed between the source layer SL and the plurality of memory cells MC1 to MCn and connected in series with each other. The gates of the source select transistors SSTa and SSTb may be connected to source select lines SSLa and SSLb, respectively.

[0041] One or more drain select transistors DSTa and DSTb may control the electrical connection between the cell string CS and the bit line BL. In an embodiment, the cell string CS may include one drain select transistor DSTa disposed between the bit line BL and the plurality of memory cells MC1 to MCn. In an embodiment, the cell string CS may include two or more drain select transistors DSTa and DSTb disposed between the bit line BL and the plurality of memory cells MC1 to MCn and connected in series with each other. The gates of the drain select transistors DSTa and DSTb may be connected to the drain select lines DSLa and DSLb, respectively.

[0042] The source selection lines SSLa and SSLb, the plurality of word lines WL1 to WLn, and the drain selection lines DSLa and DSLb may be implemented using conductive patterns stacked to be spaced apart from each other.

[0043] An erase operation of a semiconductor memory device may be performed using a gate induced drain leakage (GIDL) current. The GIDL current may be generated due to a difference between an erase voltage applied to a bit line BL and a gate voltage applied to each of drain select lines DSLa and DSLb.

[0044] Figure 3 is a perspective view schematically showing a semiconductor memory device according to an embodiment of the present disclosure.

[0045] Reference Figure 3 , the semiconductor memory device may include a first stacked body ST1 surrounding first channel structures CH1A and CH1B, second channel structures CH2A and CH2B overlapping the first channel structures CH1A and CH1B, respectively, and a plurality of second stacked bodies ST2 overlapping the first stacked body ST1 and spaced apart from each other at the same level.

[0046] The first stack body ST1 may include first interlayer insulating layers ILD1 and first conductive patterns CP1 alternately disposed in a stacking direction. The first conductive patterns CP1 may be used as Figure 2 Source select lines SSLa and SSLb and a plurality of word lines WL1 to WLn are shown.

[0047] The first channel structures CH1A and CH1B may penetrate the first stack body ST1. Each of the first channel structures CH1A and CH1B may include a first core insulating layer CO1 and a first channel layer CL1. The first core insulating layer CO1 may penetrate the first stack body ST1, and the first channel layer CL1 may surround a sidewall of the first core insulating layer CO1. In an embodiment, the first channel layer CL1 may include an undoped semiconductor layer. In an embodiment, the undoped semiconductor layer may include undoped silicon.

[0048] A sidewall of each of the first channel structures CH1A and CH1B may be surrounded by the memory layer ML. The memory layer ML may be disposed between each of the first channel structures CH1A and CH1B and the first stacked body ST1.

[0049] The first stack body ST1 and the first channel structures CH1A and CH1B may be covered with a second interlayer insulating layer ILD2.

[0050] Each second stack body ST2 may include second conductive patterns CP2 and third interlayer insulating layers ILD3 alternately arranged in the stacking direction. The second conductive pattern CP2 may be arranged between the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3 adjacent to the corresponding second conductive pattern CP2 in the stacking direction and between the third interlayer insulating layer ILD3 adjacent to the corresponding second conductive pattern CP2 in the stacking direction.

[0051] The second stacked bodies ST2 may be separated from each other by the isolation insulating layer 30. The second stacked body ST2 may be used as a selection stacked body. In an embodiment, the second conductive pattern CP2 may be used as Figure 2 Drain select lines DSLa and DSLb are shown.

[0052] The second channel structures CH2A and CH2B may penetrate the second stack body ST2 and the second interlayer insulating layer ILD2 to contact the first channel structures CH1A and CH1B, respectively. Each of the second channel structures CH2A and CH2B may penetrate a portion of the first core insulating layer CO1 and may contact the first channel layer CL1.

[0053] Each of the second channel structures CH2A and CH2B may include a second core insulation layer CO2, a capping pattern CAP, and a second channel layer CL2. The second core insulation layer CO2 may penetrate the corresponding second stack ST2. The second core insulation layer CO2 may extend to penetrate the corresponding second interlayer insulation layer ILD2. The capping pattern CAP may overlap the corresponding second core insulation layer CO2. The capping pattern CAP may overlap the first channel structure CH1A or CH1B with the second core insulation layer CO2 interposed therebetween. The second channel layer CL2 may extend along the sidewall and bottom surface of the second core insulation layer CO2. The second channel layer CL2 may contact the corresponding first channel layer CL1. The second channel layer CL2 as a selective channel layer may include a dopant to stably induce a GIDL current during an erase operation. In an embodiment, the second channel layer CL2 may include an n-type dopant.

[0054] The corresponding gate insulating layer GI may be disposed between the second channel structures CH2A and CH2B and the second conductive pattern CP2. The gate insulating layer GI may extend in a ring shape to respectively surround partial regions of the sidewalls of the second channel layer CL2 facing the second conductive pattern CP2.

[0055] The second channel structures CH2A and CH2B may include a first group of second channel structures CH2A and a second group of second channel structures CH2B. An isolation insulating layer 30 may be disposed between the first group of second channel structures CH2A and the second group of second channel structures CH2B.

[0056] The first channel structures CH1A and CH1B may include a first group of first channel structures CH1A and a second group of first channel structures CH1B. The first group of first channel structures CH1A may be coupled to the first group of second channel structures CH2A, respectively. The second group of first channel structures CH1B may be coupled to the second group of second channel structures CH2B, respectively.

[0057] The first and second channel structures CH1A and CH1B of the first and second groups may be controlled by the same first conductive pattern CP1. The second conductive pattern CP2 for controlling the second channel structure CH2A of the first group and the second conductive pattern CP2 for controlling the second channel structure CH2B of the second group may be separated from each other by the isolation insulating layer 30.

[0058] Figure 4A and Figure 4B is a cross-sectional view showing a channel structure according to an embodiment of the present disclosure. Figure 4A and Figure 4B yes Figure 3 An enlarged cross-sectional view of region A is shown.

[0059] Reference Figure 4A and Figure 4B , the memory layer ML may include a tunnel insulating layer TI, a data storage layer DS, and a first blocking insulating layer BI1.

[0060] The tunnel insulating layer TI may surround the sidewall of the first channel layer CL1. The tunnel insulating layer TI may include an insulating material that enables charge tunneling. In an implementation, the tunnel insulating layer TI may include a silicon oxide layer.

[0061] The data storage layer DS may surround the sidewall of the tunnel insulating layer TI. The data storage layer DS may include a material layer capable of storing data. In an embodiment, the data storage layer DS may be formed of a material layer capable of storing data changed using Fowler-Nordheim tunneling (FN tunneling). For this operation, the data storage layer DS may be formed of a nitride layer capable of capturing charges. The present disclosure is not limited thereto, and the data storage layer DS may include a phase change material, nanodots, etc.

[0062] The first blocking insulating layer BI1 may surround a sidewall of the data storage layer DS. The first blocking insulating layer BI1 may include an oxide layer.

[0063] The first conductive pattern CP1 may surround the memory layer ML between the first interlayer insulating layers ILD1 adjacent to the first conductive pattern CP1 in the stacking direction. The second blocking insulating layer BI2 may be formed between the first conductive pattern CP1 and the first blocking insulating layer BI1. The second blocking insulating layer BI2 may include an insulating material having a dielectric constant higher than that of the first blocking insulating layer BI1. In an embodiment, the second blocking insulating layer BI2 may include a metal oxide layer. In an embodiment, the metal oxide layer may include an aluminum oxide layer. The second blocking insulating layer BI2 may extend to a space between the first conductive pattern CP1 and the first interlayer insulating layer ILD1.

[0064] Reference Figure 4A , the second channel layer CL2A may include a semiconductor pattern SE and a doped semiconductor pattern DP. The semiconductor pattern SE may include an undoped area UDA and a doped area DA.

[0065] Reference Figure 4B , the second channel layer CL2B may include a semiconductor pattern SE, a barrier pattern BR, and a doped semiconductor pattern DP. The semiconductor pattern SE may include a doped area DA and an undoped area UDA.

[0066] Reference Figure 4A and Figure 4B , the doped semiconductor pattern DP may be disposed between the second interlayer insulating layer ILD2 and the semiconductor pattern SE and between the third interlayer insulating layer ILD3 and the semiconductor pattern SE. The doped semiconductor patterns DP may be coupled to each other via the semiconductor pattern SE.

[0067] Because the doped semiconductor pattern DP can reduce the channel resistance of the second channel layer CL2A or CL2B, the channel current of the second channel layer CL2A or CL2B can be increased due to the doped semiconductor pattern DP. Due to the doped semiconductor pattern DP, the GIDL current can be stably ensured during the erase operation of the semiconductor memory device. In an embodiment, the doped semiconductor pattern DP may include an n-type dopant. In an embodiment, the doped semiconductor pattern DP may include n-type silicon.

[0068] The doped semiconductor pattern DP may include a first doped semiconductor pattern DP1 adjacent to the first channel layer CL1. The first doped semiconductor pattern DP1 may extend to Figure 3 A space between the first channel structure CH1A or CH1B and the semiconductor pattern SE is shown. The doped semiconductor pattern DP may include a second doped semiconductor pattern DP2 extending to surround a sidewall of the capping pattern CAP.

[0069] The capping pattern CAP may include a conductive material. The capping pattern CAP may include a dopant for the junction overlap region. In an embodiment, the capping pattern CAP may include a semiconductor material doped with the same type of dopant as the doped semiconductor pattern DP. In an embodiment, the capping pattern CAP may include n-type doped silicon.

[0070] The doped semiconductor patterns DP may be separated from each other by the gate insulating layer GI.

[0071] The gate insulating layer GI may be disposed between the second conductive pattern CP2 and the semiconductor pattern SE. The gate insulating layer GI may overlap the doped semiconductor pattern DP. Each gate insulating layer GI may be disposed between the doped semiconductor patterns DP adjacent to the corresponding gate insulating layer GI in the stacking direction of the third interlayer insulating layer ILD3 and the second conductive pattern CP2. In an embodiment, the gate insulating layer GI may include silicon oxide.

[0072] The semiconductor pattern SE may extend along the sidewall and bottom surface BS of the second core insulation layer CO2. The bottom surface BS of the second core insulation layer CO2 may face the first core insulation layer CO1. The semiconductor pattern SE may extend to surround the sidewall of the capping pattern CAP. In an embodiment, the semiconductor pattern SE may include silicon. The semiconductor pattern SE may include at least one undoped area UDA.

[0073] Reference Figure 4A , the semiconductor pattern SE may include an undoped area UDA disposed between the second core insulating layer CO2 and the second conductive pattern CP2. The undoped areas UDA may be surrounded by the gate insulating layer GI, respectively. In an embodiment, the semiconductor pattern SE may include a doped area DA disposed between the second core insulating layer CO2 and the doped semiconductor pattern DP. A partial area of ​​the sidewall of the semiconductor pattern SE surrounding the cover pattern CAP may be defined as a doped area DA. The doped area DA may include dopants diffused from the doped semiconductor pattern DP and the cover pattern CAP. According to an embodiment, the dotted line indicated in the semiconductor pattern SE represents a boundary between the doped area DA and the undoped area UDA.

[0074] Reference Figure 4B The barrier pattern BR may be disposed between the semiconductor pattern SE and the doped semiconductor pattern DP. The barrier pattern BR may extend along the sidewall and bottom surface of the semiconductor pattern SE. In an embodiment, the barrier pattern BR may include an oxide layer.

[0075] The doped semiconductor pattern DP may be spaced apart from the semiconductor pattern SE by the barrier pattern BR. The thickness of the barrier pattern BR may be controlled so that each doped semiconductor pattern DP is electrically coupled to the semiconductor pattern SE. In other words, the thickness of the barrier pattern BR may be controlled so that the flow of current in the second channel layer CL2B is not blocked. In an embodiment, the thickness Tb of the barrier pattern BR may be formed to be smaller than the thickness Td of each doped semiconductor pattern DP, the thickness Ts of the semiconductor pattern SE, and the thickness Tg of the gate insulating layer GI. In an embodiment, the barrier pattern BR may be formed to or less thickness.

[0076] The phenomenon that dopants diffuse from the inside of the doped semiconductor pattern DP into the semiconductor pattern SE can be prevented by the barrier pattern BR. The undoped area UDA of the semiconductor pattern SE may be surrounded by the gate insulating layer GI and the second interlayer insulating layer ILD2, and may be surrounded by the third interlayer insulating layer ILD3 between the second conductive patterns CP2. The top of the semiconductor pattern SE may be in contact with the capping pattern CAP. The semiconductor pattern SE may include a doped area DA surrounding the sidewall of the capping pattern CAP. The doped area DA may include dopants diffused from the capping pattern CAP. According to an embodiment, the dotted line indicated in the semiconductor pattern SE represents a boundary between the doped area DA and the undoped area UDA.

[0077] Through the above reference Figure 4A and Figure 4B The described undoped area UDA may ensure the cut-off characteristic of the selection transistor using the second channel layer CL2A or CL2B as a channel region.

[0078] Figure 5A and Figure 5B is a perspective view schematically showing a semiconductor memory device according to an embodiment of the present disclosure.

[0079] Reference Figure 5A and Figure 5B , each semiconductor memory device may include a peripheral circuit PC disposed on a substrate SUB, first stacked bodies ST1A and ST1B, second stacked bodies ST2A, ST2B, ST2C, and ST2D, a bit line BL, and a source layer SL.

[0080] The substrate SUB may extend in a first direction X and a second direction Y. The first direction X may be a direction in which an X-axis in an XYZ coordinate system faces, and the second direction Y may be a direction in which a Y-axis in the XYZ coordinate system faces.

[0081] The peripheral circuit PC may include Figure 1 A voltage generator 31, a row decoder 33, a control circuit 35 and a page buffer group 37 are shown.

[0082] The first stacks ST1A and ST1B may be separated from each other by the first slits S1. Each of the first stacks ST1A and ST1B may include one or more source selection lines SSLa and SSLb and a plurality of word lines WL1 to WLn stacked to be spaced apart from each other in the third direction Z. Figure 3 The illustrated first conductive pattern CP1 implements source selection lines SSLa and SSLb and a plurality of word lines WL1 to WLn.

[0083] The second stacked bodies ST2A, ST2B, ST2C and ST2D can be separated from each other at the same level by the second slit S2. In the third direction Z, the stacking height of each of the second stacked bodies ST2A, ST2B, ST2C and ST2D can be formed to be less than the stacking height of each of the first stacked bodies ST1A and ST1B. Therefore, the length of each second slit S2 in the third direction Z can be formed to be shorter than the length of the first slit S1. Although the width of the second slit S2 is controlled to be narrow, the second slit S2 has a relatively short length, so the second slit S2 can be stably formed. In an embodiment, the width W2 of each second slit S2 can be formed to be narrower than the width W1 of the first slit S1.

[0084] Each of the first slit S1 and the second slit S2 may extend in a straight line shape, a zigzag shape, or a wave shape. The width of each of the first slit S1 and the second slit S2 may be changed in various forms according to design rules.

[0085] In an embodiment, two second stacks ST2A and ST2B separated at the same level may overlap with the first stack ST1A, and two second stacks ST2C and ST2D separated at the same level may overlap with the first stack ST1B. Embodiments of the present disclosure are not limited thereto. In an embodiment, three or more second stacks separated at the same level may overlap with each of the first stacks ST1A and ST1B.

[0086] Each of the second stacked bodies ST2A, ST2B, ST2C, and ST2D may include two or more drain selection lines DSLa and DSLb arranged to be spaced apart from each other in the third direction Z. Figure 3 The second conductive pattern CP2 is shown to implement the drain selection lines DSLa and DSLb.

[0087] The source layer SL can be the same as that in the above reference Figure 3 The first channel layer CL1 described above is in contact with the Figure 3The described first channel layer CL1 may penetrate the first stacked bodies ST1A and ST1B, respectively. The source layer SL may include a doped semiconductor layer. In an embodiment, the source layer SL may include an n-type doped silicon layer.

[0088] The bit line BL may be electrically coupled to the Figure 3 Although not shown in the drawings, the capping pattern CAP and the second channel layer CL2 may be electrically coupled to the bit line BL via a contact plug. The bit line BL may be formed of various conductive materials.

[0089] The first stacked bodies ST1A and ST2B and the second stacked bodies ST2A, ST2B, ST2C, and ST2D may be disposed between the source layer SL and the bit line BL. The source layer SL may overlap with the second stacked bodies ST2A, ST2B, ST2C, and ST2D, and the first stacked bodies ST1A and ST2B are interposed between the source layer SL and the second stacked bodies ST2A, ST2B, ST2C, and ST2D. The bit line BL may overlap with the first stacked bodies ST1A and ST1B, and the second stacked bodies ST2A, ST2B, ST2C, and ST2D are interposed between the bit line BL and the first stacked bodies ST1A and ST1B.

[0090] Although not shown in the drawings, the bit lines BL, the source layer SL, the source selection lines SSLa and SSLb, the plurality of word lines WL1 to WLn and the drain selection lines DSLa and DSLb may be electrically coupled to the peripheral circuit PC through various types of interconnections.

[0091] The plurality of word lines WL1 to WLn may overlap the source select lines SSLa and SSLb. The drain select lines DSLa and DSLb may overlap the source select lines SSLa and SSLb with the plurality of word lines WL1 to WLn interposed therebetween.

[0092] Reference Figure 5A In an embodiment, the peripheral circuit PC may overlap the second stack bodies ST2A, ST2B, ST2C, and ST2D, with the source layer SL and the first stack bodies ST1A and ST1B interposed between the peripheral circuit PC and the second stack bodies ST2A, ST2B, ST2C, and ST2D.

[0093] Reference Figure 5B As an embodiment, the peripheral circuit PC may overlap the first stack bodies ST1A and ST1B, while the bit lines BL and the second stack bodies ST2A, ST2B, ST2C, and ST2D are interposed between the peripheral circuit PC and the first stack bodies ST1A and ST1B.

[0094] Figure 6 is a plan view showing a lower stacked body 150 according to an embodiment of the present disclosure.

[0095] Reference Figure 6 , the lower stack 150 may be penetrated by the plurality of first channel structures 130A and 130B. The lower stack 150 may remain in the region divided by the first slits 141. A sidewall of each of the first channel structures 130A and 130B may be surrounded by the memory layer 120.

[0096] The first channel structures 130A and 130B may be arranged in multiple columns and multiple rows. In an embodiment, the first channel structures 130A and 130B may be arranged in a zigzag shape. The embodiments of the present disclosure are not limited thereto. In an embodiment, the first channel structures 130A and 130B may be arranged parallel to each other in the row direction and the column direction.

[0097] The first channel structures 130A and 130B may be divided into a plurality of groups. In an implementation, the first channel structures 130A and 130B may include a first group of first channel structures 130A and a second group of first channel structures 130B.

[0098] Fig. 7A , Figure 7B and Figure 7C is a cross-sectional view illustrating a step of forming the lower stacked body 150 according to an embodiment of the present disclosure. Fig. 7A , Figure 7B and Figure 7C It is along Figure 6 sectional views of the various processing steps taken along line II'.

[0099] Reference Fig. 7A The step of forming a lower stack may include a step of forming a first preliminary stack 110, a step of forming a first hole 115 passing through the first preliminary stack 110, a step of forming a memory layer 120 on corresponding sidewalls of the first hole 115, and a step of forming first channel structures 130A and 130B filling a central area of ​​the first hole 115 on a surface of the memory layer 120.

[0100] The first preliminary stack 110 may be formed on the source layer or on the substrate. The first preliminary stack 110 may include lower interlayer insulating layers 101 and first sacrificial layers 103 that are alternately stacked. Each first sacrificial layer 103 may include a material having an etching selectivity to the lower interlayer insulating layer 101. In an embodiment, the lower interlayer insulating layer 101 may include silicon oxide, and the first sacrificial layer 103 may include silicon nitride.

[0101] The first hole 115 may be formed by removing a partial region of the first preliminary stack 110 through an etching process using a photoresist pattern (not shown) formed through a photolithography process as an etching barrier. After the first hole 115 has been formed, the photoresist pattern may be removed.

[0102] The step of forming the memory layer 120 may include the steps of sequentially forming a first blocking insulating layer 121, a data storage layer 123, and a tunnel insulating layer 125. The first blocking insulating layer 121, the data storage layer 123, and the tunnel insulating layer 125 may extend along a sidewall of each first hole 115.

[0103] The step of forming the first channel structures 130A and 130B may include the steps of forming respective channel layers 131 on the memory layer 120 , and filling respective central regions of the first holes 115 opened by the channel layers 131 with the first core insulating layer 133 .

[0104] A portion of each of the first blocking insulating layer 121, the data storage layer 123, the tunnel insulating layer 125, the channel layer 131, and the first core insulating layer 133 may be removed by a planarization process. As a result, the first blocking insulating layer 121, the data storage layer 123, and the tunnel insulating layer 125 may remain in the corresponding first hole 115 as the memory layer 120. The channel layer 131 and the first core insulating layer 133 may be separated into first channel structures 130A and 130B.

[0105] Each channel layer 131 may include an undoped semiconductor layer. In an implementation, the channel layer 131 may include undoped silicon.

[0106] Reference Figure 7B , you can Fig. 7A A first upper interlayer insulating layer 137 covering the first channel structures 130A and 130B is formed on the first preliminary stack 110 as shown.

[0107] The step of forming the lower stack may include forming Figure 6 The steps of the first slit 141 and the selective removal of the first slit 141 are shown. Fig. 7A The step of forming the first sacrificial layer 103 is shown. As a result, the first gate region 143 between the lower interlayer insulating layers 101 may be opened.

[0108] Reference Figure 7C The step of forming the lower stack 150 may include: Figure 7BThe steps of forming a second blocking insulating layer 147 on the corresponding surface of the first gate region 143 and filling the first gate region 143 opened by the second blocking insulating layer 147 with a first conductive pattern 149 are shown. The first conductive pattern 149 may extend to surround the first group of first channel structures 130A and the second group of first channel structures 130B.

[0109] The first conductive pattern 149 may be formed of various types of conductive materials. In an embodiment, each first conductive pattern 149 may include each of a metal silicide layer, a metal layer, and a doped silicon layer alone, or may include at least two of the metal silicide layer, the metal layer, and the doped silicon layer. Although not shown in the drawings, a metal barrier layer may be disposed between each first conductive pattern 149 and the corresponding second blocking insulating layer 147. The metal barrier layer may extend to a space between each first conductive pattern 149 and the corresponding memory layer 120.

[0110] Figure 8 180A and 180B are plan views showing upper stacked bodies 180A and 180B according to an embodiment of the present disclosure.

[0111] Reference Figure 8 The upper stacks 180A and 180B may include a first upper stack 180A overlapping the first channel structure 130A of the first group and a second upper stack 180B overlapping the first channel structure 130B of the second group. The first upper stack 180A and the second upper stack 180B may be separated from each other by a second slit 183 .

[0112] The first upper stack 180A may extend to surround the second channel structure 170A of the first group, and the second upper stack 180B may extend to surround the second channel structure 170B of the second group. The second channel structures 170A of the first group may overlap with the first channel structures 130A of the first group, respectively, and the second channel structures 170B of the second group may overlap with the first channel structures 130B of the second group, respectively.

[0113] In order to ensure the arrangement space of the second slits 183, the interval WB between the second channel structures 170A of the first group and the second channel structures 170B of the second group adjacent to each other may be formed to be larger than Figure 6 The interval WA between the first channel structure 130A of the first group and the first channel structure 130B of the second group adjacent to each other is shown. In an embodiment, in order to ensure the interval WB between the second channel structure 170A of the first group and the second channel structure 170B of the second group, the diameter of each of the second channel structures 170A and 170B may be formed to be smaller than the diameter of each of the first channel structures 130A and 130B.

[0114] Fig. 9A , Fig. 9B , Fig. 9C , Fig.9D and Fig.9E is a cross-sectional view showing a step of forming upper stacked bodies 180A and 180B according to an embodiment of the present disclosure. Fig. 9A , Fig. 9B , Fig. 9C , Fig.9D and Fig.9E It is along Figure 8 A cross-sectional view taken along line II'.

[0115] Reference Fig. 9A , the step of forming the upper stack may include the step of forming the second preliminary stack 160 and the step of forming the second hole 167 through the second preliminary stack 160. The second preliminary stack 160 may overlap the lower stack 150 extending to surround the first channel structure 130A of the first group and the first channel structure 130B of the second group. The second hole 167 may overlap the first channel structure 130A of the first group and the first channel structure 130B of the second group. The second hole 167 may pass through the first upper interlayer insulating layer 137 to expose the first channel structure 130A of the first group and the first channel structure 130B of the second group.

[0116] The second preliminary stack 160 may include second sacrificial layers 161 and second upper interlayer insulating layers 163 alternately stacked on the first upper interlayer insulating layers 137. Each second sacrificial layer 161 may include a material having an etching selectivity to the first upper interlayer insulating layer 137 and the second upper interlayer insulating layer 163. In an embodiment, the first upper interlayer insulating layer 137 and the second upper interlayer insulating layer 163 may include silicon oxide, and the second sacrificial layer 161 may include silicon nitride.

[0117] The step of forming the second hole 167 may include the steps of forming a photoresist pattern 165 by a photolithography process, and removing a partial region of the second preliminary stack 160 and a partial region of the first upper interlayer insulating layer 137 by an etching process using the photoresist pattern 165 as an etching barrier. The second hole 167 may expose the corresponding channel layers 131 in the first channel structure 130A of the first group and the first channel structure 130B of the second group.

[0118] The total stacking height H2 of the first upper interlayer insulating layer 137 and the second preliminary stack 160 is lower than the stacking height H1 of the lower stack 150. Therefore, even if each second hole 167 is formed at a depth smaller than that of the first hole 115, the channel layer 131 may be exposed through the second hole 167. The upper diameter DB of each second hole 167 formed at a small depth may be controlled to be narrow. In an embodiment, the upper diameter DB of each second hole 167 may be formed to be narrower than the upper diameter DA of each first hole 115.

[0119] The photoresist pattern 165 may be removed after the second hole 167 has been formed.

[0120] Reference Fig. 9B The step of forming the upper stack may include the step of forming a preliminary channel structure 170 in the second hole 167. Each preliminary channel structure 170 may include a preliminary doped semiconductor pattern 171, an undoped semiconductor pattern 175U, a second core insulating layer 177, and a capping pattern 179.

[0121] The preliminary doped semiconductor pattern 171 may be formed on a surface defining each second hole 167. The preliminary doped semiconductor pattern 171 may be in contact with the corresponding channel layer 131.

[0122] The undoped semiconductor pattern 175U may be formed on the preliminarily doped semiconductor pattern 171 and may extend along a surface defining each second hole 167. The second core insulating layer 177 and the capping pattern 179 may fill a central region of the corresponding second hole 167 exposed by the undoped semiconductor pattern 175U. The capping pattern 179 may overlap with the corresponding first core insulating layer 133 with the second core insulating layer 177 interposed therebetween.

[0123] Reference Fig. 9C , a third upper interlayer insulating layer 181 may be formed on the second preliminary stack 160 . The third upper interlayer insulating layer 181 may extend to cover the preliminary channel structure 170 .

[0124] The step of forming the upper stack may include the step of forming a second slit 183 passing through the third upper interlayer insulating layer 181 and the second preliminary stack 160. The second slit 183 may be formed to a depth at which the second sacrificial layer 161B in the lowermost layer among the second sacrificial layers 161 is exposed. In this way, the width of the second slit 183 may be minimized.

[0125] Reference Fig.9D The step of forming the upper stack may include selectively removing the Fig. 9CThe second sacrificial layer 161 is formed in the step shown. Therefore, the second gate region 185 may be opened between the first upper interlayer insulating layer 137 and the second upper interlayer insulating layer 163 adjacent to each other and between the second upper interlayer insulating layers 163 adjacent to each other.

[0126] The preliminary doped semiconductor pattern 171 of each preliminary channel structure 170 may be exposed through the second gate region 185 .

[0127] Reference Fig.9E , can be achieved by passing through Fig.9D The second gate region 185 shown in FIG. Fig.9D A portion of the preliminary doped semiconductor pattern 171 shown in FIG. 1 is oxidized to form a gate insulating layer 187. An unoxidized region of the preliminary doped semiconductor pattern 171 may remain as a doped semiconductor pattern 171P.

[0128] Thereafter, the dopant of the doped semiconductor pattern 171P and the capping pattern 179 may be diffused into the Fig.9D The semiconductor patterns 175 each including an undoped region and a doped region are formed by using the undoped semiconductor pattern 175U shown in FIG. In this way, a first group of second channel structures 170A and a second group of second channel structures 170B may be defined.

[0129] Each of the second channel structures 170A of the first group and 170B of the second group may include a doped semiconductor pattern 171P, a semiconductor pattern 175 including an undoped region surrounded by a gate insulating layer 187 , a second core insulating layer 177 , and a capping pattern 179 .

[0130] The step of forming the upper stacks 180A and 180B may include filling the second conductive pattern 189 with Fig.9D 185. Each second conductive pattern 189 may include each of a metal silicide layer, a metal layer, and a doped silicon layer alone, or may include at least two of the metal silicide layer, the metal layer, and the doped silicon layer. The second conductive pattern 189 may extend to surround the gate insulating layer 187.

[0131] Then, Fig.9D The second slit 183 shown in FIG. 1 may be filled with an insulating material 191 .

[0132] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig. 10E and Fig.10F is an enlarged cross-sectional view showing a step of forming an upper stack according to an embodiment of the present disclosure.

[0133] Fig. 10A yes Fig. 9A An enlarged cross-sectional view of region B is shown.

[0134] Reference Fig. 10A The second hole 167 may pass through the first upper interlayer insulating layer 137 overlapping the channel layer 131 , the second sacrificial layer 161 , and the second upper interlayer insulating layer 163 . The second hole 167 may extend to the inside of the first hole 115 .

[0135] Fig. 10B and Fig. 10C is an enlarged cross-sectional view illustrating an embodiment of a step of forming a preliminary channel structure 170 .

[0136] Reference Fig. 10B The step of forming the preliminary channel structure may include the step of forming a doped semiconductor layer 171L on a surface defining the second hole 167. In an implementation, the doped semiconductor layer 171L may include an n-type silicon layer.

[0137] The doped semiconductor layer 171L may be deposited using a silicon source gas and an impurity gas including a dopant. Fig. 9A As described, the depth of the second hole 167 is formed to be relatively small, and thus it is easy to uniformly form the doped semiconductor layer 171L along the surface defining the second hole 167 .

[0138] Reference Fig. 10C , the undoped semiconductor layer is deposited on Fig. 10B , and then the central area of ​​the second hole 167 may be filled with the second core insulating layer 177. Next, the top of the second hole 167 may be opened by removing a portion of the second core insulating layer 177, and the opened top of the second hole 167 may be filled with a capping layer.

[0139] In an embodiment, the undoped semiconductor layer may include undoped silicon. In an embodiment, the capping layer may include a semiconductor material doped with the same type of dopant as the doped semiconductor layer 171L. In an embodiment, the capping layer may include n-type doped silicon.

[0140] A planarization process can be used to remove Fig. 10B 171L. A planarization process may be performed to expose the top surface of the second upper interlayer insulating layer 163. In this way, the capping layer may remain as a capping pattern 179, the undoped semiconductor layer may remain as an undoped semiconductor pattern 175U, and the doped semiconductor layer 171L may remain as a preliminary doped semiconductor pattern 171.

[0141] Fig. 10D and Fig. 10E 1 is an enlarged cross-sectional view illustrating an embodiment of a step of forming a gate insulating layer 187 and an embodiment of a step of forming a semiconductor pattern 175 .

[0142] Reference Fig. 10D , can be found through the above reference Fig. 9C and Fig.9D The described process leaves the second gate region 185 open.

[0143] Then, the second gate region 185 may be removed Fig. 10C A portion of the preliminary doped semiconductor pattern 171 is shown in FIG. In this manner, a preliminary doped semiconductor pattern 171 ′ having a sidewall formed with a trench GV may be defined.

[0144] Reference Fig. 10E , can be achieved by preliminarily doping the semiconductor pattern 171' via Fig. 10D The surface exposed by the trench GV shown in FIG. 1 is oxidized to form a gate insulating layer 187. An unoxidized region of the preliminary doped semiconductor pattern 171' may remain as a doped semiconductor pattern 171P.

[0145] Even if the thickness of the gate insulating layer 187 is increased during the above oxidation process, Fig. 10D The trench GV shown is used to reduce the space dedicated to the gate insulating layer 187 within the second gate region 185 .

[0146] The oxidation process may be controlled so that the doped semiconductor pattern 171P remains between the first upper interlayer insulating layer 137 and the Fig. 10D The undoped semiconductor pattern 175U shown in FIG. 1 and the second upper interlayer insulating layer 163 and Fig. 10D The oxidation process may be controlled so that the gate insulating layer 187 is Fig. 10D In this way, the doped semiconductor patterns 171P may be separated from each other by the gate insulating layer 187 .

[0147] After forming the gate insulating layer 187, the dopant doping the semiconductor pattern 171P and the dopant doping the capping pattern 179 may be diffused into the Fig. 10D As a result, a semiconductor pattern 175 including a doped region ARd and an undoped region ARu may be defined. The doped region ARd may contact the doped semiconductor pattern 171P and the capping pattern 179, respectively, and the undoped region ARu may be surrounded by a gate insulating layer 187, respectively.

[0148] Fig.10Fis an enlarged cross-sectional view showing the second conductive pattern 189 .

[0149] Reference Fig.10F , Fig. 10E The second gate region 185 shown in FIG. 1 may be filled with a second conductive pattern 189. Fig. 10E As described, when the space dedicated to the gate insulating layer 187 within the second gate region 185 is reduced, the space occupied by the second conductive pattern 189 within the second gate region 185 may be increased.

[0150] Fig.11 is a plan view showing a bit line 197 according to an embodiment of the present disclosure.

[0151] Reference Fig.11 , the bit line 197 may be formed at Fig.9E The bit line 197 may be formed on the third upper interlayer insulating layer 181 shown in FIG. Fig.9E The first contact plug 195A and the second contact plug 195B of the third upper interlayer insulating layer 181 shown in FIG. 1 are coupled to a pair of first and second groups of second channel structures (ie, the first group of second channel structures 170A and the second group of second channel structures 170B) corresponding to respective bit lines 197 .

[0152] Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D is an enlarged cross-sectional view showing a step of forming an upper stack according to an embodiment of the present disclosure.

[0153] Reference Fig. 12A , you can use the above reference Fig. 7A , Figure 7B and Figure 7C The first stacked body 250 extending to surround the first channel structure 230 is formed by the process described above. Fig. 7A , Figure 7B and Figure 7C According to the described process, the memory layer 220 may be disposed between the first channel structure 230 and the first stacked body 250 , and the first channel structure 230 may include a channel layer 231 and a first core insulating layer 233 .

[0154] After forming the first upper interlayer insulating layer 237 on the above-described first stacked body 250, sacrificial layers 261 and second upper interlayer insulating layers 263 may be alternately stacked on the first upper interlayer insulating layer 237. Then, a hole 267 may be formed through the first upper interlayer insulating layer 237, the sacrificial layers 261, and the second upper interlayer insulating layer 263 overlapping the first channel structure 230. The hole 267 may extend to the inside of the first core insulating layer 233, and may expose the channel layer 231.

[0155] Afterwards, you can use the above reference Fig. 10B The process described forms a doped semiconductor layer 271L on the surface defining the hole 267. Next, a barrier layer 273L may be formed on the doped semiconductor layer 271L. The thickness T2 of the barrier layer 273L may be controlled to be less than the thickness T1 of the doped semiconductor layer 271L. In an embodiment, the thickness T2 of the barrier layer 273L may be controlled to be less than or equal to

[0156] In an embodiment, the barrier layer 273L may include an oxide layer. In an embodiment, the oxide layer may be a native oxide layer formed on the surface of the doped semiconductor layer 271L. The native oxide layer may remain as the barrier layer 273L because a cleaning process is omitted after the doped semiconductor layer 271L is formed. The native oxide layer may be formed with a thickness smaller than that of the doped semiconductor layer 271L.

[0157] Reference Fig. 12B , an undoped semiconductor layer 275L may be formed on the surface of the barrier layer 273L. In an embodiment, the undoped semiconductor layer 275L may include undoped silicon. The thickness T3 of the undoped semiconductor layer 275L may be controlled to be greater than the thickness T2 of the barrier layer 273L. The barrier layer 273L may prevent the dopant from the doped semiconductor layer 271L from diffusing into the undoped semiconductor layer 275L.

[0158] Reference Fig. 12C , you can use the above reference Fig. 10C The described process forms a second core insulating layer 277 and a capping pattern 279 in the central region of the hole 267. The planarization process may be used to remove the second core insulating layer 277 and the capping pattern 279. Fig. 12B 271L, the barrier layer 273L, and the doped semiconductor layer 271L shown in the figure cover the corresponding portions of the top surface of the second upper interlayer insulating layer 263. In this way, the doped semiconductor layer 271L can remain in the hole 267 as the preliminary doped semiconductor pattern 271, the barrier layer 273L can remain in the hole 267 as the barrier pattern 273, and the undoped semiconductor layer 275L can remain in the hole 267 as the undoped semiconductor pattern 275U.

[0159] Reference Fig.12D , can be obtained by using the above reference Fig. 9C and Fig.9D Describe the process of removing Fig. 12C The sacrificial layer 261 shown in FIG. 2 is used to open the gate region.

[0160] Next, you can use the above reference Fig. 10Dand Fig. 10E The gate insulating layer 287 is formed by the process described.

[0161] The oxidation process for the preliminarily doped semiconductor pattern to form the gate insulating layer 287 may be controlled so that an oxidized region of the preliminarily doped semiconductor pattern contacts the barrier pattern 273. Fig. 12C The preliminary doped semiconductor patterns 271 shown in FIG. 2 may be separated into doped semiconductor patterns 271P by gate insulating layers 287 . In an implementation, a thickness T4 of each gate insulating layer 287 may be formed to be greater than a thickness T2 of the barrier pattern 273 .

[0162] After forming the gate insulating layer 287, the dopant of the capping pattern 279 may be diffused into Fig. 12C As a result, a semiconductor pattern 275 including a doped region ARd and an undoped region ARu may be defined. The doped region ARd may surround the sidewall of the capping pattern 279, and the undoped region ARu may be defined along the sidewall and bottom surface of the second core insulating layer 277.

[0163] Afterwards, you can use the above reference Fig.10F The described process is used to form conductive patterns 289 surrounding the gate insulating layers 287, respectively.

[0164] Fig.13A and Fig. 13B is a cross-sectional view showing a first channel structure CH1 ′ and a second channel structure CH2 ′ according to an embodiment of the present disclosure. Figure 3 Each of the first channel structures CH1A and CH1B shown in FIG. Fig.13A or Fig. 13B The first channel structure CH1 ′ shown in FIG. Figure 3 Each of the second channel structures CH2A and CH2B shown in FIG. Fig.13A or Fig. 13B The second channel structure CH2′ shown in FIG.

[0165] Reference Fig.13A and Fig. 13B , the first channel structure CH1' may penetrate the first stack body ST1'. The first stack body ST1' may include first interlayer insulating layers ILD1' and first conductive patterns CP1' alternately stacked, as described above with reference to Figure 3 Described.

[0166] The sidewall of the first channel structure CH1' may be surrounded by the memory layer ML'. Figure 4A and Figure 4BAs described, the memory layer ML' may include a tunnel insulating layer TI', a data storage layer DS', and a first blocking insulating layer BI1'.

[0167] As mentioned above Figure 4A and Figure 4B As described, the second blocking insulating layer BI2 ′ may be disposed between the first conductive pattern CP1 ′ and the memory layer ML′, and may extend to a space between the first conductive pattern CP1 ′ and the first interlayer insulating layer ILD1 ′.

[0168] The first channel structure CH1' may include a first core insulation layer CO1', a first channel layer CL1', and a pad pattern PAD'. The pad pattern PAD' may overlap the first core insulation layer CO1'. The first core insulation layer CO1' and the pad pattern PAD' may penetrate the first stack body ST1', and the first channel layer CL1' may extend to surround the sidewalls of the first core insulation layer CO1' and the sidewalls of the pad pattern PAD'. In an embodiment, the first channel layer CL1' may include an undoped semiconductor layer. In an embodiment, the undoped semiconductor layer may include undoped silicon. The pad pattern PAD' may include an undoped semiconductor layer or a doped semiconductor layer.

[0169] As mentioned above Figure 3 As described above, the second channel structure CH2' may penetrate the second interlayer insulating layer ILD2' covering the first stack ST1' and the second stack ST2' overlapping the first stack ST1', wherein the second interlayer insulating layer ILD2' is interposed between the first stack ST1' and the second stack ST2'. Figure 3 As described, the second stack body ST2 ′ may include the second conductive patterns CP2 ′ and the third interlayer insulating layers ILD3 ′ which are alternately stacked.

[0170] The sidewall of the first channel structure CH1' may be surrounded by the memory layer ML'. Figure 4A and Figure 4B As described, the memory layer ML' may include a tunnel insulating layer TI', a data storage layer DS', and a first blocking insulating layer BI1'.

[0171] As mentioned above Figure 3 As described above, the second channel structure CH2' may include a second core insulating layer CO2', a capping pattern CAP', and a second channel layer CL2A' or CL2B'. Figure 3 As described, the gate insulating layer GI' may be disposed between the second channel structure CH2' and the second conductive pattern CP2', respectively.

[0172] Reference Fig.13AThe second channel layer CL2A' may include a semiconductor pattern SE' and a doped semiconductor pattern DP', as described above with reference to Figure 4A As described above. Figure 4A As described, the semiconductor pattern SE' may include the undoped area UDA' and the doped area DA'.

[0173] Reference Fig. 13B The second channel layer CL2B' may include a semiconductor pattern SE', a barrier pattern BR' and a doped semiconductor pattern DP', as described above with reference to Figure 4B As described above. Figure 4B As described, the semiconductor pattern SE' may include the doped area DA' and the undoped area UDA'.

[0174] Fig.14 is a cross-sectional view illustrating a step of forming a first channel structure 330 according to an embodiment of the present disclosure. Fig.14 The first channel structure 330 shown in FIG. Fig.13A or Fig. 13B The first channel structure CH1 ′ is shown in FIG.

[0175] Reference Fig.14 , you can use the above reference Fig. 7A The process is described to perform the hole 315 through the lower interlayer insulating layer 301 and the first sacrificial layer 303 of the first preliminary stack 310 .

[0176] Afterwards, you can use the above reference Fig. 7A The described process forms a memory layer 320 including a first blocking insulating layer 321, a data storage layer 323, and a tunnel insulating layer 325 on the sidewalls of each hole 315. Next, the above reference Fig. 7A The described process forms a channel layer 331 and a core insulating layer 333 in each hole 315. Thereafter, a portion of the core insulating layer 333 may be removed so that the top of each hole 315 is open. The open top of each hole 315 may be filled with a pad pattern 335. The pad pattern 335 may include an undoped semiconductor layer or a doped semiconductor layer.

[0177] A planarization process may be used to planarize the pad pattern 335, the channel layer 331, and the memory layer 320. In this way, the top surface of the first preliminary laminate 310 may be exposed, and first channel structures 330 each including a channel layer 331, a core insulating layer 333, and a pad pattern 335 may be defined in the holes 315, respectively.

[0178] Next, you can execute the above reference Figure 7B and Figure 7C The process described above refers to Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig. 10E and Fig.10F The process described and the above reference Fig.11 In other embodiments, the above-mentioned process can be performed. Figure 7B and Figure 7C The process described above refers to Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D The process described and the above reference Fig.11 Describe the process.

[0179] Fig.15 is a block diagram illustrating a memory system 1100 according to an embodiment of the present disclosure.

[0180] Reference Fig.15 , the memory system 1100 includes a memory device 1120 and a memory controller 1110 .

[0181] The memory device 1120 may include: a stack including an interlayer insulating layer and a conductive pattern disposed between the interlayer insulating layers; a channel structure penetrating the stack; and a gate insulating layer between the channel structure and the conductive pattern. The channel layer of the channel structure may include: a semiconductor pattern including an undoped region surrounded by a gate insulating layer; and a doped semiconductor pattern surrounded by the interlayer insulating layer. The memory device 1120 may generate a gate induced drain leakage (GIDL) current during an erase operation. The doped semiconductor pattern may improve the GIDL current, and the undoped region may improve the cutoff characteristics of a transistor including a gate coupled to the conductive pattern.

[0182] The memory device 1120 may be a multi-chip package composed of a plurality of flash memory chips.

[0183] The memory controller 1110 may control the memory device 1120, and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 is used as a working memory of the CPU 1112, the CPU 1112 performs an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 is provided with a data exchange protocol of a host connected to the memory system 1100. In addition, the error correction block 1114 detects and corrects errors included in data read from the memory device 1120, and the memory interface 1115 interfaces with the memory device 1120. In addition, the memory controller 1110 may further include a read-only memory (ROM) or the like storing code data for interfacing with the host.

[0184] Fig.16 is a block diagram showing a configuration of a computing system according to an embodiment of the present disclosure.

[0185] Reference Fig.16 , the computing system 1200 according to an embodiment of the present disclosure may include a CPU 1220, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically coupled to a system bus 1260. The computing system 1200 may be a mobile device.

[0186] The memory system 1210 may include a memory device 1212 and a memory controller 1211. The memory device 1212 may include: a stack including an interlayer insulating layer and a conductive pattern disposed between the interlayer insulating layers; a channel structure penetrating the stack; and a gate insulating layer between the channel structure and the conductive pattern. The channel layer of the channel structure may include: a semiconductor pattern including an undoped region surrounded by a gate insulating layer; and a doped semiconductor pattern surrounded by the interlayer insulating layer.

[0187] According to the present disclosure, a channel structure penetrating a stack of conductive patterns and interlayer insulating layers may include a doped semiconductor pattern and an undoped region. Therefore, a selection transistor including a gate coupled to the conductive pattern and a channel including a doped semiconductor pattern and an undoped region can be provided.

[0188] According to the present disclosure, channel current characteristics can be improved by doping a semiconductor pattern. Therefore, the present disclosure can stably generate a gate induced drain leakage (GIDL) current for an erase operation, thereby improving the operational reliability of a semiconductor memory device.

[0189] According to the present disclosure, the cut-off characteristics of the selection transistor can be improved by the undoped region. Therefore, the present disclosure can improve the operational reliability of the semiconductor memory device.

[0190] CROSS-REFERENCE TO RELATED APPLICATIONS

[0191] This application claims the priority of Korean Patent Application No. 10-2020-0076048 filed on June 22, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor memory device, comprising: a stacked body including a plurality of interlayer insulating layers and a selection line disposed between the plurality of interlayer insulating layers; a semiconductor pattern, the semiconductor pattern penetrating the stacked body; a doped semiconductor pattern, wherein the doped semiconductor pattern is disposed between the semiconductor pattern and the interlayer insulating layer; as well as a gate insulating layer, the gate insulating layer being disposed between the semiconductor pattern and the selection line, The semiconductor pattern includes an undoped region surrounded by the gate insulating layer.

2. The semiconductor memory device according to claim 1, wherein The doped semiconductor pattern contacts the gate insulating layer.

3. The semiconductor memory device according to claim 1, wherein: The semiconductor pattern further includes a doped region surrounded by the doped semiconductor pattern.

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