Main junction modulation fast recovery diode chip and preparation method thereof

Abstract

The invention provides a main junction modulation fast recovery diode chip and a preparation method thereof, and relates to the technical field of semiconductors. The preparation method of the main junction modulation fast recovery diode chip comprises the following steps: providing an epitaxial wafer, and forming a main junction window and a cut-off ring window on a first surface of the epitaxial wafer by adopting a photoetching process; first nonmetal is injected into the main junction window and the cut-off ring window respectively, and diffusion junction pushing is carried out; forming a field limiting ring window on the first surface of the epitaxial wafer by adopting a photoetching process; and second nonmetal is injected into the main junction window and the field limiting ring window respectively and diffusion junction pushing is carried out so as to realize junction depth distribution of the main junction shallow ring junction depth. According to the preparation method of the main junction modulation fast recovery diode chip, the junction depth distribution of the main junction shallow ring junction depth can be generated on the premise of saving one-time photoetching, the withstand voltage, the through-current capability, the surge level and the preparation efficiency of the main junction modulation fast recovery diode chip can be improved, and the manufacturing cost of the main junction modulation fast recovery diode chip is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a main junction modulation fast recovery diode chip and a preparation method thereof. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar transistor and an insulated gate field effect transistor. It has the advantages of high input impedance of metal-oxide semiconductor field effect transistor and low on-state voltage drop of power transistor. When using IGBT, it is usually necessary to use FRD (Fast Recovery Diode). FRD mainly plays the role of freewheeling, clamping and buffering in the circuit.

[0003] With the development of new energy, the conversion efficiency and voltage requirements of IGBT are getting higher and higher, which puts higher requirements on the FRD devices connected in parallel in the circuit. Existing FRD products generally use planar field limiting rings and field plate structures to minimize the impact of curvature effect on the breakdown voltage of the PN junction. During preparation, the main junction and the ring junction are injected and pushed separately to obtain a junction depth distribution effect with a shallow main junction and a deep ring junction. In this way, when the main junction depletion layer widens under reverse bias, the electric field sharing and protection of the field limiting ring junction can be obtained faster, so that the product has a higher reverse breakdown voltage and avalanche tolerance. However, this preparation method requires multiple photolithography, which is inefficient and costly. Summary of the invention

[0004] The purpose of the present application is to provide a main junction modulated fast recovery diode chip and a preparation method thereof in view of the deficiencies in the above-mentioned prior art, which can produce a junction depth distribution with a main junction shallow ring junction and a deep junction, and has high preparation efficiency and low cost.

[0005] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0006] According to one aspect of an embodiment of the present application, a method for preparing a main junction modulated fast recovery diode chip is provided, comprising: providing an epitaxial wafer, and using a photolithography process to form a main junction window and a cutoff ring window on a first surface of the epitaxial wafer, wherein the cutoff ring window surrounds the main junction window; injecting a first non-metal into the main junction window and the cutoff ring window respectively and performing diffusion to push the junction; using a photolithography process to form a field limiting ring window on the first surface of the epitaxial wafer, wherein the field limiting ring window surrounds the main junction window, and the field limiting ring window is located between the main junction window and the cutoff ring window; injecting a second non-metal into the main junction window and the field limiting ring window respectively and performing diffusion to push the junction, so as to achieve a junction depth distribution with a shallow main junction and a deep ring junction.

[0007] Optionally, providing an epitaxial wafer and using a photolithography process to form a main junction window and a cutoff ring window on the first surface of the epitaxial wafer includes: providing an epitaxial wafer and forming an oxide layer on the first surface of the epitaxial wafer; using a photolithography process to form a main junction window and a cutoff ring window on the surface of the oxide layer.

[0008] Optionally, after respectively injecting a second non-metal into the main junction window and the field limiting ring window and performing diffusion and pushing the junction, the method further includes: forming at least two field plates on the first surface of the epitaxial wafer, wherein at least two field plates sequentially surround the main junction window, one field plate is connected to the main junction window, and the remaining field plates are respectively connected to the field limiting ring windows.

[0009] Optionally, after forming at least two field plates on the first surface of the epitaxial wafer, the method further comprises: implanting platinum into the first surface of the epitaxial wafer and performing platinum diffusion.

[0010] Optionally, after platinum is injected into the first surface of the epitaxial wafer and platinum is diffused, the method further includes: forming a first metal layer on the first surface of the epitaxial wafer, wherein the first metal layer covers the main junction window; and forming a second metal layer on the second surface of the epitaxial wafer, wherein the second surface is opposite to the first surface.

[0011] Optionally, after forming the first metal layer on the first surface of the epitaxial wafer, the method further includes: forming a passivation layer on the first surface of the epitaxial wafer, wherein the passivation layer covers the edge of the first metal layer, the field plate, the field limiting ring window and the cutoff ring window.

[0012] Optionally, before forming the second metal layer on the second surface of the epitaxial wafer, the method further comprises: performing a thinning operation on the epitaxial wafer on one side of the second surface of the epitaxial wafer to reduce the thickness of the epitaxial wafer.

[0013] Optionally, the first non-metal is phosphorus, and the second non-metal is boron or aluminum.

[0014] Optionally, there are multiple field limiting ring windows, and the multiple field limiting ring windows surround the main junction window in sequence.

[0015] On the other hand, an embodiment of the present application provides a main junction modulated fast recovery diode chip, comprising: an epitaxial wafer, a main junction arranged on a first surface of the epitaxial wafer, a field limiting ring and a cutoff ring, the field limiting ring and the cutoff ring surround the main junction in sequence, the junction depth of the main junction is smaller than the junction depth of the field limiting ring, the main junction is filled with a first non-metal and a second non-metal covering the first non-metal, and the field limiting ring is filled with the second non-metal.

[0016] The beneficial effects of this application include:

[0017] The present application provides a method for preparing a main junction modulated fast recovery diode chip, comprising: providing an epitaxial wafer, and using a photolithography process to form a main junction window and a cutoff ring window on the first surface of the epitaxial wafer, wherein the cutoff ring window surrounds the main junction window; injecting a first non-metal into the main junction window and the cutoff ring window respectively and performing diffusion and pushing the junction; using a photolithography process to form a field limiting ring window on the first surface of the epitaxial wafer, wherein the field limiting ring window surrounds the main junction window, and the field limiting ring window is located between the main junction window and the cutoff ring window; injecting a second non-metal into the main junction window and the field limiting ring window respectively and performing diffusion and pushing the junction to achieve a junction depth distribution of a main junction shallow ring junction depth. The method for preparing a main junction modulated fast recovery diode chip adopts a method of first injecting a first non-metal into the main junction window and then injecting a second non-metal into the main junction window to perform main junction junction depth modulation, thereby generating a junction depth distribution of a main junction shallow ring junction depth. In this way, it can be achieved that in the reverse bias state, as the depletion layer expands, the main junction develops as far as possible in the direction of the parallel plane junction, reducing the influence of the curvature effect on the voltage of the main junction modulation fast recovery diode chip, so that the main junction modulation fast recovery diode chip can withstand higher voltages; in the forward turn-on state, more electron holes and other carriers can be produced, significantly improving the flow capacity and surge level of the main junction modulation fast recovery diode chip. At the same time, it can save one photolithography, improve the preparation efficiency of the main junction modulation fast recovery diode chip, and reduce the manufacturing cost of the main junction modulation fast recovery diode chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 One of the flow charts of the method for preparing the main junction modulated fast recovery diode chip provided in the embodiment of the present application;

[0020] Figure 2 One of the schematic diagrams of the preparation process of the main junction modulated fast recovery diode chip provided in the embodiment of the present application;

[0021] Figure 3 The second schematic diagram of the preparation process of the main junction modulated fast recovery diode chip provided in the embodiment of the present application;

[0022] Figure 4 Flow chart 2 of the method for preparing the main junction modulated fast recovery diode chip provided in the embodiment of the present application;

[0023] Figure 5The third schematic diagram of the preparation process of the main junction modulated fast recovery diode chip provided in the embodiment of the present application;

[0024] Figure 6 A schematic diagram of the structure of a main junction modulated fast recovery diode chip provided in an embodiment of the present application.

[0025] Icon: 10-main junction modulated fast recovery diode chip; 11-epitaxial wafer; 111-main junction window; 112-cutoff ring window; 113-field limiting ring window; 12-main junction; 13-cutoff ring; 14-field limiting ring; 15-oxide layer; 16-field plate; 17-first metal layer; 18-second metal layer; 19-passivation layer. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. It should be noted that, in the absence of conflict, the various features in the embodiments of the present application can be combined with each other, and the combined embodiments are still within the scope of protection of the present application.

[0028] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0029] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0030] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0031] In one aspect of the embodiment of the present application, please refer to Figure 1 , a method for preparing a main junction modulated fast recovery diode chip is provided, comprising:

[0032] S100: providing an epitaxial wafer, and forming a main junction window and a cut-off ring window on a first surface of the epitaxial wafer by using a photolithography process, wherein the cut-off ring window surrounds the main junction window.

[0033] Please refer to Figure 2 The epitaxial wafer 11 is an epitaxial wafer 11 that can be used to prepare a fast recovery diode, and its structure is a prior art. For example, the epitaxial wafer 11 is an N-type epitaxial wafer.

[0034] The epitaxial wafer 11 has a first surface and a second surface opposite to each other. A main junction window 111 and a stop ring window 112 are formed from the first surface of the epitaxial wafer 11 to the inside of the epitaxial wafer 11. The stop ring window 112 is ring-shaped and is arranged around the main junction window 111.

[0035] S200: injecting a first non-metal into the main junction window and the cut-off ring window respectively and performing diffusion to push the junction.

[0036] The first non-metal is injected into the main junction window 111, and the first non-metal is pushed into a deeper position in the epitaxial wafer 11 (i.e., a diffusion push junction). The first non-metal is injected into the cut-off ring window 112, and the first non-metal is pushed into a deeper position in the epitaxial wafer 11. The diffusion push junction process is a prior art, and this embodiment will not be described in detail here. The first non-metal injection into the main junction window 111 and the cut-off ring window 112 can be performed simultaneously, or one after the other. Similarly, the diffusion push junction of the main junction window 111 and the diffusion push junction of the cut-off ring window 112 can be performed simultaneously, or one after the other. After the first non-metal is injected into the cut-off ring window 112 and a diffusion push junction is performed, a cut-off ring 13 is formed. By way of example, the first non-metal is phosphorus.

[0037] S300: forming a field limiting ring window on the first surface of the epitaxial wafer by using a photolithography process, wherein the field limiting ring window surrounds the main junction window and is located between the main junction window and the cut-off ring window.

[0038] Please refer to Figure 3The field limiting ring window 113 is annular and is arranged around the main junction window 111. The number of the field limiting ring windows 113 can be one, two or more, and all the field limiting ring windows 113 are located between the main junction window 111 and the cut-off ring window 112.

[0039] When the number of field limiting ring windows 113 is at least two, the size of at least two field limiting ring windows 113 gradually increases and surrounds the main junction window 111 in sequence. The main function of the field limiting ring 14 is to improve the withstand voltage performance of the main junction modulation fast recovery diode chip 10 and reduce the electric field concentration effect, thereby extending the life of the main junction modulation fast recovery diode chip 10 and improving the overall reliability. Providing multiple field limiting rings 14 can effectively suppress the uneven distribution of the edge electric field and avoid local breakdown caused by excessive concentration of the electric field.

[0040] S400: injecting a second non-metal into the main junction window and the field limiting ring window respectively and performing diffusion to push the junction, so as to achieve a junction depth distribution in which the main junction is shallow and the ring junction is deep.

[0041] A second non-metal is injected into the main junction window 111, and the second non-metal is pushed into a deeper position in the epitaxial wafer 11. A second non-metal is injected into the field limiting ring window 113, and the first and second non-metals are pushed into a deeper position in the epitaxial wafer 11. The second non-metal injection of the main junction window 111 and the field limiting ring window 113 can be performed simultaneously or one after the other. Similarly, the diffusion push-junction of the main junction window 111 and the diffusion push-junction of the field limiting ring window 113 can be performed simultaneously or one after the other. For example, the second non-metal is boron or aluminum.

[0042] The main junction 12 is formed by injecting the second non-metal into the main junction window 111 and performing diffusion and pushing the junction, and the field limiting ring 14 is formed by injecting the second non-metal into the field limiting ring window 113 and performing diffusion and pushing the junction. Since the first non-metal is first injected into the main junction window 111 in step S200, the regulation effect of the first non-metal can effectively make the junction depth of the main junction 12 shallower than the junction depth of the field limiting ring 14 without modulation, thereby realizing the junction depth distribution of the main junction shallow and the ring deep.

[0043] The preparation method of the main junction modulation fast recovery diode chip mentioned above adopts a method of first injecting the first non-metal and then injecting the second non-metal into the main junction window 111 to modulate the junction depth of the main junction 12, so as to produce a junction depth distribution with a shallow ring junction depth of the main junction. In this way, it can be achieved that in the reverse bias state, with the expansion of the depletion layer, the main junction 12 develops in the direction of the parallel plane junction as much as possible, reducing the influence of the curvature effect on the voltage of the main junction modulation fast recovery diode chip 10, so that the main junction modulation fast recovery diode chip 10 can withstand higher voltages; in the forward turn-on state, more carriers such as electrons and holes can be produced, which significantly improves the flow capacity and surge level of the main junction modulation fast recovery diode chip 10. At the same time, one photolithography can be saved, the preparation efficiency of the main junction modulation fast recovery diode chip 10 is improved, and the manufacturing cost of the main junction modulation fast recovery diode chip 10 is reduced.

[0044] Optionally, see Figure 4 , providing an epitaxial wafer, and using a photolithography process to form a main junction window and a cutoff ring window on a first surface of the epitaxial wafer, including:

[0045] S110: providing an epitaxial wafer, and forming an oxide layer on a first surface of the epitaxial wafer.

[0046] S120: A main junction window and a cutoff ring window are formed on the surface of the oxide layer by using a photolithography process.

[0047] Please refer to Figure 2 Before forming the main junction window 111 and the stop ring window 112, an oxide layer 15 is first formed on the first surface of the epitaxial wafer 11, and then the main junction window 111 and the stop ring window 112 are formed in the epitaxial wafer 11 by photolithography on the surface of the oxide layer 15 away from the epitaxial wafer 11. The oxide layer 15 has the functions of anti-corrosion, improving wear resistance and electrical insulation. The oxide layer 15 can be obtained by surface oxidation of the epitaxial wafer 11.

[0048] Optionally, see Figure 1 After injecting a second non-metal into the main junction window and the field limiting ring window respectively and performing diffusion and pushing the junction, the method further comprises:

[0049] S500: forming at least two field plates on the first surface of the epitaxial wafer, wherein the at least two field plates sequentially surround the main junction window, one field plate is connected to the main junction window, and the remaining field plates are respectively connected to the field limiting ring windows.

[0050] Please refer to Figure 5Among the at least two field plates 16, one of the field plates 16 covers a portion of the main junction window 111, thereby connecting to the main junction 12; one of the field plates 16 covers a portion of the cut-off ring window 112, thereby connecting to the cut-off ring 13; the remaining field plates 16 correspond one-to-one to the field limiting ring windows 113, and respectively cover a portion of the field limiting ring windows 113 corresponding thereto, thereby realizing a one-to-one corresponding connection between the field plates 16 and the field limiting rings 14.

[0051] For example, D-POLY is deposited on the first surface of the epitaxial wafer 11 , and the deposited D-POLY is photolithographically processed, followed by dry etching, so as to etch out the poly field plate 16 .

[0052] If an oxide layer 15 is formed on the surface of the epitaxial wafer 11 , a portion of the field plate 16 covers the oxide layer 15 , and another portion covers the corresponding main junction window 111 , stop ring window 112 or field limiting ring window 113 .

[0053] Optionally, see Figure 1 After forming at least two field plates on the first surface of the epitaxial wafer, the method further comprises:

[0054] S600: Platinum is implanted into the first surface of the epitaxial wafer and platinum is diffused.

[0055] The platinum diffusion process can reduce the reverse recovery time of the main junction modulation fast recovery diode chip 10 and increase the life of the main junction modulation fast recovery diode chip 10. Moreover, platinum will not produce agglomeration effect in the epitaxial wafer 11, and the platinum diffusion process has low cost and is suitable for mass production.

[0056] Optionally, after implanting platinum into the first surface of the epitaxial wafer and performing platinum diffusion, the method further comprises:

[0057] S710: forming a first metal layer on a first surface of the epitaxial wafer, wherein the first metal layer covers the main junction window.

[0058] For example, please refer to Figure 6 A layer of metal material is deposited on the first surface of the epitaxial wafer 11, and the deposited metal material is photolithographically processed to obtain a patterned first metal layer 17. The first metal layer 17 covers the main junction window 111, and forms a front metal contact on the surface of the main junction 12.

[0059] S720: forming a second metal layer on a second surface of the epitaxial wafer, wherein the second surface is opposite to the first surface.

[0060] By way of example, a layer of metal material is deposited on the second surface of the epitaxial wafer 11 to obtain the second metal layer 18 .

[0061] The second metal layer 18 covers the second surface of the epitaxial wafer 11 to form a back metal contact on the second surface of the epitaxial wafer 11. The first metal layer 17 and the second metal layer 18 can reduce the contact resistance and improve the switching speed and withstand voltage of the main junction modulation fast recovery diode chip 10.

[0062] Optionally, see Figure 1 After forming the first metal layer on the first surface of the epitaxial wafer, the method further comprises:

[0063] S800: forming a passivation layer on the first surface of the epitaxial wafer, wherein the passivation layer covers an edge of the first metal layer, a field plate, a field limiting ring window, and a stop ring window.

[0064] Please refer to Figure 6 The passivation layer 19 covers the first surface of the epitaxial wafer 11 and the structure formed on the first surface, and only partially exposes the first metal layer 17. The passivation layer 19 can protect the main junction modulation fast recovery diode chip 10, reduce the erosion of impurities and moisture on the main junction modulation fast recovery diode chip 10, and thus extend its service life.

[0065] For example, a layer of polyimide material is deposited on the first surface of the epitaxial wafer 11 , and the deposited polyimide material is photolithographically processed to obtain a patterned passivation layer 19 .

[0066] Optionally, before forming the second metal layer on the second surface of the epitaxial wafer, the method further comprises:

[0067] S900: performing a thinning operation on the epitaxial wafer at one side of the second surface of the epitaxial wafer to reduce the thickness of the epitaxial wafer.

[0068] Please refer to Figure 6 By thinning the thickness of the epitaxial wafer 11 from the back side of the epitaxial wafer 11 , the thickness of the main junction modulation fast recovery diode chip 10 can be reduced, and the on-resistance of the main junction modulation fast recovery diode chip 10 can be reduced.

[0069] It should be understood that although Figure 1 and Figure 4 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 and Figure 4At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0070] This embodiment also provides a main junction modulation fast recovery diode chip 10, which is prepared by the above-mentioned main junction modulation fast recovery diode chip preparation method. The main junction modulation fast recovery diode chip 10 includes an epitaxial wafer 11, a main junction 12 arranged on the first surface of the epitaxial wafer 11, a field limiting ring 14 and a cut-off ring 13, the field limiting ring 14 and the cut-off ring 13 surround the main junction 12 in sequence, the junction depth of the main junction 12 is less than the junction depth of the field limiting ring 14, the main junction 12 is filled with a first non-metal and a second non-metal covering the first non-metal, and the field limiting ring 14 is filled with the second non-metal.

[0071] The main junction modulation fast recovery diode chip 10 has a shallow main junction and a deep ring junction, has high withstand voltage, current carrying capacity, surge level and manufacturing efficiency, and has low cost.

[0072] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a main junction modulated fast recovery diode chip, characterized in that: include: Providing an epitaxial wafer, and forming a main junction window and a cut-off ring window on a first surface of the epitaxial wafer by using a photolithography process, wherein the cut-off ring window surrounds the main junction window; Injecting a first non-metal into the main junction window and the cut-off ring window respectively and performing diffusion and pushing the junction; Forming a field limiting ring window on the first surface of the epitaxial wafer by using a photolithography process, wherein the field limiting ring window surrounds the main junction window and is located between the main junction window and the cut-off ring window; A second non-metal is injected into the main junction window and the field limiting ring window respectively, and the junction is diffused and pushed, so as to achieve a junction depth distribution with a shallow main junction and a deep ring junction.

2. The method for preparing the main junction modulated fast recovery diode chip according to claim 1, characterized in that: The step of providing an epitaxial wafer and forming a main junction window and a cutoff ring window on a first surface of the epitaxial wafer by using a photolithography process comprises: Providing an epitaxial wafer, and forming an oxide layer on a first surface of the epitaxial wafer; A main junction window and a cut-off ring window are formed on the surface of the oxide layer by using a photolithography process.

3. The method for preparing the main junction modulated fast recovery diode chip according to claim 1, characterized in that: After respectively injecting a second non-metal into the main junction window and the field limiting ring window and performing diffusion and junction pushing, the method further comprises: At least two field plates are formed on the first surface of the epitaxial wafer, wherein at least two of the field plates surround the main junction window in sequence, one of the field plates is connected to the main junction window, and the remaining field plates are respectively connected to the field limiting ring windows.

4. The method for preparing the main junction modulated fast recovery diode chip according to claim 3, characterized in that: After forming at least two field plates on the first surface of the epitaxial wafer, the method further comprises: Platinum is implanted into the first surface of the epitaxial wafer and then diffused.

5. The method for preparing the main junction modulated fast recovery diode chip according to claim 4, characterized in that: After implanting platinum into the first surface of the epitaxial wafer and performing platinum diffusion, the method further comprises: Forming a first metal layer on the first surface of the epitaxial wafer, wherein the first metal layer covers the main junction window; A second metal layer is formed on a second surface of the epitaxial wafer, wherein the second surface is opposite to the first surface.

6. The method for preparing the main junction modulated fast recovery diode chip according to claim 5, characterized in that: After forming the first metal layer on the first surface of the epitaxial wafer, the method further comprises: A passivation layer is formed on the first surface of the epitaxial wafer, wherein the passivation layer covers the edge of the first metal layer, the field plate, the field limiting ring window and the stop ring window.

7. The method for preparing the main junction modulated fast recovery diode chip according to claim 5, characterized in that: Before forming the second metal layer on the second surface of the epitaxial wafer, the method further comprises: The epitaxial wafer is thinned on one side of the second surface of the epitaxial wafer to reduce the thickness of the epitaxial wafer.

8. The method for preparing the main junction modulated fast recovery diode chip according to claim 1, characterized in that: The first non-metal is phosphorus, and the second non-metal is boron or aluminum.

9. The method for preparing a main junction modulated fast recovery diode chip according to claim 1, characterized in that: There are multiple field limiting ring windows, and the multiple field limiting ring windows surround the main junction window in sequence.

10. A main junction modulated fast recovery diode chip, characterized in that: include: An epitaxial wafer, a main junction, a field limiting ring and a cut-off ring arranged on a first surface of the epitaxial wafer, the field limiting ring and the cut-off ring surround the main junction in sequence, the junction depth of the main junction is smaller than the junction depth of the field limiting ring, the main junction is filled with a first non-metal and a second non-metal covering the first non-metal, and the field limiting ring is filled with the second non-metal.

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