Semiconductor device, manufacturing method thereof and electronic equipment
By removing the substrate on the back of the semiconductor device and reducing the depth and depth ratio of the power supply through holes, the problems of complex production process and large power supply signal voltage drop caused by the depth and width of the power supply through holes in the prior art are solved, and the effect of simplifying the process and improving device performance is achieved.
Patent Information
- Application Number
- CN202311155757.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-07
- Publication Date
- 2025-03-11
AI Technical Summary
The depth and width of the power supply through holes in existing semiconductor devices are relatively high, resulting in complex manufacturing processes and large power signal voltage drop, affecting device performance and power consumption.
By removing the substrate on the back of the semiconductor device, the end surface of the power supply through hole is flush with the isolation dielectric layer, the depth of the power supply through hole is reduced, thereby reducing the depth-to-face ratio and simplifying the production process.
The depth and depth ratio of the power supply through-hole are reduced, the production process is simplified, the voltage drop of the power supply signal is reduced, the performance of semiconductor devices is improved and power consumption is reduced.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art
[0002] With the continuous development of semiconductor technology, semiconductor devices are gradually developing towards higher device density, higher device performance, and lower manufacturing cost, so that semiconductor devices are gradually developing towards a three-dimensional structure. For example, semiconductor devices may include: fin field effect transistors (Fin FET) or all-around gate (GAA) transistors and other transistors with a three-dimensional structure.
[0003] In traditional semiconductor devices, transistors need to be connected to a power supply network on the front side. The power supply network and the signal network need to occupy the interconnection layer of the semiconductor device together, which requires the power signal to pass through multiple film layers in the interconnection layer before it can be transmitted to the transistor, resulting in a large voltage drop (IR drop) of the power signal and a larger area of the logic cell of the semiconductor device.
[0004] In order to solve the above technical problems caused by the front power supply network solution, the related art proposes a solution of setting a backside power delivery network (BSPDN) in the electronic device, and the transistor in the semiconductor device is connected to the backside power distribution network on the back through a power via, so as to reduce the voltage drop of the power signal, reduce the area of the logic unit of the semiconductor device, improve the performance of the semiconductor device, and reduce the power consumption of the semiconductor device. However, due to the high depth-to-width ratio of the power via, the etching process and deposition process of making the power via are more difficult, and the back manufacturing process of the semiconductor device is more complicated. Summary of the invention
[0005] The embodiments of the present application provide a semiconductor device, a manufacturing method thereof, and an electronic device for reducing the aspect ratio of a power via, thereby simplifying the manufacturing process of the power via and reducing the complexity of the backside manufacturing process of the semiconductor device.
[0006] In the first aspect, an embodiment of the present application provides a semiconductor device. The semiconductor device provided in the embodiment of the present application may include: a fin structure, an isolation dielectric layer, a source-drain electrode, and a power via. The semiconductor device in the embodiment of the present application may include one or more fin structures, and the isolation dielectric layer may play a supporting and insulating role. When the semiconductor device includes multiple fin structures, the isolation dielectric layer may also play a role in separating adjacent fin structures. The source-drain electrode is electrically connected to the channel region of the fin structure, and the source-drain electrode may be the source or drain of the transistor, and the source-drain electrode may include polysilicon material or other conductive materials. The semiconductor device in the embodiment of the present application may also include a gate. The semiconductor device may include one or more transistors, each of which includes: a fin structure, a source and a drain electrically connected to the channel region of the fin structure, and a gate covering the channel region of the fin structure. By applying a gate voltage to the gate, the conduction or cutoff of the transistor can be controlled.
[0007] The isolation dielectric layer includes a first surface and a second surface that are arranged opposite to each other in the thickness direction. The fin structure penetrates the isolation dielectric layer in the thickness direction, and the surface on one side of the fin structure is flush with the second surface of the isolation dielectric layer, and the other side protrudes from the first surface of the isolation dielectric layer. The power through hole penetrates the isolation dielectric layer in the thickness direction, the first end of the power through hole is electrically connected to the source and drain electrodes, the second end of the power through hole is flush with the second surface of the isolation dielectric layer, and the second end of the power through hole is used to electrically connect to the back side power distribution network. In an embodiment of the present application, the power through hole is formed in the isolation dielectric layer by an etching process, and a conductive material is filled in the through hole by a deposition process, that is, the power through hole includes a conductive material, which can play a role of electrical connection. The power through hole may include a metal material. Of course, the power through hole may also include other conductive materials, which are not limited here.
[0008] In the related art, the power via needs to penetrate the isolation dielectric layer and be embedded to a certain depth of the substrate, resulting in a high depth-to-width ratio of the power via, a high difficulty in the etching process and deposition process of the power via, and a complex backside manufacturing process of the semiconductor device. In the semiconductor device provided in the embodiment of the present application, by removing the substrate on the back side and making the end face of the power via flush with the second surface of the isolation dielectric layer, the depth of the power via can be reduced, the depth-to-width ratio of the power via can be reduced, thereby simplifying the manufacturing process of the power via and reducing the complexity of the backside manufacturing process of the semiconductor device. In addition, by reducing the depth of the power via, the transmission path of the power signal can be shortened, the voltage drop of the power signal can be reduced, thereby reducing the cut-off current (Ioff) of the semiconductor device and improving the performance of the semiconductor device.
[0009] The semiconductor device in the embodiment of the present application may also include: a conductive connection portion located on the side of the source and drain electrodes away from the isolation dielectric layer, and an interlayer dielectric layer located on the side of the first surface of the isolation dielectric layer. The power supply via penetrates the isolation dielectric layer and part of the interlayer dielectric layer in the thickness direction, and at least part of the conductive connection portion is located in the interlayer dielectric layer. In the thickness direction of the isolation dielectric layer, the conductive connection portion at least partially overlaps with the source and drain electrodes, and the conductive connection portion at least partially overlaps with the power supply via, and the power supply via is electrically connected to the source and drain electrodes through the conductive connection portion. In the thickness direction of the isolation dielectric layer, the power supply via and the source and drain electrodes do not overlap each other, and the electrical connection between the power supply via and the source and drain electrodes can be achieved by setting the conductive connection portion. In a specific implementation, the power supply via and the conductive connection portion may include the same conductive material, for example, the power supply via and the conductive connection portion may both include metal materials, and in some cases, the power supply via and the conductive connection portion may also include different conductive materials, which are not limited here.
[0010] In a possible implementation, the channel region of the fin structure has a first end surface and a second end surface that are oppositely arranged in a first direction, and the first direction is parallel to the first surface of the isolation dielectric layer. The source and drain electrodes are in contact with the first end surface or the second end surface. Exemplarily, the fin structure may be in contact with the source electrode at the first end surface and in contact with the drain electrode at the second end surface.
[0011] In an embodiment of the present application, the fin structure may include: a sub-fin portion and a device portion, the sub-fin portion is located inside the isolation dielectric layer, the device portion is located on the side of the sub-fin portion away from the isolation dielectric layer, and the channel region of the fin structure is located inside the device portion. The two end faces of the device portion that are relatively arranged in the first direction may be the above-mentioned first end face and second end face, and the source and drain electrodes are specifically contacted and connected with the end faces of the device portion. The sub-fin portion may play a role in supporting the device portion, making it easier for the gate to surround the device portion to realize a transistor with a three-dimensional structure. In a specific implementation, adjacent fin structures may share the same sub-fin portion. The sub-fin portion may include semiconductor materials such as Si and Ge. In some cases, in order to avoid short-circuiting the sub-fin portion with other conductive components, the sub-fin portion may also be set to an insulating material. The material of the sub-fin portion may be selected according to actual needs and is not limited here.
[0012] In some embodiments of the present application, the semiconductor device may include a gate-all-around (GAA) transistor. Specifically, the device portion may include: a plurality of channel layers stacked and arranged, and the number of channel layers may be set according to actual needs. The semiconductor device may also include: a gate dielectric layer, the gate surrounds each channel layer through the gate dielectric layer, and the area of each channel layer surrounded by the gate is the channel region of the fin structure. In this way, a three-dimensional structure in which the gate surrounds the channel layer can be formed, and the coverage area of the channel region of the gate and the fin structure is large, which can increase the gate's control ability over the transistor and improve the performance of the semiconductor device. Exemplarily, the channel layer may be a nanosheet or a nanowire.
[0013] In a specific implementation, the semiconductor device may further include: an inner spacer, which may be located between adjacent channel layers, or between the first or last channel layer and other film layers, and the inner spacer may isolate the gate from the source-drain electrode to prevent the gate from being short-circuited with the source-drain electrode. In addition, in order to improve the performance of the semiconductor device, a bottom dielectric isolation layer (Bottom dielectric isolation, BDI) may be provided between the device portion and the sub-fin portion, and the gate (or device portion) and the bottom dielectric isolation layer have an overlapping area in a direction perpendicular to the thickness of the isolation dielectric layer. In this way, the leakage current of the transistor may be reduced by the isolation effect of the bottom dielectric isolation layer.
[0014] In some other embodiments of the present application, the semiconductor device may include a fin field effect transistor (Fin FET), specifically, the semiconductor device may further include: a gate dielectric layer, a gate surrounding the top surface of the device portion and two side surfaces connected to the top surface through the gate dielectric layer, the top surface being the surface of the device portion on the side of the back ion fin portion, and the area of the device portion covered by the gate being the channel region of the fin structure. In this way, a three-dimensional structure in which the gate surrounds the channel region on three sides can be formed, and the coverage area of the gate and the channel region of the fin structure is large, which can increase the gate's control ability over the transistor and improve the performance of the semiconductor device.
[0015] In the embodiments of the present application, the transistor in the semiconductor device is a full-surround gate transistor as an example for explanation. When the transistor is a fin field effect transistor, the embodiment in which the transistor is a full-surround gate transistor can be referred to, and the repeated parts will not be repeated.
[0016] The semiconductor device in the embodiment of the present application may also include: an interconnection layer located on the side of the gate away from the isolation dielectric layer, and the interconnection layer may include a plurality of conductive film layers and a plurality of insulating film layers. The transistor in the semiconductor device can lead the signal from the front through the interconnection layer. In the embodiment of the present application, the transistor is connected to the back side distribution network through the power via, and the power supply network does not need to occupy the space of the front interconnection layer, which can reduce the area of the logic unit of the semiconductor device and improve the density of the semiconductor device. In addition, the depth-to-width ratio of the power via in the embodiment of the present application is relatively small, the transmission path of the power signal is short, and the voltage drop of the power signal is small, so that the performance of the semiconductor device is better.
[0017] In a second aspect, an embodiment of the present application further provides an electronic device, and the electronic device in the embodiment of the present application may include: any of the above-mentioned semiconductor devices and a back-side power distribution network, and the semiconductor device is electrically connected to the back-side power distribution network through a power through hole. Since the depth-to-width ratio of the power through hole in the above-mentioned semiconductor device is relatively small, the process complexity of manufacturing the above-mentioned semiconductor device is relatively low, and the performance of the semiconductor device is relatively good, so the process complexity of the electronic device including the above-mentioned semiconductor device is also relatively low, and the performance of the electronic device is also relatively good.
[0018] In a third aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device provided by an embodiment of the present application may include:
[0019] Step 1: Form a fin structure and an isolation dielectric layer on the substrate, so that the fin structure penetrates the isolation dielectric layer in the thickness direction and protrudes from the first surface of the isolation dielectric layer, where the first surface is the surface of the isolation dielectric layer facing away from the substrate. The specific production process of step 1 is as follows:
[0020] A substrate is provided, and the substrate may include semiconductor materials such as Si and Ge. A first etch stop layer (ESL) and a first semiconductor layer may be provided on the substrate, and the first etch stop layer may include materials such as SiGe and SiO2, and the first semiconductor layer may include semiconductor materials such as Si and Ge. A first sacrificial layer may be epitaxially grown on the first semiconductor layer, and the first sacrificial layer may include materials such as SiGe, Si, SiGe, Si, SiGe, and Si. Afterwards, multiple layers of second semiconductor layers and multiple layers of second sacrificial layers are alternately epitaxially grown on the first sacrificial layer to obtain a stacked film layer. In a specific implementation, the number of layers of the second semiconductor layer and the second sacrificial layer may be set according to actual needs, and the number of layers of the second semiconductor layer and the second sacrificial layer may be the same or different, which is not limited here. The second semiconductor layer may include semiconductor materials such as Si and Ge, and the second sacrificial layer may include materials with relatively high etching selectivity such as SiGe.
[0021] The stacked film layer, the first sacrificial layer and the first semiconductor layer are patterned to obtain one or more fin structures. Each fin structure may include: a sub-fin portion and a device portion, the sub-fin portion is obtained by patterning the first semiconductor layer, and the device portion is obtained by patterning the stacked film layer. Specifically, the device portion may include: a plurality of channel layers and a plurality of second sacrificial layers that are stacked and alternately arranged, the channel layer is obtained by patterning the second semiconductor layer, and the second sacrificial layer needs to be removed later. After the above patterning process, the first semiconductor layer is not completely removed except for the fin structures, and a shallow trench structure is formed between adjacent sub-fins. Then, an isolation dielectric layer is formed in the region outside the fin structures on the first semiconductor layer, so that the isolation dielectric layer is filled in the shallow trench structure, so that the fin structure passes through the isolation dielectric layer in the thickness direction and protrudes from the first surface of the isolation dielectric layer. The isolation dielectric layer can play a supporting and insulating role. When the semiconductor device includes multiple fin structures, the isolation dielectric layer can also play a role in separating adjacent fin structures. The first surface of the isolation dielectric layer can be substantially flush with the surface of the sub-fin, or the first surface of the isolation dielectric layer can be substantially flush with the surface of the first sacrificial layer. Optionally, the isolation dielectric layer may include one or more of SiO2, SiON, and SiNx.
[0022] Afterwards, a dummy gate is formed on the fin structure and the isolation dielectric layer. The dummy gate may surround the top surface and two side surfaces of the device portion, that is, the dummy gate may surround the device portion on three sides. The dummy gate may include a dummy gate electrode layer and a dummy insulating layer disposed between the dummy gate electrode layer and the device portion. Optionally, the dummy gate electrode layer may include a polysilicon material. Then, a hard mask is formed on the surface of the dummy gate, and a sidewall is formed on the side of the dummy gate. Optionally, the hard mask (or sidewall) may include one or more of SiNx and SiON.
[0023] Step 2: forming source and drain electrodes electrically connected to the channel region of the fin structure. The specific manufacturing process of step 2 is as follows:
[0024] The device portion of the source-drain electrode region is removed, and the first end surface and the second end surface of the fin structure are exposed. The channel region of the fin structure is located in the device portion, so after the device portion of the source-drain electrode region is removed, the channel region of the fin structure can be exposed, which is convenient for electrical connection with the source-drain electrode. Optionally, the first sacrificial layer in the source-drain electrode region can be removed.
[0025] The first sacrificial layer is removed by an isotropic etch process, and a bottom electrical isolation layer is formed by an atomic layer deposition (ALD) process, and then the bottom electrical isolation layer in the area outside the fin structure is removed. Optionally, the bottom electrical isolation layer may include materials such as SiO2, SiCN, SiON, and SiN.
[0026] A second etch barrier layer is formed on the surface of the sub-fin portion in the source-drain electrode region (in order to distinguish it from the first etch barrier layer, the etch barrier layer here is referred to as the second etch barrier layer). Optionally, the second etch barrier layer may include a Si material doped with one or a combination of B, C, N, and O, and the second etch barrier layer may be manufactured by an epitaxial process or an ion implantation process.
[0027] Etch the portion of the second sacrificial layer exposed on the surface, and form an inner sidewall at the position where the second sacrificial layer is etched. The inner sidewall can isolate the gate and the source-drain electrode formed subsequently to prevent the gate and the source-drain electrode from short-circuiting. Afterwards, deposit a conductive material in the source-drain electrode region to form a source-drain electrode in contact with the first end face or the second end face of the fin structure. Optionally, the source-drain electrode may include polysilicon material, and the source-drain electrode may be manufactured by an epitaxial growth process. Of course, other materials or other processes may also be used to manufacture the source-drain electrode, which is not limited here.
[0028] Step 3: Form a first through hole penetrating the isolation dielectric layer, and fill the first through hole with a conductive material to obtain a power through hole electrically connected to the source and drain electrodes. The specific manufacturing process of step 3 is as follows:
[0029] Remove the film layers such as the dummy gate, hard mask and sidewall, and remove the second sacrificial layer between the channel layers to expose the channel layer to form a suspended channel layer. Optionally, the channel layer can be a nanowire or a nanosheet. A gate dielectric layer and a gate with a high dielectric constant are deposited on the surface of the exposed channel layer so that the gate surrounds each channel layer through the gate dielectric layer. Afterwards, an interlayer dielectric layer is formed on the film layer where the source and drain electrodes are located. The isolation dielectric layer and the interlayer dielectric layer are patterned to obtain a first through hole that penetrates the isolation dielectric layer and part of the interlayer dielectric layer and a second through hole that penetrates part of the interlayer dielectric layer. In the thickness direction of the isolation dielectric layer, the first through hole and the second through hole at least partially overlap. In some cases, the surface of the first semiconductor layer may also be overetched during the etching process, that is, the first through hole may also penetrate part of the first semiconductor layer. Fill the first through hole with a conductive material to obtain a power through hole, and fill the second through hole with a conductive material to obtain a conductive connection portion. The power through hole is electrically connected to the source and drain electrodes through the conductive connection portion. In the thickness direction of the isolation dielectric layer, the power via and the source-drain electrode do not overlap each other, and the electrical connection between the power via and the source-drain electrode can be achieved by providing a conductive connection portion. In a specific implementation, the power via and the conductive connection portion may include the same conductive material, for example, the power via and the conductive connection portion may both include a metal material, and in some cases, the power via and the conductive connection portion may also include different conductive materials, which is not limited here.
[0030] An interconnection layer is formed on the film layer where the interlayer dielectric layer is located. The interconnection layer may include multiple conductive film layers and multiple insulating film layers. The transistor in the semiconductor device may lead out the signal from the front through the interconnection layer. Afterwards, the side of the semiconductor device having the interconnection layer is fixed to the surface of the carrier. For example, the carrier may be bonded to the interconnection layer of the semiconductor device. Of course, other methods may also be used to fix the carrier, which will not be given one by one here.
[0031] Step 4: After forming each film layer in the semiconductor device, the semiconductor device is turned over and the side of the semiconductor device with the substrate is thinned to remove the substrate and expose the end of the power through hole. The specific production process of step 4 is as follows:
[0032] After forming each film layer of the interconnection layer, the semiconductor device is turned over so that the carrier is located under each film layer of the semiconductor device, and the carrier plays the role of supporting each film layer in the semiconductor device. After that, the side of the semiconductor device with the substrate is thinned to remove the substrate and expose the end of the power through hole. During the thinning process, the isolation dielectric layer can be used as a stop layer. In some cases, during the thinning process, after thinning to the surface of the isolation dielectric layer, it can also be slightly thinned to a certain depth to further reduce the aspect ratio of the power through hole.
[0033] When the semiconductor device includes a plurality of fin structures, after thinning the side of the semiconductor device having the substrate, the method may further include:
[0034] Using the second etch barrier layer as a barrier, remove at least part of the sub-fin of the fin structure. An etching process can be used to remove at least part of the sub-fin of the fin structure. During the etching process, the second etch barrier layer is used as a barrier to protect the source and drain electrodes and prevent the source and drain electrodes from being damaged during the etching process. Afterwards, an insulating layer is filled in the through hole formed after removing the sub-fin. During the deposition of the insulating material, some insulating material will be deposited on the surface of the isolation dielectric layer. After the deposition of the insulating layer, a masking process can be used to remove the insulating material on the surface of the isolation dielectric layer to leak out the end of the power through hole. In this way, at least part of the sub-fin of the fin structure can be insulated to prevent the sub-fin from being short-circuited with other conductive components. In the specific implementation, the sub-fin that needs to be insulated can be selected according to actual needs. Of course, if each sub-fin does not have the risk of short-circuiting with other conductive components, the step of insulating the sub-fin can also be omitted.
[0035] In a possible implementation, after connecting the power vias in the semiconductor device to the backside power distribution network, the carrier board may be removed.
[0036] In the method for manufacturing a semiconductor device provided in an embodiment of the present application, after forming each film layer on the front side of the semiconductor device, the semiconductor device is flipped over and a side of the semiconductor device having a substrate is thinned to remove the substrate and expose the end of the power through hole, thereby reducing the depth of the power through hole and the aspect ratio of the power through hole, thereby simplifying the manufacturing process of the power through hole and reducing the complexity of the manufacturing process of the back side of the semiconductor device.
[0037] The above uses the full-surround gate transistor as an example to illustrate the manufacturing method of the semiconductor device provided in the embodiment of the present application. When the transistor is a fin field effect transistor, there is no need to prepare a stacked film layer. The other steps can be implemented with reference to the above-mentioned manufacturing method, and the repeated parts will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;
[0039] Figure 2 for Figure 1 A partial enlarged schematic diagram of (3) in FIG.
[0040] Figure 3 Another partial schematic diagram of a semiconductor device in an embodiment of the present application;
[0041] Figure 4 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present application, Figures 5 to 13 It is a structural schematic diagram corresponding to each step of the manufacturing method in the embodiment of the present application.
[0042] Reference numerals:
[0043] 11-fin structure; 111-sub-fin; 112-device; 12-isolation dielectric layer; 13-source-drain electrode; 14-power through hole; 15-gate; 16-conductive connection; 17-interlayer dielectric layer; 18-gate dielectric layer; 19-interconnection layer; 20-inner side wall; 21-bottom electrical isolation layer; 22-first etch barrier layer; 23-first semiconductor layer; 24-first sacrificial layer; 25-stacked film layer; 251-second semiconductor layer; 252-second sacrificial layer; 26-dummy gate; 27-hard mask; 28-side wall; 29-second etch barrier layer; 30-carrier; S1-first surface; S2-second surface; D1-first end face; D2-second end face; W-channel layer; SD-source-drain electrode region; T1-first through hole; T2-second through hole. DETAILED DESCRIPTION
[0044] In the backside power distribution network solution of the related art, the transistors in the semiconductor device are connected to the backside power distribution network on the back side through power vias, thereby reducing the voltage drop of the power signal, reducing the area of the logic unit of the semiconductor device, improving the performance of the semiconductor device, and reducing the power consumption of the semiconductor device. However, due to the high depth-to-width ratio of the power via, the etching process and deposition process for making the power via are more difficult, and the backside manufacturing process of the semiconductor device is more complicated.
[0045] Based on this, in order to solve the problem in the related art that the etching process and deposition process of making the power through hole are difficult due to the high depth-to-width ratio of the power through hole, and the back side manufacturing process of the semiconductor device is complicated. The embodiment of the present application provides a semiconductor device, a manufacturing method thereof, and an electronic device. The semiconductor device in the embodiment of the present application may include a transistor with a three-dimensional structure, for example, the semiconductor device may include a fin field effect transistor (FinFET) or a gate-all-around (GAA) transistor, etc. The semiconductor device in the embodiment of the present application can be widely used in various electronic devices. For example, the semiconductor device in the embodiment of the present application can be applied to electronic devices such as smart phones, smart TVs, smart TV set-top boxes, smart watches, personal computers (PCs), wearable devices, and smart broadband. In some cases, the semiconductor device in the embodiment of the present application can also be applied to other electronic devices, which will not be given one by one here.
[0046] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.
[0047] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be changed as needed, and the changes are included in the protection scope of this application. The drawings of this application are only used to illustrate the relative position relationship and do not represent the true proportion.
[0048] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application, Figure 1 (1) is a schematic diagram of a top view of a semiconductor device in an embodiment of the present application, Figure 1 (2) in Figure 1 The cross-sectional view of (1) at the dotted line L1, Figure 1 (3) in is Figure 1 The cross-sectional view of (1) at the dotted line L2, Figure 1 (4) in is Figure 1 Schematic diagram of the cross section of (1) at the dotted line L3. Figure 1 As shown, the semiconductor device provided in the embodiment of the present application may include: a fin structure 11, an isolation dielectric layer 12, a source-drain electrode 13, and a power via 14. The semiconductor device in the embodiment of the present application may include one or more fin structures 11, and the isolation dielectric layer 12 may play a supporting and insulating role. When the semiconductor device includes multiple fin structures 11, the isolation dielectric layer 12 may also play a role in separating adjacent fin structures 11. The source-drain electrode 13 is electrically connected to the channel region of the fin structure 11. The source-drain electrode 13 may be a source or drain of a transistor. The source-drain electrode 13 may include polysilicon material or other conductive materials. The semiconductor device in the embodiment of the present application may also include a gate 15. The semiconductor device may include one or more transistors, each of which includes: a fin structure 11, a source and a drain electrically connected to the channel region of the fin structure 11, and a gate 15 covering the channel region of the fin structure 11. By applying a gate voltage to the gate 15, the conduction or cutoff of the transistor can be controlled.
[0049] The isolation dielectric layer 12 includes Figure 1 The fin structure 11 penetrates the isolation dielectric layer 12 in the thickness direction, and the surface on one side of the fin structure 11 is flush with the second surface S2 of the isolation dielectric layer 12, and the other side protrudes from the first surface S1 of the isolation dielectric layer 12. The power through hole 14 penetrates the isolation dielectric layer 12 in the thickness direction, the first end of the power through hole 14 is electrically connected to the source and drain electrode 13, the second end of the power through hole 14 is flush with the second surface of the isolation dielectric layer 12, and the second end of the power through hole 14 is used to be electrically connected to the back side power distribution network. In the embodiment of the present application, the power through hole 14 is formed in the isolation dielectric layer 12 by an etching process, and a conductive material is filled in the through hole by a deposition process. That is, the power through hole 14 includes a conductive material, which can play a role of electrical connection. The power through hole 14 may include a metal material. Of course, the power through hole 14 may also include other conductive materials, which are not limited here.
[0050] In the related art, the power via needs to penetrate the isolation dielectric layer and be embedded to a certain depth of the substrate, resulting in a high depth-to-width ratio of the power via, a high difficulty in the etching process and deposition process of the power via, and a complex backside manufacturing process of the semiconductor device. In the semiconductor device provided in the embodiment of the present application, by removing the substrate on the back side so that the end face of the power via 14 is flush with the second surface S2 of the isolation dielectric layer 12, the depth of the power via 14 can be reduced, and the depth-to-width ratio of the power via 14 can be reduced, thereby simplifying the manufacturing process of the power via 14 and reducing the complexity of the backside manufacturing process of the semiconductor device. In addition, by reducing the depth of the power via 14, the transmission path of the power signal can be shortened, and the voltage drop of the power signal can be reduced, thereby reducing the cut-off current (Ioff) of the semiconductor device and improving the performance of the semiconductor device.
[0051] Continue to refer to Figure 1 The semiconductor device in the embodiment of the present application may further include: a conductive connection portion 16 located on the side of the source / drain electrode 13 away from the isolation dielectric layer 12, and an interlayer dielectric layer 17 located on the side of the first surface S1 of the isolation dielectric layer 12. Figure 1 The conductive connecting portion 16 is located in the interlayer dielectric layer 17. In the thickness direction of the isolation dielectric layer 12, the conductive connecting portion 16 at least partially overlaps with the source-drain electrode 13, and the conductive connecting portion 16 at least partially overlaps with the power supply via 14. The power supply via 14 is electrically connected to the source-drain electrode 13 through the conductive connecting portion 16. In the thickness direction of the isolation dielectric layer 12, the power supply via 14 and the source-drain electrode 13 do not overlap each other. The electrical connection between the power supply via 14 and the source-drain electrode 13 can be achieved by providing the conductive connecting portion 16. In a specific implementation, the power supply via 14 and the conductive connecting portion 16 may include the same conductive material. For example, the power supply via 14 and the conductive connecting portion 16 may both include metal materials. In some cases, the power supply via 14 and the conductive connecting portion 16 may also include different conductive materials, which is not limited here.
[0052] Figure 2 for Figure 1 The partial enlarged schematic diagram of (3) in FIG. Figure 2 As shown, the channel region of the fin structure 11 is in a first direction (eg Figure 2 The fin structure 11 has a first end surface D1 and a second end surface D2 that are oppositely disposed in the y direction (in the y direction), and the first direction y is parallel to the first surface S1 of the isolation dielectric layer 12. The source-drain electrode 13 is in contact with the first end surface D1 or the second end surface D2. Exemplarily, the fin structure 11 may be in contact with the source at the first end surface D1 and in contact with the drain at the second end surface D2.
[0053] Combination Figure 1 and Figure 2In an embodiment of the present application, the fin structure 11 may include: a sub-fin portion 111 and a device portion 112, the sub-fin portion 111 is located inside the isolation dielectric layer 12, the device portion 112 is located on the side of the sub-fin portion 111 away from the isolation dielectric layer 12, and the channel region of the fin structure 11 is located in the device portion 112. The two end surfaces of the device portion 112 that are opposite to each other in the first direction may be the first end surface D1 and the second end surface D2 mentioned above, and the source and drain electrodes 13 are specifically in contact and connected with the end surfaces of the device portion 112. The sub-fin portion 111 may play a role in supporting the device portion 112, so as to facilitate the gate 15 to surround the device portion 112, so as to realize a transistor with a three-dimensional structure. In a specific implementation, adjacent fin structures 11 may share the same sub-fin portion 111, for example Figure 2 In the figure, three adjacent fin structures 11 share the same sub-fin 111. The sub-fin 111 may include semiconductor materials such as Si and Ge. In some cases, in order to avoid short circuit between the sub-fin 111 and other conductive components, the sub-fin 111 may also be set as an insulating material. The material of the sub-fin 111 may be selected according to actual needs and is not limited here.
[0054] Continue to refer to Figure 2 In some embodiments of the present application, the semiconductor device may include a gate-all-around (GAA) transistor. Specifically, the device portion 112 may include: a plurality of channel layers W stacked together, Figure 2 In the figure, the device part 112 includes three layers of channel layers W as an example for illustration, and the number of layers of the channel layer W can be set according to actual needs. The semiconductor device can also include: a gate dielectric layer 18, a gate 15 surrounds each channel layer W through the gate dielectric layer 18, and the area of each channel layer W surrounded by the gate 15 is the channel region of the fin structure 11. In this way, a three-dimensional structure in which the gate 15 surrounds the channel layer W can be formed, and the coverage area of the gate 15 and the channel region of the fin structure 11 is large, which can increase the control ability of the gate 15 on the transistor and improve the performance of the semiconductor device. Exemplarily, the channel layer W can be a nanosheet or a nanowire.
[0055] Combination Figure 1 and Figure 2In a specific implementation, the semiconductor device may further include: an inner spacer 20. The inner spacer 20 may be located between adjacent channel layers W, or the inner spacer 20 may be located between the first or last channel layer W and other film layers. The inner spacer 20 may isolate the gate 15 from the source-drain electrode 13 to prevent the gate 15 from being short-circuited with the source-drain electrode 13. In addition, in order to improve the performance of the semiconductor device, a bottom dielectric isolation layer (Bottom dielectric isolation, BDI) 21 may be provided between the device portion 112 and the sub-fin portion 111. In a thickness direction perpendicular to the isolation dielectric layer 12, the gate 15 (or the device portion 112) and the bottom dielectric isolation layer 21 have an overlapping region. In this way, the leakage current of the transistor may be reduced by the isolation effect of the bottom dielectric isolation layer 21.
[0056] Figure 3 is another partial schematic diagram of a semiconductor device in an embodiment of the present application, Figure 3 The cross section shown is a cross section of the semiconductor device in the xz plane, and the direction in which the first end surface of the fin structure points to the second end surface is perpendicular to the xz plane, that is, Figure 3 The cross section shown is Figure 1 The perspective of (4) is the same. Figure 3 As shown, in some other embodiments of the present application, the semiconductor device may include a fin field effect transistor (Fin FET), specifically, the semiconductor device may further include: a gate dielectric layer 18, a gate 15 surrounding the top surface of the device portion 112 and two side surfaces connected to the top surface through the gate dielectric layer 18, the top surface is the surface of the device portion 112 on the side of the back ion fin portion, and the area of the device portion 112 covered by the gate 15 is the channel region of the fin structure 11. In this way, a three-dimensional structure in which the gate 15 surrounds the channel region on three sides can be formed, and the coverage area of the gate 15 and the channel region of the fin structure 11 is large, which can increase the control capability of the gate 15 on the transistor and improve the performance of the semiconductor device.
[0057] In the embodiments of the present application, the transistor in the semiconductor device is a full-surround gate transistor as an example for explanation. When the transistor is a fin field effect transistor, the embodiment in which the transistor is a full-surround gate transistor can be referred to, and the repeated parts will not be repeated.
[0058] like Figure 1As shown, the semiconductor device in the embodiment of the present application may also include: an interconnection layer 19 located on the side of the gate 15 away from the isolation dielectric layer 12, and the interconnection layer 19 may include multiple conductive film layers and multiple insulating film layers. The transistor in the semiconductor device can lead the signal out from the front through the interconnection layer 19. In the embodiment of the present application, the transistor is connected to the back side power distribution network through the power via 14, and the power supply network does not need to occupy the space of the front interconnection layer 19, which can reduce the area of the logic unit of the semiconductor device and improve the density of the semiconductor device. In addition, the power via 14 in the embodiment of the present application has a small depth-to-width ratio, a short transmission path of the power signal, and a small voltage drop of the power signal, so that the performance of the semiconductor device is better.
[0059] Based on the same technical concept, an embodiment of the present application also provides an electronic device, and the electronic device in the embodiment of the present application may include: any of the above-mentioned semiconductor devices and a back-side power distribution network, and the semiconductor device is electrically connected to the back-side power distribution network through a power through hole. Since the depth-to-width ratio of the power through hole in the above-mentioned semiconductor device is relatively small, the process complexity of manufacturing the above-mentioned semiconductor device is low, and the performance of the semiconductor device is good, so the process complexity of the electronic device including the above-mentioned semiconductor device is also low, and the performance of the electronic device is also good.
[0060] Based on the same technical concept, an embodiment of the present application provides a method for manufacturing a semiconductor device. Figure 4 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present application, Figures 5 to 13 Schematic diagram of the structure corresponding to each step of the manufacturing method in the embodiment of the present application. Figures 4 to 13 , the method for manufacturing a semiconductor device provided in an embodiment of the present application may include:
[0061] S101, forming a fin structure and an isolation dielectric layer on the substrate, so that the fin structure penetrates the isolation dielectric layer in the thickness direction and protrudes from the first surface of the isolation dielectric layer, the first surface being the surface of the isolation dielectric layer facing away from the substrate. The specific manufacturing process of step S101 is as follows:
[0062] Reference Figure 5, a substrate 10 is provided, and the substrate 10 may include semiconductor materials such as Si and Ge. A first etch stop layer (ESL) 22 and a first semiconductor layer 23 may be provided on the substrate 10, and the first etch stop layer 22 may include materials such as SiGe and SiO2, and the first semiconductor layer 23 may include semiconductor materials such as Si and Ge. A first sacrificial layer 24 may be epitaxially grown on the first semiconductor layer 23, and the first sacrificial layer 24 may include materials such as SiGe, Si, SiGe, Si, SiGe, and Si. Afterwards, multiple layers of second semiconductor layers 251 and multiple layers of second sacrificial layers 252 are alternately epitaxially grown on the first sacrificial layer 24 to obtain a stacked film layer 25. Figure 5 In the figure, the stacked film layer 25 includes three layers of second semiconductor layers 251 and three layers of second sacrificial layers 252. In the specific implementation, the number of layers of the second semiconductor layer 251 and the second sacrificial layer 252 can be set according to actual needs, and the number of layers of the second semiconductor layer 251 and the second sacrificial layer 252 can be the same or different, which is not limited here. The second semiconductor layer 251 can include semiconductor materials such as Si and Ge, and the second sacrificial layer 252 can include materials with relatively high etching selectivity such as SiGe.
[0063] Reference Figure 6 , Figure 6 (1) is a schematic diagram of a top view of a semiconductor device in an embodiment of the present application, Figure 6 (2) in Figure 6 The cross-sectional view of (1) at the dotted line L1, Figure 6 (3) in is Figure 6 The cross-sectional view of (1) at the dotted line L2, Figure 6 (4) in is Figure 6(1) is a schematic cross-sectional view at the dotted line L3. The stacked film layer 25, the first sacrificial layer 24 and the first semiconductor layer 23 are patterned to obtain one or more fin structures 11. Each fin structure 11 may include: a sub-fin portion 111 and a device portion 112, the sub-fin portion 111 is obtained by patterning the first semiconductor layer 23, and the device portion 112 is obtained by patterning the stacked film layer 25. Specifically, the device portion 112 may include: a plurality of stacked and alternately arranged channel layers W and a plurality of second sacrificial layers 252, the channel layer W is obtained by patterning the second semiconductor layer 251, and the second sacrificial layer 252 needs to be removed later. After the above-mentioned patterning process, the area of the first semiconductor layer 23 other than each fin structure 11 is not completely removed, and a shallow trench structure is formed between adjacent sub-fin portions 111. Then, an isolation dielectric layer 12 is formed in the area outside each fin structure 11 on the first semiconductor layer 23, so that the isolation dielectric layer 12 is filled in the shallow trench structure, so that the fin structure 11 passes through the isolation dielectric layer 12 in the thickness direction and protrudes from the first surface S1 of the isolation dielectric layer 12. The isolation dielectric layer 12 can play a supporting and insulating role. When the semiconductor device includes a plurality of fin structures 11, the isolation dielectric layer 12 can also play a role in separating adjacent fin structures 11. The first surface S1 of the isolation dielectric layer 12 can be substantially flush with the surface of the sub-fin 111, or the first surface S1 of the isolation dielectric layer 12 can be substantially flush with the surface of the first sacrificial layer 24. Optionally, the isolation dielectric layer 12 can include one or more of SiO2, SiON, and SiNx.
[0064] Afterwards, a dummy gate 26 is formed on the fin structure 11 and the isolation dielectric layer 12. The dummy gate 26 may surround the top surface and two side surfaces of the device portion 112, that is, the dummy gate 26 may surround the device portion 112 on three sides. The dummy gate 26 may include a dummy gate electrode layer and a dummy insulating layer disposed between the dummy gate electrode layer and the device portion 112. Optionally, the dummy gate electrode layer may include a polysilicon material. Then, a hard mask 27 is formed on the surface of the dummy gate 26, and a sidewall 28 is formed on the side of the dummy gate 26. Optionally, the hard mask 27 (or sidewall 28) may include one or more of SiNx and SiON.
[0065] S102, forming source and drain electrodes electrically connected to the channel region of the fin structure. The specific manufacturing process of step S102 is as follows:
[0066] Reference Figure 7 , Figure 7 (1) is a schematic diagram of a top view of a semiconductor device in an embodiment of the present application, Figure 7 (2) in Figure 7 The cross-sectional view of (1) at the dotted line L1, Figure 7 (3) in is Figure 7The cross-sectional view of (1) at the dotted line L2, Figure 7 (4) in is Figure 7 Schematic cross-sectional view of (1) at the dotted line L3 in FIG. The device portion 112 of the source-drain electrode region SD is removed, and the first end surface D1 and the second end surface D2 of the fin structure 11 are exposed. The channel region of the fin structure 11 is located in the device portion 112. Therefore, after the device portion 112 of the source-drain electrode region SD is removed, the channel region of the fin structure 11 can be exposed, which is convenient for electrical connection with the source-drain electrode. Optionally, the first sacrificial layer 24 of the source-drain electrode region SD can be removed.
[0067] Reference Figure 8 , Figure 8 (1) is a schematic diagram of a top view of a semiconductor device in an embodiment of the present application, Figure 8 (2) in Figure 8 The cross-sectional view of (1) at the dotted line L1, Figure 8 (3) in is Figure 8 The cross-sectional view of (1) at the dotted line L2, Figure 8 (4) in is Figure 8 1 is a cross-sectional schematic diagram at the dotted line L3 of (1). The first sacrificial layer 24 is removed by an isotropic etch process, and a bottom electrical isolation layer 21 is formed by an atomic layer deposition (ALD) process, and then the bottom electrical isolation layer 21 in the area outside the fin structure 11 is removed. Optionally, the bottom electrical isolation layer 21 may include materials such as SiO2, SiCN, SiON, and SiN.
[0068] Reference Fig. 9 , Fig. 9 (1) is a schematic diagram of a top view of a semiconductor device in an embodiment of the present application, Fig. 9 (2) in Fig. 9 The cross-sectional view of (1) at the dotted line L1, Fig. 9 (3) in is Fig. 9 The cross-sectional view of (1) at the dotted line L2, Fig. 9 (4) in is Fig. 9 A second etch stop layer 29 is formed on the surface of the sub-fin 111 of the source-drain electrode region SD (in order to distinguish it from the first etch stop layer, the etch stop layer here is referred to as the second etch stop layer). Optionally, the second etch stop layer 29 may include a Si material doped with one or a combination of B, C, N, and O, and the second etch stop layer 29 may be manufactured by an epitaxial process or an ion implantation process.
[0069] Reference Fig.10 , Fig.10(1) is a schematic diagram of a top view of a semiconductor device in an embodiment of the present application, Fig.10 (2) in Fig.10 The cross-sectional view of (1) at the dotted line L1, Fig.10 (3) in is Fig.10 The cross-sectional view of (1) at the dotted line L2, Fig.10 (4) in is Fig.10 Schematic cross-sectional view of (1) at the dotted line L3 in FIG. The portion of the second sacrificial layer 252 exposed on the surface is etched, and an inner sidewall 20 is formed at the position where the second sacrificial layer 252 is etched. The inner sidewall 20 can isolate the gate 15 and the source-drain electrode 13 formed subsequently to prevent the gate 15 from being short-circuited with the source-drain electrode 13. Thereafter, a conductive material is deposited in the source-drain electrode region to form a source-drain electrode 13 in contact with the first end face or the second end face of the fin structure 11. Optionally, the source-drain electrode 13 may include a polysilicon material, and the source-drain electrode 13 may be manufactured by an epitaxial growth process. Of course, the source-drain electrode 13 may also be manufactured by other materials or other processes, which are not limited here.
[0070] S103, forming a first through hole penetrating the isolation dielectric layer, and filling the first through hole with a conductive material to obtain a power through hole electrically connected to the source and drain electrodes. The specific manufacturing process of step S103 is as follows:
[0071] Continue to refer to Fig.10, remove the film layers such as the dummy gate, the hard mask and the sidewall, and remove the second sacrificial layer 252 between the channel layers W to expose the channel layer W to form a suspended channel layer W. Optionally, the channel layer W can be a nanowire or a nanosheet. A gate dielectric layer 18 and a gate 15 with a high dielectric constant are deposited on the surface of the exposed channel layer W so that the gate 15 surrounds each channel layer W through the gate dielectric layer 18. Afterwards, an interlayer dielectric layer 17 is formed on the film layer where the source and drain electrodes 13 are located. The isolation dielectric layer 12 and the interlayer dielectric layer 17 are patterned to obtain a first through hole T1 penetrating the isolation dielectric layer 12 and a portion of the interlayer dielectric layer 17 and a second through hole T2 penetrating a portion of the interlayer dielectric layer 17. In the thickness direction of the isolation dielectric layer 12, the first through hole T1 and the second through hole T2 at least partially overlap. In some cases, the surface of the first semiconductor layer 23 may also be overetched during the etching process, that is, the first through hole T1 may also penetrate a portion of the first semiconductor layer 23. The first through hole T1 is filled with a conductive material to obtain a power through hole 14, and the second through hole T2 is filled with a conductive material to obtain a conductive connection portion 16. The power through hole 14 is electrically connected to the source-drain electrode 13 through the conductive connection portion 16. In the thickness direction of the isolation dielectric layer 12, the power through hole 14 and the source-drain electrode 13 do not overlap each other, and the electrical connection between the power through hole 14 and the source-drain electrode 13 can be achieved by providing the conductive connection portion 16. In a specific implementation, the power through hole 14 and the conductive connection portion 16 may include the same conductive material, for example, the power through hole 14 and the conductive connection portion 16 may both include a metal material. In some cases, the power through hole 14 and the conductive connection portion 16 may also include different conductive materials, which is not limited here.
[0072] Reference Fig.11 , Fig.11 (1) is a schematic diagram of a top view of a semiconductor device in an embodiment of the present application, Fig.11 (2) in Fig.11 The cross-sectional view of (1) at the dotted line L1, Fig.11 (3) in is Fig.11 The cross-sectional view of (1) at the dotted line L2, Fig.11 (4) in is Fig.11 Schematic cross-sectional view of (1) at the dotted line L3. An interconnection layer 19 is formed on the film layer where the interlayer dielectric layer 17 is located. The interconnection layer 19 may include multiple conductive film layers and multiple insulating film layers. The transistor in the semiconductor device may lead out the signal from the front through the interconnection layer 19. Afterwards, the side of the semiconductor device having the interconnection layer 19 is fixed to the surface of the carrier 30. For example, the carrier 30 may be bonded to the interconnection layer 19 of the semiconductor device. Of course, other methods may also be used to fix the carrier 30, which will not be given one by one here.
[0073] S104, after forming each film layer in the semiconductor device, flip the semiconductor device and perform a thinning process on the side of the semiconductor device with the substrate to remove the substrate and expose the end of the power through hole. The specific production process of step S104 is as follows:
[0074] Reference Fig.12 , Fig.12 (1) is a schematic diagram of a top view of a semiconductor device in an embodiment of the present application, Fig.12 (2) in Fig.12 The cross-sectional view of (1) at the dotted line L1, Fig.12 (3) in is Fig.12 The cross-sectional view of (1) at the dotted line L2, Fig.12 (4) in is Fig.12 1 is a cross-sectional schematic diagram at the dotted line L3 in (1). After forming the film layers of the interconnection layer 19, the semiconductor device is flipped over so that the carrier 30 is located under the film layers of the semiconductor device, and the carrier 30 plays the role of supporting the film layers in the semiconductor device. Afterwards, the side of the semiconductor device with the substrate is thinned to remove the substrate and expose the end of the power through hole 14. During the thinning process, the isolation dielectric layer 12 can be used as a stop layer. In some cases, during the thinning process, after thinning to the surface of the isolation dielectric layer 12, it can also be slightly thinned to a certain depth to further reduce the aspect ratio of the power through hole 14.
[0075] Reference Fig.13 , Fig.13 (1) is a schematic diagram of a top view of a semiconductor device in an embodiment of the present application, Fig.13 (2) in Fig.13 The cross-sectional view of (1) at the dotted line L1, Fig.13 (3) in is Fig.13 The cross-sectional view of (1) at the dotted line L2, Fig.13 (4) in is Fig.13 When the semiconductor device includes a plurality of fin structures 11, after the semiconductor device is thinned on the side with the substrate, the following may also be included:
[0076] The second etching barrier layer 29 is used as a barrier to remove at least part of the sub-fin 111 of the fin structure 11. The etching process can be used to remove at least part of the sub-fin 111 of the fin structure 11. During the etching process, the second etching barrier layer 29 is used as a barrier to protect the source and drain electrodes 13 and prevent the source and drain electrodes 13 from being damaged during the etching process. After that, an insulating layer is filled in the through hole formed after the sub-fin 111 is removed. During the deposition of the insulating material, some insulating material will be deposited on the surface of the isolation dielectric layer 12. After the deposition of the insulating layer, a masking process can be used to remove the insulating material on the surface of the isolation dielectric layer 12 to leak out the end of the power through hole 14. In this way, at least part of the sub-fin 111 of the fin structure 11 can be insulated to prevent the sub-fin 111 from being short-circuited with other conductive components. In the specific implementation, the sub-fin 111 that needs to be insulated can be selected according to actual needs. Of course, if there is no risk of short-circuiting with other conductive components in each sub-fin 111, the step of insulating the sub-fin 111 can also be omitted.
[0077] In a possible implementation, after the power vias in the semiconductor device are connected to the backside power distribution network, the carrier board 30 may be removed.
[0078] In the method for manufacturing a semiconductor device provided in an embodiment of the present application, after forming each film layer on the front side of the semiconductor device, the semiconductor device is flipped over and a side of the semiconductor device having a substrate is thinned to remove the substrate and expose the end of the power through hole, thereby reducing the depth of the power through hole and the aspect ratio of the power through hole, thereby simplifying the manufacturing process of the power through hole and reducing the complexity of the manufacturing process of the back side of the semiconductor device.
[0079] The above uses the full-surround gate transistor as an example to illustrate the manufacturing method of the semiconductor device provided in the embodiment of the present application. When the transistor is a fin field effect transistor, there is no need to prepare a stacked film layer. The other steps can be implemented with reference to the above-mentioned manufacturing method, and the repeated parts will not be repeated.
[0080] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.
[0081] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A semiconductor device, characterized in that: include: Fin structure, isolation dielectric layer, source and drain electrodes, and power vias; The isolation dielectric layer includes a first surface and a second surface that are arranged opposite to each other in the thickness direction; The fin structure penetrates the isolation dielectric layer in the thickness direction, and a surface on one side of the fin structure is flush with the second surface of the isolation dielectric layer, and the other side of the fin structure protrudes from the first surface of the isolation dielectric layer; The source-drain electrode is electrically connected to the channel region of the fin structure; The power through hole penetrates the isolation dielectric layer in the thickness direction, the first end of the power through hole is electrically connected to the source and drain electrodes, the second end of the power through hole is flush with the second surface of the isolation dielectric layer, and the second end of the power through hole is used to be electrically connected to the back side power distribution network.
2. The semiconductor device according to claim 1, wherein Also includes: a conductive connection portion located on a side of the source / drain electrode facing away from the isolation dielectric layer, and an interlayer dielectric layer located on a side of the first surface of the isolation dielectric layer; The power through hole penetrates the isolation dielectric layer and part of the interlayer dielectric layer in the thickness direction, and at least part of the conductive connection part is located in the interlayer dielectric layer; In the thickness direction of the isolation dielectric layer, the conductive connection portion at least partially overlaps with the source-drain electrode, and the conductive connection portion at least partially overlaps with the power through hole; The power through hole is electrically connected to the source-drain electrode through the conductive connection portion.
3. The semiconductor device according to claim 1, wherein The channel region of the fin structure has a first end surface and a second end surface that are oppositely arranged in a first direction, and the first direction is parallel to the first surface of the isolation dielectric layer; The source-drain electrode is in contact with and connected to the first end surface or the second end surface.
4. The semiconductor device according to claim 3, characterized in that The fin structure comprises: a sub-fin portion and a device portion, wherein the sub-fin portion is located inside the isolation dielectric layer, and the device portion is located on a side of the sub-fin portion away from the isolation dielectric layer; A channel region of the fin structure is located within the device portion.
5. The semiconductor device according to claim 4, wherein: Also includes: A gate and a gate dielectric layer; The gate surrounds the top surface of the device portion and two side surfaces connected to the top surface through the gate dielectric layer, and the top surface is the surface of the device portion facing away from the sub-fin portion; The region of the device portion covered by the gate is the channel region of the fin structure.
6. The semiconductor device according to claim 4, wherein: Also includes: a gate and a gate dielectric layer; The device part comprises: a plurality of channel layers stacked and arranged, wherein the gate surrounds each of the channel layers through the gate dielectric layer; The area of each channel layer surrounded by the gate is the channel region of the fin structure.
7. The semiconductor device according to claim 6, wherein: The channel layer is a nanosheet or a nanowire.
8. The semiconductor device according to claim 5 or 6, characterized in that Also includes: An interconnection layer is located on a side of the gate away from the isolation dielectric layer.
9. An electronic device, characterized in that: include: The semiconductor device and backside power distribution network according to any one of claims 1 to 8, wherein the semiconductor device is electrically connected to the backside power distribution network through a power through hole.
10. A method for manufacturing a semiconductor device, characterized in that: include: forming a fin structure and an isolation dielectric layer on the substrate, so that the fin structure penetrates the isolation dielectric layer in a thickness direction and protrudes from a first surface of the isolation dielectric layer; The first surface is a surface of the isolation dielectric layer facing away from the substrate; forming a source-drain electrode electrically connected to the channel region of the fin structure; Forming a first through hole penetrating the isolation dielectric layer, and filling the first through hole with a conductive material to obtain a power through hole electrically connected to the source and drain electrodes; After forming each film layer in the semiconductor device, the semiconductor device is turned over, and a thinning process is performed on a side of the semiconductor device having the substrate to remove the substrate and expose the end of the power through hole.
11. The method according to claim 10, characterized in that: The fin structure comprises: a sub-fin portion and a device portion, wherein the sub-fin portion is located inside the isolation dielectric layer, and the sub-fin portion is located on a side of the sub-fin portion away from the isolation dielectric layer; and a channel region of the fin structure is located inside the device portion; Before forming the source-drain electrode electrically connected to the channel region of the fin structure, the method further includes: Removing the device portion of the source-drain electrode region to expose the first end surface and the second end surface of the fin structure; forming an etch stop layer on the surface of the sub-fin portion in the source-drain electrode region; The forming of the source-drain electrode electrically connected to the channel region of the fin structure specifically includes: Depositing a conductive material in the source-drain electrode region to form the source-drain electrode in contact with the first end surface or the second end surface of the fin structure; When the semiconductor device includes a plurality of the fin structures, after thinning the side of the semiconductor device having the substrate, the method further includes: Using the etching barrier layer as a barrier, at least a portion of the sub-fin portion of the fin structure is removed, and an insulating layer is filled in the through hole formed after the sub-fin portion is removed.
12. The production method according to claim 10 or 11, characterized in that: After forming the source-drain electrode electrically connected to the channel region of the fin structure, the method further includes: forming an interlayer dielectric layer on the film layer where the source and drain electrodes are located; The forming of a first through hole penetrating the isolation dielectric layer and filling the first through hole with a conductive material to obtain a power through hole electrically connected to the source and drain electrodes specifically includes: The isolation dielectric layer and the interlayer dielectric layer are patterned to obtain a first through hole penetrating the isolation dielectric layer and a portion of the interlayer dielectric layer and a second through hole penetrating a portion of the interlayer dielectric layer; in a thickness direction of the isolation dielectric layer, the first through hole at least partially overlaps with the second through hole; The first through hole is filled with a conductive material to obtain the power through hole, and the second through hole is filled with a conductive material to obtain a conductive connecting portion; the power through hole is electrically connected to the source-drain electrode through the conductive connecting portion.