Planar gate dual-control electrode 4H-SiC composite transistor structure and preparation method thereof

Abstract

The invention discloses a planar gate dual-control electrode 4H-SiC composite transistor structure which comprises a plurality of cell structures connected in parallel, each cell structure comprises an n buffer layer on a 4H-SiC n + substrate, an n-drift region, an n carrier expansion layer and p body regions in the two sides of the n carrier expansion layer, each p body region is of a mesa structure, an n + source region and a p + region are arranged in the upper part and the lower part, and a gap is formed between the n + source region and the p + region; gate oxide layers and polycrystalline silicon layers are arranged on the surfaces of the n carrier expansion layer, the p body regions on the two sides and part of the n + source region; a plane grid G is arranged on the surface of the polycrystalline silicon layer; a source S is arranged on the surface of the n + source region; a base B is arranged on the surface of the p + region; a drain electrode D is arranged on the back surface of the 4H-SiC n + substrate; the cellular structure is in bilateral symmetry with the planar grid G as the axis, equivalently, the VDMOS and the BJT are connected in parallel, the VDMOS is located in the center, and the BJT is located on the outer side. According to the invention, the conduction loss of the device can be reduced, the anti-short-circuit capability is improved, and the influence of a body diode is eliminated.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductor devices, and in particular relates to a planar gate double-control electrode 4H-SiC composite transistor structure and a preparation method thereof. Background Art

[0002] 4H-SiC power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide Semiconductor Field-Effect Transistor, abbreviated as MOS) is a power switch. It has been applied in new energy vehicles, photovoltaic inverters, smart grid systems and other fields due to its voltage control and advantages such as fast switching speed and high frequency. In comparison, the existing power MOSFET mostly adopts the planar gate MOSFET (VDMOS) structure because the planar gate structure is simpler than the trench gate structure. However, due to the presence of the JFET (Junction Field-Effect Transistor) region, its on-resistance is relatively large. In order to reduce its on-resistance, the existing 4H-SiC VDMOS structure usually performs a high concentration of n-type doping above the n-drift region of the traditional VDMOS to form a carrier expansion layer (CSL) to reduce the resistance of the JFET region and expand the current distribution of the n-drift region.

[0003] Despite the above structural improvements, the existing 4H-SiC VDMOS still has many disadvantages in practical applications, such as large on-resistance, poor short-circuit resistance, too fast rise in turn-off dv / dt, the presence of a body diode, etc., resulting in the 4H-SiC power MOSFET device still failing to meet application requirements in applications with high requirements for conduction loss and short-circuit capability. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a planar gate dual-control electrode 4H-SiC composite transistor structure and a preparation method. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] In a first aspect, an embodiment of the present invention provides a planar gate dual-control electrode 4H-SiC composite transistor structure, comprising a plurality of parallel cell structures, wherein the cell structure comprises:

[0006] An n buffer layer, an n-drift region, an n carrier expansion layer, and a p body region are sequentially arranged on a 4H-SiC n+ substrate, wherein the p body region on each side is a table structure, and an n+ source region and a p+ region are respectively arranged in the upper and lower parts of the table structure, and the n+ source region and the p+ region have a spacing; a gate oxide layer and a polysilicon layer are arranged from bottom to top on the upper surfaces of the n carrier expansion layer, the p body regions on both sides of the n carrier expansion layer, and the adjacent n+ source region; a planar gate G is arranged on the surface of the polysilicon layer; a source S is arranged on the surface of the n+ source region; a base B is arranged on the surface of the p+ region; a drain D is arranged on the back of the 4H-SiC n+ substrate; wherein the planar gate G and the base B are both control electrodes; each cell structure is symmetrical with the central planar gate G as an axis, which is equivalent to the parallel connection of a VDMOS and a BJT, wherein the VDMOS is located in the center and the BJT is located on the outside.

[0007] In one embodiment of the present invention, in the cell structure, the n-drift region of VDMOS is equivalent to the n-collector region of BJT, the p-body region of VDMOS is equivalent to the p-base region of BJT, the n+ source region of VDMOS is equivalent to the n+ emitter region of BJT, and the 4H-SiC n+ substrate of VDMOS is equivalent to the collector ohmic contact region of BJT; at the same time, the source S of VDMOS is the emitter E of BJT, and the drain D of VDMOS is the collector C of BJT.

[0008] In one embodiment of the present invention, when the planar gate dual-control electrode 4H-SiC composite transistor structure is turned on, a gate voltage is applied to the planar gate G, a base current is applied to the base B, and VDMOS and BJT are triggered to turn on at the same time, so that the n-drift region produces a conductivity modulation effect, and the entire device operates in a bipolar mode.

[0009] In one embodiment of the present invention, the width W of the n+ source region is n+ is 5 to 7 μm; the thickness D of the n+ source region n+ is 0.3 to 0.5 μm; + The distance S between the source region and the p+ region B 3~5μm.

[0010] In a second aspect, an embodiment of the present invention provides a method for preparing a planar gate dual-control electrode 4H-SiC composite transistor structure, the method comprising:

[0011] Using epitaxial process on 4H-SiC n+ substrate, n buffer layer, n-drift region and n carrier expansion layer are grown in sequence;

[0012] Aluminum ions are implanted into local areas of the top layer on both sides of the n-carrier extension layer to form a p-body region;

[0013] Nitrogen ion implantation is performed in the local area of ​​the p-body region on both sides close to the surface of the n-carrier extension layer to form an n+ source region;

[0014] Etching the p-body region outside the n+ source region by using an etching process to form a mesa structure of the n+ source region and the p-body region; performing ion implantation on the outer surface edge region of the p-body region having a distance from the n+ source region to form a p+ region;

[0015] On the upper surfaces of the n carrier extension layer, the p body regions on both sides and the adjacent part of the n+ source region, a gate oxide layer is prepared by thermal oxidation, and polysilicon is deposited on the surface of the gate oxide layer and heavily doped;

[0016] A planar gate G is prepared on the obtained polysilicon layer, a source S is prepared in the n+ source region, a base B is prepared on the surface of the p+ region, and a drain D is prepared on the back side of the 4H-SiC n+ substrate.

[0017] In one embodiment of the present invention, the step of implanting aluminum ions into local regions of the top layer on both sides of the n carrier extension layer to form a p body region includes:

[0018] A 30-50nm silicon dioxide covering film is deposited on the upper surface of the current crystal, and then under the mask of photoresist, aluminum ions are injected multiple times at room temperature into the local surface areas on both sides of the n-carrier expansion layer to form a p-body region.

[0019] In one embodiment of the present invention, the step of implanting nitrogen ions in a local area near the surface of the n carrier extension layer in the p-body region on both sides to form an n+ source region includes:

[0020] The silicon dioxide film on the upper surface of the current crystal is removed, a polysilicon masking film is deposited, and a polysilicon mesa is formed by photolithography;

[0021] Deposit 800nm ​​to 1000nm of silicon dioxide film on the surface of the current crystal, and then perform dry etching to form oxide sidewalls;

[0022] A 30-50nm silicon dioxide covering film is deposited on the upper surface of the current crystal. Under the mask of the oxide sidewalls, multiple nitrogen ion implantations are performed on the local area of ​​the top layer in the p-body region on each side at 500°C to form an n+ source region.

[0023] In one embodiment of the present invention, the step of etching the p-body region outside the n+ source region by an etching process to form a mesa structure of the n+ source region and the p-body region; and performing ion implantation on the outer surface edge region of the p-body region having a distance from the n+ source region to form the p+ region comprises:

[0024] The silicon dioxide film on the current crystal surface is removed, a silicon dioxide masking film is re-deposited, and the p-body region outside the n+ source region on the crystal surface is dry-etched to form a mesa structure of the n+ source region and the p-body region; wherein the over-etching of the n+ source region is controlled within 10% of its depth;

[0025] The silicon dioxide masking film on the upper surface of the current crystal is removed, and the upper surface is subjected to NO / N2O nitridation treatment to remove the damage caused by surface etching to reduce the interface state;

[0026] A 30-50 nm silicon dioxide covering film is deposited on the upper surface of the current crystal, and a polysilicon masking film is deposited. By etching the polysilicon film, an injection window for the p+ region is formed at the outer surface edge area of ​​the p-body region with a spacing from the n+ source region. Then, aluminum ion implantation is performed at 500°C to form a p+ region. The doping concentration of the p+ region is 3×10 19 ~5×10 19 cm -3 .

[0027] The silicon dioxide covering film and polysilicon masking film on the current crystal surface are removed, and a carbon film is deposited. High-temperature annealing is performed under the protection of the carbon film to activate impurities, eliminate damage caused by ion implantation, and prevent impurities from overflowing; wherein, the temperature of the high-temperature annealing is 1700°C.

[0028] In one embodiment of the present invention, a gate oxide layer is prepared by thermal oxidation on the upper surfaces of the n carrier extension layer, the p body regions on both sides and the adjacent part of the n+ source region, and polysilicon is deposited on the surface of the gate oxide layer and heavily doped, including:

[0029] The carbon film on the surface of the current crystal is removed, and high-temperature thermal oxidation is performed to form a gate oxide layer, and then polysilicon is deposited and heavily doped, and then etched to form a polysilicon layer; the temperature used for high-temperature thermal oxidation is 1250°C; the doping concentration of polysilicon is 5×10 19 cm -3 above.

[0030] Beneficial effects of the present invention:

[0031] The planar gate dual control electrode 4H-SiC composite transistor structure of the embodiment of the present invention introduces BJT on the basis of the existing planar gate 4H-SiCMOSFET (VDMOS) structure, connects the two in parallel, adopts dual control electrodes, and controls the opening and closing of MOS and BJT by adjusting the voltage or current of the control electrodes respectively, which can reduce the on-resistance and conduction loss of the device, increase the short-circuit withstand time, improve the short-circuit resistance, and eliminate the influence of the body diode on the device characteristics, thereby meeting the application requirements of power switching devices.

[0032] Furthermore, the manufacturing process of the planar gate dual-control electrode 4H-SiC composite transistor structure of the embodiment of the present invention is compatible with the existing VDMOS process. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of the existing 4H-SiC VDMOS cell structure;

[0034] Figure 2 Schematic diagram of a planar gate dual control electrode 4H-SiC composite transistor (P-DCT) cell structure provided by an embodiment of the present invention;

[0035] Figure 3 is an equivalent circuit of the P-DCT cell structure provided by an embodiment of the present invention;

[0036] Figure 4 is the driving signal control timing applied by the P-DCT double control poles of the embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of the carrier transport trajectory in the initial stage of the opening of the existing 4H-SiC VDMOS;

[0038] Figure 6 Schematic diagram of carrier transport trajectory in the initial stage of P-DCT opening according to an embodiment of the present invention;

[0039] Figure 7 1 is a comparison curve of the breakdown characteristics of the P-DCT of the embodiment of the present invention and the existing 4H-SiC VDMOS;

[0040] Figure 8 1 is a comparison curve of the on-state characteristics of the P-DCT of the embodiment of the present invention and the existing 4H-SiC VDMOS;

[0041] Fig. 9 1 is a transfer characteristic comparison curve between the P-DCT of the embodiment of the present invention and the existing 4H-SiC VDMOS;

[0042] Fig.10 1 is a comparison curve of turn-on characteristics of the P-DCT of the embodiment of the present invention and the existing 4H-SiC VDMOS under resistive load;

[0043] Fig.11 1 is a comparison curve of turn-off characteristics of the P-DCT of the embodiment of the present invention and the existing VDMOS under resistive load;

[0044] Fig.12 1 is a comparison curve of the turn-off characteristics of the P-DCT of the embodiment of the present invention and the existing VDMOS under inductive load;

[0045] Fig.131 is a short-circuit characteristic comparison curve of the P-DCT of the embodiment of the present invention and the existing 4H-SiC VDMOS;

[0046] Fig.14 The P-DCT of the embodiment of the present invention has different n+ region widths W. n+ The conduction characteristic comparison curve diagram;

[0047] Fig.15 The P-DCT of the embodiment of the present invention has different n+ region thickness D n+ The conduction characteristic comparison curve diagram;

[0048] Fig.16 The P-DCT of the embodiment of the present invention has different spacings S between n+ and p+ regions. B Conduction characteristic comparison curve when ;

[0049] Fig.17 is a comparative curve diagram of the conduction characteristics of the P-DCT of the embodiment of the present invention at different base steady-state currents;

[0050] Fig.18 1 is a comparison curve of the turn-on characteristics of the P-DCT of the embodiment of the present invention under different base trigger peak currents and resistive loads;

[0051] Fig.19 1 is a comparison curve of the turn-off characteristics of the P-DCT of the embodiment of the present invention at different base turn-off peak currents and resistive loads;

[0052] Fig. 20 A schematic flow chart of a method for preparing a planar gate dual-control electrode 4H-SiC composite transistor structure provided by an embodiment of the present invention;

[0053] Figure 21a to Figure 21h A schematic cross-sectional diagram of the process flow of a method for preparing a planar gate dual-control electrode 4H-SiC composite transistor structure provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0055] See also Figure 1 The cell structure of the existing 4H-SiC planar gate power MOSFET (hereinafter referred to as VDMOS) is on a 4H-SiC n+ substrate (see Figure 1 4H-SiC n+sub), n buffer layers are arranged in sequence (see Figure 1 n buffer), n-drift region (see Figure 1 n-drift in), n-carrier extension layer (see Figure 1nCSL in the figure), and p-body regions are arranged on both sides of nCSL (see Figure 1 The p-body in the p-body region has an n+ source region (see Figure 1 n+ on both sides of the upper middle), a gate oxide layer and heavily doped polysilicon are respectively arranged on the upper surfaces of the p-body regions on both sides and part of the n+ source region, and a gate G is arranged on the polysilicon; p+ ohmic contact regions in contact with the n+ source region are respectively arranged outside the n+ source region (see Figure 1 The p+ on both sides of the upper middle part is provided with a source S on the upper surface of the part of the n+ source region and the p+ ohmic contact region, and the drain D is provided on the back of the 4H-SiC n+ substrate. Each unit cell is symmetrical about the central plane gate, and the entire device is a multi-unit parallel structure. In addition, there is a PIN body diode composed of a p+ ohmic contact region, a p-body region, an n-carrier expansion layer (CSL), an n-drift region, an n-buffer layer, and an n+ substrate.

[0056] However, in practical applications, the existing 4H-SiC VDMOS still has many disadvantages, such as large on-resistance, poor short-circuit resistance, too fast turn-off dv / dt rise, and the existence of body diode, etc., which leads to the 4H-SiC power MOSFET devices still unable to meet the application requirements in applications with high conduction loss and short-circuit capability requirements.

[0057] In order to solve the above problems, an embodiment of the present invention proposes a planar gate dual-control electrode 4H-SiC composite transistor structure and a preparation method.

[0058] In the first aspect, the embodiment of the present invention provides a planar gate dual control electrode 4H-SiC composite transistor structure, the planar gate dual control electrode 4H-SiC composite transistor is referred to as P-DCT, and its structure includes a plurality of parallel cell structures, see Figure 2 , the cellular structure comprises:

[0059] An n buffer layer, an n-drift region, an n carrier expansion layer, and a p body region are sequentially arranged on a 4H-SiC n+ substrate, wherein the p body region on each side is a table structure, and an n+ source region and a p+ region are respectively arranged in the upper and lower parts of the table structure, and the n+ source region and the p+ region have a spacing; a gate oxide layer and a polysilicon layer are arranged from bottom to top on the upper surfaces of the n carrier expansion layer, the p body regions on both sides of the n carrier expansion layer, and the adjacent n+ source region; a planar gate G is arranged on the surface of the polysilicon layer; a source S is arranged on the surface of the n+ source region; a base B is arranged on the surface of the p+ region; a drain D is arranged on the back of the 4H-SiC n+ substrate; wherein the planar gate G and the base B are both control electrodes; each cell structure is symmetrical with the central planar gate G as an axis, which is equivalent to the parallel connection of a VDMOS and a BJT, wherein the VDMOS is located in the center and the BJT is located on the outside.

[0060] and Figure 1 similar, Figure 2 In the table, 4H-SiC n+sub represents 4H-SiC n+substrate; n buffer represents n buffer layer; n-drift represents n-drift region; n CSL represents n carrier extension layer; p-body represents p body region; n+ represents n+ source region; p+ represents p+ region, i.e. p+ ohmic contact region; G represents planar gate; S represents source; B represents base; D represents drain; E represents emitter of BJT; and C represents collector of BJT.

[0061] In the cell structure of the embodiment of the present invention, the n-drift region of VDMOS is equivalent to the n-collector region of BJT, the p-body region of VDMOS is equivalent to the p-base region of BJT, the n+source region of VDMOS is equivalent to the n+emitter region of BJT, and the 4H-SiC n+substrate of VDMOS is equivalent to the collector ohmic contact region of BJT; at the same time, the source S of VDMOS is the emitter E of BJT, and the drain D of VDMOS is the collector C of BJT. The J1 junction formed by the p-body region and the n-drift region is equivalent to the collector junction of BJT; the J2 junction formed by the p-body region and the n+source region is equivalent to the emitter junction of BJT.

[0062] When the planar gate dual-control electrode 4H-SiC composite transistor structure is turned on, a gate voltage is applied to the planar gate G, a base current is applied to the base B, and VDMOS and BJT are triggered to turn on at the same time, so that the n-drift region produces a conductivity modulation effect, and the entire device operates in a bipolar mode.

[0063] In a preferred embodiment, the width W of the n+ source region is n+ is 5 to 7 μm; the thickness D of the n+ source region n+is 0.3 to 0.5 μm; + The distance S between the source region and the p+ region B 3~5μm.

[0064] The polysilicon in the embodiment of the present invention is heavily doped like the existing VDMOS.

[0065] contrast Figure 1 , Figure 2 It can be seen that compared with the existing VDMOS, the difference of the P-DCT proposed in the present invention is that a table is set on the surface of the p-body region and the n+ source region, the n+ source region is separated from the p+ ohmic contact region, and they are set as the source and the base respectively. The entire P-DCT is equivalent to the parallel connection of VDMOS and BJT.

[0066] When the P-DCT is turned on, the gate voltage and base current are applied to the control electrode respectively, and the VDMOS and BJT are triggered to turn on at the same time. The n-drift region will produce a conductivity modulation effect, so the P-DCT works in a bipolar mode, which can not only improve the on-resistance of the device, but also reduce the channel density of the same chip area due to the increase in the width of the n+ source region and the distance between it and the p+ ohmic contact region, which can effectively improve the short-circuit resistance of the device. In addition, by adjusting the size of the base current, the conduction loss and turn-off loss of the device can be reduced. In addition, the separation of the p+ ohmic contact region and the n+ source region eliminates the body diode in the existing VDMOS, thereby avoiding the influence of the body diode on the characteristics of the MOSFET.

[0067] In summary, the planar gate dual control electrode 4H-SiC composite transistor structure of the embodiment of the present invention introduces BJT on the basis of the existing planar gate 4H-SiC MOSFET (VDMOS) structure, connects the two in parallel, adopts dual control electrodes, and controls the opening and closing of MOS and BJT by adjusting the voltage or current of the control electrodes respectively, which can reduce the on-resistance and conduction loss of the device, increase the short-circuit withstand time, improve the short-circuit resistance, and eliminate the influence of the body diode on the device characteristics, thereby meeting the application requirements of power switching devices.

[0068] In order to facilitate understanding of the effect of the planar gate dual-control electrode 4H-SiC composite transistor structure proposed in the present invention, the P-DCT structure is compared and analyzed with the existing 4H-SiC VDMOS, as follows:

[0069] 1) The working principle of the above-mentioned 4H-SiC P-DCT with dual control electrodes of the present invention is significantly different from that of the existing power MOSFET.

[0070] Reference Figure 3, is the equivalent circuit of the 4H-SiC dual-controller composite transistor of the present invention. It can be seen that the 4H-SiC P-DCT is formed by connecting MOS and BJT in parallel, the drain D is shared with the collector C, the source S is shared with the emitter E, and the gate G and base B are used to control the opening and closing of each.

[0071] Reference Figure 4 , is the driving signal control timing applied by the dual control electrodes of the P-DCT of the present invention; it can be seen that when the device is turned on, the gate G applies a positive voltage signal and the base B applies a positive current peak signal; after conduction, the gate voltage remains unchanged and the base current drops to the steady-state base current; when the device is turned off, the gate G applies a negative voltage signal and the base B applies a negative current signal.

[0072] Reference Figure 5 , is a schematic diagram of the carrier transport trajectory of the existing VDMOS at the initial stage of opening. It can be seen that when the gate-source voltage is greater than the threshold voltage (V GS >V TH ), the drain-source voltage is greater than zero (V DS >0), at the beginning of VDMOS conduction, an N channel will be formed on the surface of the p-body region below the gate G, and the electrons in the n+ source region will enter the n CSL through the N channel and expand horizontally to reach the n-drift region, and finally flow out from the drain to form a drain current. It can be seen that the drain current is only the electron current passing through the channel, and its working mode is a unipolar working mode. During the conduction period, the n-drift region will not have a conductivity modulation effect, so it has a higher on-resistance.

[0073] Reference Figure 6 , is a schematic diagram of the carrier transport trajectory of the P-DCT of the present invention at the initial stage of opening. It can be seen that the carrier transport trajectory of the P-DCT of the present invention is significantly different from that of the existing VDMOS at the initial stage of opening. When the gate-source voltage is greater than the threshold voltage (V GS >V TH ), the base-emitter voltage is greater than the J2 junction turn-on voltage (V BE >V TO )(i.e. base current I B >0), drain-source voltage is greater than zero (V DS >0), two parallel N channels similar to VDMOS are formed under the P-DCT gate G of the present invention. In addition to the N channels being able to conduct electron current, due to the positive bias voltage V applied by the base-emitter BEMake the J2 junction (i.e., the emitter junction) forward biased, so the n+ source region (emitter region) will inject electrons into the p-body region (p-base region), and some of them will recombine with some holes in the p-body region to form a hole current; the holes that have not recombinated will enter the n+ emitter region and flow out from the emitter; the electrons that have not recombinated will be swept into the n-drift region by the electric field of the reverse-biased J1 junction (i.e., the collector junction), drift, and then flow out from the collector to form a drain (collector) current. It can be seen that the current in the P-DCT has two parts, one is the electron current passing through the MOS channel, and the other is the current passing through the BJT, including the electron current and the hole current; therefore, the P-DCT works in bipolar mode, and a conductivity modulation effect will occur during the conduction period, thereby reducing the on-resistance.

[0074] 2) Taking the 2kV withstand voltage level as an example, the relevant characteristics are compared and explained.

[0075] Reference Figure 7 , which is a comparison curve of the breakdown characteristics of the P-DCT of the present invention and the existing VDMOS. Because the breakdown mechanism of the two is the same, the external voltage is borne by the J1 junction formed by the p-body region and the n-drift region. Under the same longitudinal structural parameters and a leakage current of 10nA, the breakdown voltage of VDMOS is 2580V, and the breakdown voltage of P-DCT is 2610V. It can be seen that the breakdown voltage of the P-DCT of the present invention is slightly higher than that of VDMOS, and the breakdown voltages of both meet the 2kV withstand voltage level requirement.

[0076] Reference Figure 8 , which is a comparison curve of the on-state characteristics of the P-DCT of the present invention and the existing VDMOS. It can be seen that under the conditions of a drain current of 60A and a gate voltage of 18V, the on-resistances of the P-DCT and VDMOS are 12mΩ and 16.6mΩ respectively, and the on-resistance of the P-DCT is 27.7% lower than that of the VDMOS, and the saturation current of the P-DCT is also significantly lower than that of the VDMOS, indicating that the P-DCT can reduce the conduction loss and improve the short-circuit tolerance.

[0077] Reference Fig. 9 , is a transfer characteristic comparison curve between the P-DCT of the present invention and the existing VDMOS. It can be seen that in V DS =V GS 、V GS =20V, I D =48mA, the threshold voltage of VDMOS is 3.1V; the threshold voltage of P-DCT is 1.7V. This shows that after adding the base, the threshold voltage of P-DCT is significantly reduced.

[0078] Reference Fig.10 , is the turn-on characteristic comparison curve of the P-DCT of the present invention and the existing VDMOS under resistive load. It can be seen that when the bus voltage V DD=1000V, gate resistance R G =2Ω, gate-source voltage V GS = +18V, load resistance R L =16.6Ω, when the existing VDMOS is turned on, the rise time t r (i.e., voltage drop time) is 22.8ns; the P-DCT of the present invention has a voltage drop time of 22.8ns. DD =1000V, R G =2Ω、R L =16.6Ω,V GS = +18V, base trigger peak current I BP =7A and base steady-state current I B =When turned on under 2A condition, the rise time t r is 26.9ns, which is shorter than VDMOS’s t r Slightly longer.

[0079] Reference Fig.11 , is the turn-off characteristic comparison curve of the P-DCT of the present invention and the existing VDMOS under resistive load. It can be seen that at V DD =1000V, I DS =60A, R G =2Ω、R L =16.6Ω、V GS = -2V, when the 60A current is turned off, the fall time t of the existing VDMOS when it is turned off f (i.e., voltage rise time) is 9.9ns; the P-DCT of the present invention has a voltage rise time of 9.9ns. DD =1000V, R G =2Ω、R L =16.6Ω,V GS =-2V, I BO = -8A, turn off I DS = Fall time t at 60A current f is 17.4ns, which is shorter than VDMOS’s t f Longer.

[0080] Reference Fig.12 , is the turn-off characteristic comparison curve of the P-DCT of the present invention and the existing VDMOS under inductive load. It can be seen that under the same load inductance L G=10μH, the overshoot voltage of the existing VDMOS when turned off is 268V, and the dv / dt is 126.6V / μs; the overshoot voltage of the P-DCT of the present invention when turned off is 210V, and the dv / dt is 49.2V / μs, which are about 21.6% and 61.1% lower than the overshoot voltage and dv / dt of VDMOS, respectively. This shows that the working stability of P-DCT is better than that of VDMOS, and it will not cause large electromagnetic interference and generate EMI noise due to high dv / dt.

[0081] Reference Fig.13 , is a short-circuit characteristic comparison curve of the P-DCT of the present invention and the existing VDMOS when the bus voltage is 1000V and the stray inductance is 15nH. It can be seen that since the P-DCT has a lower saturation current and the base negative current is extracted, its short-circuit withstand time is 4.2μs, while the short-circuit withstand time of the VDMOS is 3.6μs, and the short-circuit withstand time of the P-DCT is improved by 16.7% compared with the VDMOS.

[0082] 3) Explanation of the influence trend of the key structural parameters of the P-DCT of the present invention on the characteristics.

[0083] Reference Fig.14 , is the conduction characteristic curve of the P-DCT of the present invention under different n+ source region widths. It can be seen that with the n+ source region width W n+ Increase, the on-resistance R on and saturation current will decrease. n+ When 5μm is used, a lower R on and saturation current I Dsat .

[0084] Reference Fig.15 , is the conduction characteristic curve of the P-DCT of the present invention under different n+ source region thicknesses. It can be seen that with the n+ source region thickness D n+ Increase, the on-resistance R on The saturation current will increase. n+ When 0.3μm is used, a lower R on and saturation current I Dsat .

[0085] Reference Fig.16 , is a graph of the conduction characteristic of the P-DCT of the present invention at different distances between the n+ source region and the p+ ohmic contact region. It can be seen that with the distance S between the n+ source region and the p+ ohmic contact region, B Increase, the on-resistance R on remains basically unchanged, but the saturation current decreases significantly. B When 3μm is used, a lower R on and saturation current I Dsat .

[0086] 4) Explanation of the influence trend of the P-DCT base current on the switching characteristics of the present invention.

[0087] Reference Fig.17 , is the conduction characteristic curve of the P-DCT of the present invention under different base steady-state currents. It can be seen that with the base steady-state current I B Increase, the on-resistance R on The saturation current will increase significantly. B When 3A is used, a lower R on and saturation current I Dsat .

[0088] Reference Fig.18 , is the turn-on characteristic curve of the resistive load of the P-DCT of the present invention under different base trigger peak currents. It can be seen that with the base trigger peak current I BP Increase, opening time t on When I BP When the current is above 7A, a shorter turn-on time and lower turn-on energy consumption can be obtained at the same time.

[0089] Reference Fig.19 , is the turn-off characteristic curve of the resistive load of the P-DCT of the present invention under different base turn-off peak currents. It can be seen that with the base turn-off current I BO Increase, turn-off time t off Reduce, turn off energy consumption E off When I BO When the current is above -8A, a shorter shutdown time and lower shutdown energy consumption can be obtained at the same time.

[0090] In a second aspect, an embodiment of the present invention provides a method for preparing a planar gate dual-control electrode 4H-SiC composite transistor structure, see Fig. 20 and Figure 21a to Figure 21h , the method may include the following steps:

[0091] S1, using epitaxial process on 4H-SiC n+ substrate, growing n buffer layer, n-drift region, and n carrier expansion layer in sequence;

[0092] Among them, the first choice is the crystal direction <0001> The n+ type 4H-SiC substrate is prepared, and the surface is etched and cleaned in situ to obtain the desired 4H-SiC n+ substrate. Then, the n buffer layer, n-drift region, and n carrier expansion layer are grown on the 4H-SiC n+ substrate in sequence using an epitaxial process. The thickness of each layer can be set as required. The obtained crystal structure is shown in Fig.21a shown.

[0093] S2, aluminum ion implantation is performed in the local area of ​​the top layer on both sides of the n carrier extension layer to form a p body region;

[0094] Specifically, S2 may include the following steps:

[0095] A 30-50nm silicon dioxide film is deposited on the upper surface of the current crystal, and then, under the mask of photoresist, aluminum ions are implanted multiple times at room temperature on the local surface areas on both sides of the n-carrier expansion layer to form a p-body region. The resulting crystal structure is shown in Figure 21b As shown (for simplicity, the silicon dioxide film on the upper surface of the crystal is not shown).

[0096] In this step, the p-body region doping concentration formed after aluminum ion implantation annealing is 1×10 17 cm -3 ~2×10 17 cm -3 .

[0097] S3, nitrogen ion implantation is performed in the local area of ​​the p-body region on both sides close to the surface of the n-carrier extension layer to form an n+ source region;

[0098] Specifically, S3 may include the following steps:

[0099] S31, removing the silicon dioxide film on the upper surface of the current crystal, depositing a polysilicon masking film, and photolithographically forming a polysilicon mesa;

[0100] S32, depositing a silicon dioxide film of 800nm ​​to 1000nm on the upper surface of the current crystal, and then performing dry etching to form an oxide sidewall;

[0101] S33, depositing a 30-50nm silicon dioxide covering film on the upper surface of the current crystal, and under the mask of the oxide sidewalls, multiple nitrogen ion implantations are performed on the local area of ​​the top layer in the p-body region on each side at 500°C to form an n+ source region.

[0102] In this step, the doping concentration of the n+ source region formed after nitrogen ion implantation annealing is 3×10 19 cm -3 ~5×10 19 cm -3 .

[0103] The obtained crystal structure can be found in Fig.21c As shown (for simplicity, the silicon dioxide film on the upper surface of the crystal is not shown), Fig.21c It can be seen that the n+ source region is not in contact with the n carrier extension layer.

[0104] S4, etching the p-body region outside the n+ source region by an etching process to form a mesa structure of the n+ source region and the p-body region; performing ion implantation on the outer surface edge region of the p-body region having a distance from the n+ source region to form a p+ region;

[0105] Specifically, S4 may include the following steps:

[0106] S41, remove the silicon dioxide film on the current crystal surface, re-deposit a silicon dioxide masking film, and dry-etch the p-body region outside the n+ source region on the crystal surface to form a mesa structure of the n+ source region and the p-body region; wherein the over-etching of the n+ source region is controlled within 10% of its depth; the obtained crystal structure is shown in Fig.21d As shown (for simplicity, the silicon dioxide film on the upper surface of the crystal is not shown).

[0107] S42, removing the silicon dioxide masking film on the upper surface of the current crystal, performing NO / N2O nitridation treatment on the upper surface to remove damage caused by surface etching to reduce interface states;

[0108] S43, depositing a 30-50 nm silicon dioxide cover film on the upper surface of the current crystal, and depositing a polysilicon mask film, by etching the polysilicon film, forming an injection window of the p+ region at the outer surface edge region of the p body region with a spacing from the n+ source region, and then performing aluminum ion implantation at 500° C. to form a p+ region;

[0109] S44, removing the silicon dioxide covering film and the polysilicon masking film on the upper surface of the current crystal, and depositing a carbon film, and performing high-temperature annealing under the protection of the carbon film to activate impurities, eliminate damage caused by ion implantation, and prevent impurities from overflowing;

[0110] The temperature of high temperature annealing is 1700°C. In this step, the doping concentration of the p+ region formed after aluminum ion implantation annealing is 3×10 19 cm -3 ~5×10 19 cm -3 , which belongs to high concentration injection.

[0111] The crystal structure obtained in this step is shown in Fig.21e As shown (for simplicity, the silicon dioxide covering film and polysilicon masking film on the upper surface of the crystal are not shown).

[0112] S5, preparing a gate oxide layer by thermal oxidation on the upper surfaces of the n carrier extension layer, the p body regions on both sides and the adjacent part of the n+ source region, and depositing polysilicon on the surface of the gate oxide layer and performing heavy doping;

[0113] Specifically, S5 may include:

[0114] Remove the carbon film on the surface of the current crystal, perform high-temperature thermal oxidation to form a gate oxide layer, then deposit polysilicon and perform heavy doping;

[0115] The temperature used for high temperature thermal oxidation is 1250°C; the doping concentration used for heavy doping is 5×10 19 cm -3 above.

[0116] The crystal structure obtained in this step is shown in Fig.21f shown.

[0117] S6, preparing a planar gate G on the obtained polysilicon layer, preparing a source S on the n+ source region, preparing a base B on the surface of the p+ region, and preparing a drain D on the back side of the 4H-SiC n+ substrate;

[0118] Specifically, S6 may include the following steps:

[0119] S61, depositing a silicon dioxide film and a borophosphosilicate glass layer on the upper surface of the current crystal, and then etching to form ohmic contact holes for the source and base;

[0120] S62, depositing metal nickel on the upper surface of the current crystal, annealing at 750°C to form metal ohmic contacts of the source and base, and then removing the metal nickel layer on the surface of the borophosphosilicate glass by a stripping process;

[0121] S63, on the upper surface of the current crystal, under the mask of photoresist, a gate pressure welding hole is etched, and metal titanium, titanium nitride and aluminum copper films are deposited in sequence, and then the source, base and gate metal electrodes are formed by reverse etching, and rapid annealing is performed; the crystal structure obtained in this step is shown in Figure 21g shown.

[0122] S64, depositing a silicon nitride film on the upper surface of the current crystal and performing photolithography to passivate the terminal area on the chip surface;

[0123] S65, coating a polyimide film on the upper surface of the current crystal, photolithography to form surface source, gate and base region bonding area patterns, and performing imidization treatment to form a front terminal passivation and protection layer;

[0124] S66, thinning the lower surface of the current crystal, and sputtering metal titanium, nickel, and silver in sequence, and then performing laser annealing to reduce the ohmic contact resistance;

[0125] Step S66 is to prepare the drain electrode D.

[0126] The crystal structure obtained in this step is shown in Figure 21h shown.

[0127] Through the above steps, the planar gate dual control electrode 4H-SiC composite transistor is completed.

[0128] The chips then need to be diced, packaged and tested.

[0129] The design features of the above process flow of the present invention are:

[0130] In all ion implantations (involving step S2, step S33 and step S43), a 30-50 nm silicon dioxide capping film is used for implantation, which can not only avoid crystal damage caused by ion implantation, but also move the implantation peak concentration to the crystal surface;

[0131] After all ions are implanted, only one high temperature annealing treatment is performed under the protection of the carbon film (involving step S5), which can not only activate the impurities, eliminate the damage caused by ion implantation, and prevent the impurities from overflowing, but also reduce the process flow and reduce the cost;

[0132] The channel length between the p-body region and the n+ source region is precisely controlled by a self-alignment process through the oxide sidewall (involving steps S2, S31, and S32), which can improve the preparation accuracy;

[0133] The over-etching of the n+ source region needs to be controlled within 10% of its depth to prevent the p-body region from being too thin and causing punch-through (involving step S41).

[0134] In summary, the preparation method of the planar gate dual-control electrode 4H-SiC composite transistor structure proposed in the present invention has a simple manufacturing process and is compatible with the existing VDMOS process. It can reduce the device conduction loss, improve the short-circuit resistance, and eliminate the influence of the body diode.

[0135] It should be noted that, in the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0136] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0137] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the concept and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A planar gate dual-control electrode 4H-SiC composite transistor structure, characterized in that: The invention comprises a plurality of parallel cellular structures, wherein the cellular structure comprises: An n buffer layer, an n-drift region, an n carrier expansion layer, and a p body region are sequentially arranged on a 4H-SiC n+ substrate, wherein the p body region on each side is a table structure, and an n+ source region and a p+ region are respectively arranged in the upper and lower parts of the table structure, and the n+ source region and the p+ region have a spacing; a gate oxide layer and a polysilicon layer are arranged from bottom to top on the upper surfaces of the n carrier expansion layer, the p body regions on both sides of the n carrier expansion layer, and the adjacent n+ source region; a planar gate G is arranged on the surface of the polysilicon layer; a source S is arranged on the surface of the n+ source region; a base B is arranged on the surface of the p+ region; a drain D is arranged on the back of the 4H-SiC n+ substrate; wherein the planar gate G and the base B are both control electrodes; each cell structure is symmetrical with the central planar gate G as an axis, which is equivalent to the parallel connection of a VDMOS and a BJT, wherein the VDMOS is located in the center and the BJT is located on the outside.

2. The planar gate dual-control electrode 4H-SiC composite transistor structure according to claim 1, characterized in that: In the cell structure, the n-drift region of VDMOS is equivalent to the n-collector region of BJT, the p-body region of VDMOS is equivalent to the p-base region of BJT, the n+ source region of VDMOS is equivalent to the n+ emitter region of BJT, and the 4H-SiC n+ substrate of VDMOS is equivalent to the collector ohmic contact region of BJT; at the same time, the source S of VDMOS is the emitter E of BJT, and the drain D of VDMOS is the collector C of BJT.

3. The planar gate dual-control electrode 4H-SiC composite transistor structure according to claim 2, characterized in that: When the planar gate dual-control electrode 4H-SiC composite transistor structure is turned on, a gate voltage is applied to the planar gate G, a base current is applied to the base B, and VDMOS and BJT are triggered to turn on at the same time, so that the n-drift region produces a conductivity modulation effect, and the entire device operates in a bipolar mode.

4. The planar gate dual-control electrode 4H-SiC composite transistor structure according to claim 1, characterized in that: The width W of the n+ source region n+ is 5 to 7 μm; the thickness D of the n+ source region n+ is 0.3 to 0.5 μm; + The distance S between the source region and the p+ region B 3~5μm.

5. A method for preparing a planar gate dual-control electrode 4H-SiC composite transistor structure, characterized in that: include: Using epitaxial process on 4H-SiC n+ substrate, n buffer layer, n-drift region and n carrier expansion layer are grown in sequence; Aluminum ions are implanted into local areas of the top layer on both sides of the n-carrier extension layer to form a p-body region; Nitrogen ion implantation is performed in the local area of ​​the p-body region on both sides close to the surface of the n-carrier extension layer to form an n+ source region; Etching the p-body region outside the n+ source region by using an etching process to form a mesa structure of the n+ source region and the p-body region; Ion implantation is performed on the outer surface edge region of the p-body region which is spaced apart from the n+ source region to form a p+ region; On the upper surfaces of the n carrier extension layer, the p body regions on both sides and the adjacent part of the n+ source region, a gate oxide layer is prepared by thermal oxidation, and polysilicon is deposited on the surface of the gate oxide layer and heavily doped; A planar gate G is prepared on the obtained polysilicon layer, a source S is prepared in the n+ source region, a base B is prepared on the surface of the p+ region, and a drain D is prepared on the back side of the 4H-SiC n+ substrate.

6. The method for preparing a planar gate dual-control electrode 4H-SiC composite transistor structure according to claim 5, characterized in that: The step of implanting aluminum ions into local regions of the top layer on both sides of the n-carrier extension layer to form a p-body region comprises: A 30-50nm silicon dioxide covering film is deposited on the upper surface of the current crystal, and then under the mask of photoresist, aluminum ions are injected multiple times at room temperature into the local surface areas on both sides of the n-carrier expansion layer to form a p-body region.

7. The method for preparing a planar gate dual-control electrode 4H-SiC composite transistor structure according to claim 6, characterized in that: The step of implanting nitrogen ions in a local area near the surface of the n carrier extension layer in the p-body region on both sides to form an n+ source region comprises: The silicon dioxide film on the upper surface of the current crystal is removed, a polysilicon masking film is deposited, and a polysilicon mesa is formed by photolithography; Deposit 800nm ​​to 1000nm of silicon dioxide film on the surface of the current crystal, and then perform dry etching to form oxide sidewalls; A 30-50nm silicon dioxide covering film is deposited on the upper surface of the current crystal. Under the mask of the oxide sidewalls, multiple nitrogen ion implantations are performed on the local area of ​​the top layer in the p-body region on each side at 500°C to form an n+ source region.

8. The method for preparing a planar gate dual-control electrode 4H-SiC composite transistor structure according to claim 7, characterized in that: The p-body region outside the n+ source region is etched by an etching process to form a mesa structure of the n+ source region and the p-body region; Ion implantation is performed on the outer surface edge region of the p-body region having a spacing from the n+ source region to form a p+ region, including: The silicon dioxide film on the current crystal surface is removed, a silicon dioxide masking film is re-deposited, and the p-body region outside the n+ source region on the crystal surface is dry-etched to form a mesa structure of the n+ source region and the p-body region; wherein the over-etching of the n+ source region is controlled within 10% of its depth; The silicon dioxide masking film on the upper surface of the current crystal is removed, and the upper surface is subjected to NO / N2O nitridation treatment to remove the damage caused by surface etching to reduce the interface state; A 30-50 nm silicon dioxide covering film is deposited on the upper surface of the current crystal, and a polysilicon masking film is deposited. By etching the polysilicon film, an injection window for the p+ region is formed at the outer surface edge area of ​​the p-body region with a spacing from the n+ source region. Then, aluminum ion implantation is performed at 500°C to form a p+ region. The doping concentration of the p+ region is 3×10 19 ~5×10 19 cm -3 . The silicon dioxide covering film and polysilicon masking film on the current crystal surface are removed, and a carbon film is deposited. High-temperature annealing is performed under the protection of the carbon film to activate impurities, eliminate damage caused by ion implantation, and prevent impurities from overflowing; wherein, the temperature of the high-temperature annealing is 1700°C.

9. The method for preparing a planar gate dual-control electrode 4H-SiC composite transistor structure according to claim 8, characterized in that: On the upper surfaces of the n carrier extension layer, the p body regions on both sides and the adjacent n+ source region, a gate oxide layer is prepared by thermal oxidation, polysilicon is deposited on the surface of the gate oxide layer and heavily doped, including: The carbon film on the surface of the current crystal is removed, and high-temperature thermal oxidation is performed to form a gate oxide layer, and then polysilicon is deposited and heavily doped; the temperature used for high-temperature thermal oxidation is 1250°C; the doping concentration of polysilicon is 5×10 19 cm -3 above.

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