Silicon carbide MOS device preparation method for improving groove morphology

Abstract

The invention discloses a silicon carbide MOS device preparation method for improving the morphology of a groove, and relates to the technical field of semiconductors. According to the trench morphology of a trench gate SiC MOSFET device, a Poly hard mask layer is adopted as a barrier layer, and then a CSL layer, a P-body layer and an NP layer on the two sides of the trench are prepared in an epitaxial deposition mode. Compared with an original groove etching method, the groove preparation method has the advantages that the shape of the groove is better, the roughness of the inner wall of the groove is smaller, and therefore the groove preparation method is more beneficial to both the performance and the reliability of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a silicon carbide MOS device with improved groove morphology. Background Art

[0002] SiC MOSFET devices made of the third-generation wide bandgap semiconductor material silicon carbide (SiC) have both the switching characteristics of MOSFET unipolar devices and the excellent physical characteristics of SiC, so they have good performance in both static conduction performance and dynamic switching performance. Especially compared with SiIGBT devices, SiC MOSFET can bring higher efficiency benefits in the same application scenario, and the system size and volume can be greatly reduced, which is undoubtedly more in line with the more stringent use requirements of power devices in today's social development.

[0003] Since trench SiC MOSFET can achieve a smaller chip area, the power density and cost of the device are more advantageous, which also makes trench SiC MOSFET known as the future device structure development direction. At present, the grooves of trench SiC MOSFET are formed by etching SiC materials using etching equipment. This preparation process undoubtedly puts high requirements on the etching morphology. If the etching morphology is not good, it will have a significant impact on the performance and reliability of the device. Therefore, the development of a trench preparation method that improves the groove morphology is a technical problem that needs to be solved urgently in this field. Summary of the invention

[0004] In view of the above problems, the present invention provides a silicon carbide MOS device with improved groove morphology and a preparation method thereof, which can improve the groove preparation morphology, reduce the roughness of the inner wall of the groove, and improve the performance and reliability of the device.

[0005] The technical solution of the present invention is: S100, forming an N- Drift layer on the top surface of the N+ Sub layer by epitaxial deposition; S200, forming a P-shield region arranged at intervals on the top surface of the N-Drift layer by Al ion implantation; S300, preparing a Poly hard mask layer on the top surface of the P-shield region as a barrier layer for subsequent trench formation; S400, forming a CSL layer, a P-body layer and a NP layer in sequence on the top surface of the N-Drift layer by epitaxial deposition; S500, removing the Poly hard mask layer to form a groove; S600, forming a gate oxide layer on the inner wall of the trench by dry oxygen oxidation, and forming a Poly layer on the surface of the gate oxide layer by polysilicon deposition; S700, forming an isolation dielectric layer on top surfaces of the NP layer, the gate oxide layer and the Poly layer by oxide deposition; S800, forming an ohmic contact alloy layer on the top surface of the NP layer by sputtering or depositing Ni metal followed by thermal annealing; S900, forming a front electrode metal layer on the top of the device by sputtering Ti and AlCu metals.

[0006] Specifically, in step S100, the doping concentration of the N+ Sub layer is 1E19-5E19cm -2 , N-Drift layer doping concentration is 5E15-3E16cm -2 ; Specifically, in step S200, the doping concentration of the P-shield region is 5E18-1E19cm -2 ; Specifically, in step S300, the depth of the Poly hard mask layer is 0.7um-2.4um; Specifically, in step S400, the depth of the CSL layer is 0.3um-0.6um, and the doping concentration is 1E17-1E19cm -2 ; Specifically, in step S400, the depth of the P-body layer is 0.2um-0.6um, and the doping concentration is 1E17-3E18cm -2 ; Specifically, in step S400, the NP layer depth is 0.2um-0.8um, and the doping concentration is 1E18-3E19cm -2 ; Specifically, in step S600, the thickness of the gate oxide layer is 40nm-80nm; Specifically, in step S800, the Ni metal thickness is 0.3um-1um; Specifically, in step S900, the thickness of the Ti metal is 0.1um-0.6um, and the thickness of the AlCu metal is 2um-5um; For the trench morphology of the trench gate SiC MOSFET device, the present invention uses a Poly hard mask layer as a barrier layer, and then uses epitaxial deposition to prepare the CSL layer, P-body layer and NP layer on both sides of the trench. Compared with the original trench etching method, this trench preparation method has a better trench morphology and a smaller roughness of the inner wall of the trench, so it is more beneficial to the performance and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1is a structural schematic diagram of step S100 of the present invention; Figure 2 is a structural schematic diagram of step S200 of the present invention; Figure 3 is a schematic structural diagram of step S300 of the present invention; Figure 4 is a structural schematic diagram of step S400 of the present invention; Figure 5 is a schematic structural diagram of step S500 of the present invention; Figure 6 is a schematic structural diagram of step S600 of the present invention; Figure 7 is a schematic structural diagram of step S700 of the present invention; Figure 8 is a structural schematic diagram of step S800 of the present invention; Fig. 9 is a structural schematic diagram of step S900 of the present invention; Fig.10 is a structural schematic diagram of step S1000 of the present invention; Fig.11 is a schematic diagram of the structure of step S1100 of the present invention; Fig.12 is a schematic diagram of the structure of step S1200 of the present invention; In the figure, 1 is the N+ Sub layer, 2 is the N-Drift layer, 3 is the P-shield region, 4 is the Poly hard mask layer, 5 is the CSL layer, 6 is the P-body layer, 7 is the NP layer, 8 is the gate oxide layer, 9 is the Poly layer, 10 is the isolation dielectric layer, 11 is the ohmic contact alloy layer, and 12 is the front electrode metal layer. DETAILED DESCRIPTION

[0008] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0009] A silicon carbide MOS device with improved groove morphology comprises the following steps: S100, forming an N-Drift layer 2 on the top surface of the N+ Sub layer 1 by epitaxial deposition; Figure 1 As shown; In step S100, the doping concentration of N+ Sub layer 1 is 1E19-5E19cm -2 , N-Drift layer 2 doping concentration is 5E15-3E16cm -2 .

[0010] S200, forming a P-shield region 3 arranged at intervals on the top surface of the N-Drift layer 2 by Al ion implantation; Figure 2 As shown; The doping concentration of the P-shield region 3 in step S200 is 5E18-1E19cm -2 , depth is 0.2um-0.8um.

[0011] S300, preparing a Poly hard mask layer 4 on the top surface of the P-shield region 3 as a barrier layer for subsequent trench formation; Figure 3 As shown; The depth of the Poly hard mask layer 4 in step S300 is 0.7um-2.4um.

[0012] S400, forming a CSL layer 5 on the top surface of the N-Drift layer 2 by epitaxial deposition; Figure 4 As shown; The depth (or thickness) of the CSL layer 5 in step S400 is 0.3um-0.6um, and the doping concentration is 1E17-1E19cm -2 .

[0013] S500, forming a P-body layer 6 on the top surface of the CSL layer 5 by epitaxial deposition; Figure 5 As shown; The depth of the P-body layer 6 in step S500 is 0.2um-0.6um, and the doping concentration is 1E17-3E18cm -2 .

[0014] S600, forming an NP layer 7 on the top surface of the P-body layer 6 by epitaxial deposition; Figure 6 As shown; In step S600, the depth of the NP layer 7 is 0.2um-0.8um, and the doping concentration is 1E18-3E19cm -2 .

[0015] S700, removing the Poly hard mask layer 4 to form a groove; Figure 7 As shown; the height of the Poly hard mask layer 4 ( Figure 6 in the vertical direction from top to bottom) is greater than the sum of the heights of the CSL layer 5, the P-body layer 6, and the NP layer 7; Wet etching is used for removal. Since the normal groove is formed by etching the SCDO layer by etching method, but the roughness of etching is difficult to control, this method uses the Poly hard mask layer 4 as a block in advance to retain the groove area, and then wet etching is used to remove the Poly hard mask layer 4 to form the groove area, so the roughness is improved compared with etching.

[0016] S800, forming a gate oxide layer 8 on the inner wall of the trench by dry oxygen oxidation; Figure 8 As shown; The thickness of the gate oxide layer 8 in step S800 is 40 nm-80 nm.

[0017] S900, forming a Poly layer 9 on the surface of the gate oxide layer 8 by polysilicon deposition; Fig. 9 As shown; S1000, forming an isolation dielectric layer 10 on the top surfaces of the NP layer 7, the gate oxide layer 8 and the Poly layer 9 by oxide deposition; Figure 1 0 shown; S1100, forming an ohmic contact alloy layer 11 on the top surface of the NP layer 7 by Ni metal sputtering or deposition followed by thermal annealing; Fig.11 As shown; The Ni metal thickness in step S1100 is 0.3um-1um.

[0018] S1200, forming a front electrode metal layer 12 on the top of the device by sputtering Ti and AlCu metals, such as Fig.12 shown.

[0019] The thickness of the Ti metal in step S1200 is 0.1um-0.6um, and the thickness of the AlCu metal is 2um-5um.

[0020] A silicon carbide MOS device with improved trench morphology, comprising: an N+ Sub layer 1, an N-Drift layer 2, a CSL layer 5, a P-body layer 6, an NP layer 7, an ohmic contact alloy layer 11 and a front electrode metal layer 12 arranged in sequence from bottom to top; The top surface of the N-Drift layer 2 is provided with a plurality of P-shield areas 3 extending downward; A Poly layer 9 extending to the CSL layer 5 is disposed on the top surface of the NP layer 7, and a gate oxide layer 8 is disposed on the side and bottom surfaces of the Poly layer 9; the bottom surface of the gate oxide layer 8 is connected to the P-shield region 3; The isolation dielectric layer 10 is respectively located on the top surfaces of the NP layer 7 , the gate oxide layer 8 and the Poly layer 9 , and is connected to the ohmic contact alloy layer 11 on the side surface.

[0021] The present invention is aimed at the groove morphology of the trench gate SiC MOSFET device, uses a Poly hard mask layer 4 as a barrier layer, and then uses epitaxial deposition to prepare the CSL layer 5, P-body layer 6 and NP layer 7 on both sides of the groove. Compared with the original trench etching method, this trench preparation method has a better groove morphology and a smaller roughness of the inner wall of the trench, so it is more beneficial to the performance and reliability of the device.

Claims

1. A method for preparing a silicon carbide MOS device with improved groove morphology, characterized in that: The steps include: S100, forming an N-Drift layer (2) on the top surface of the N+ Sub layer (1) by epitaxial deposition; S200, forming a P-shield region (3) arranged at intervals on the top surface of the N-Drift layer (2) by Al ion implantation; S300, preparing a Poly hard mask layer (4) on the top surface of the P-shield region (3) as a barrier layer for subsequent trench formation; S400, forming a CSL layer (5), a P-body layer (6) and a NP layer (7) in sequence on the top surface of the N-Drift layer (2) by epitaxial deposition; S500, removing the Poly hard mask layer (4) to form a groove; S600, forming a gate oxide layer (8) on the inner wall of the trench by dry oxygen oxidation, and forming a Poly layer (9) on the surface of the gate oxide layer (8) by polysilicon deposition; S700, forming an isolation dielectric layer (10) on the top surfaces of the NP layer (7), the gate oxide layer (8) and the Poly layer (9) by means of oxide deposition; S800, forming an ohmic contact alloy layer (11) on the top surface of the NP layer (7) by Ni metal sputtering or deposition followed by thermal annealing; S900, forming a front electrode metal layer (12) on the top of the device by sputtering Ti and AlCu metals.

2. The method for preparing a silicon carbide MOS device with improved groove morphology according to claim 1, characterized in that: In step S100, the doping concentration of the N+ Sub layer (1) is 1E19-5E19cm -2 , the doping concentration of N-Drift layer (2) is 5E15-3E16cm -2 .

3. The method for preparing a silicon carbide MOS device with improved groove morphology according to claim 1, characterized in that: In step S200, the doping concentration of the P-shield region (3) is 5E18-1E19cm -2 .

4. The method for preparing a silicon carbide MOS device with improved groove morphology according to claim 1, characterized in that: In step S300, the depth of the Poly hard mask layer (4) is 0.7um-2.4um.

5. The method for preparing a silicon carbide MOS device with improved groove morphology according to claim 1, characterized in that: In step S400, the depth of the CSL layer (5) is 0.3um-0.6um, and the doping concentration is 1E17-1E19cm -2 .

6. The method for preparing a silicon carbide MOS device with improved groove morphology according to claim 1, characterized in that: In step S400, the depth of the P-body layer (6) is 0.2um-0.6um, and the doping concentration is 1E17-3E18cm -2 .

7. The method for preparing a silicon carbide MOS device with improved groove morphology according to claim 1, characterized in that: In step S400, the depth of the NP layer (7) is 0.2um-0.8um, and the doping concentration is 1E18-3E19cm -2 .

8. The method for preparing a silicon carbide MOS device with improved groove morphology according to claim 1, characterized in that: The thickness of the gate oxide layer (8) in step S600 is 40nm-80nm.

9. The method for preparing a silicon carbide MOS device with improved groove morphology according to claim 1, characterized in that: The thickness of the Ni metal in step S800 is 0.3um-1um.

10. The method for preparing a silicon carbide MOS device with improved groove morphology according to claim 1, characterized in that: In step S900 , the thickness of the Ti metal is 0.1um-0.6um, and the thickness of the AlCu metal is 2um-5um.

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