Integrated circuit including power gate switch

Abstract

An integrated circuit includes: a backside wiring layer on a backside of a substrate, the backside wiring layer including a first backside pattern and a second backside pattern isolated from each other; and a power gate switch on a front side of the substrate, the power gate switch connected to the first backside pattern and the second backside pattern. The power supply gate switch includes: a first source / drain region connected to the first backside pattern and configured to receive a first supply voltage from the first backside pattern; a gate line structure configured to receive a power gate signal; and a second source / drain region connected to the second backside pattern, and configured to receive a power supply signal from the first source / drain region based on the power supply gate signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority of Korean Patent Application No. 10-2023-0118551 filed on September 6, 2023, and Korean Patent Application No. 10-2023-0197638 filed on December 29, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] Devices and methods consistent with embodiments of the present invention relate to integrated circuits, and more particularly, to integrated circuits including power gate switches and methods of designing the same. Background Art

[0004] Due to the need for high integration and advancements in semiconductor processes, the width, spacing, and / or height of wires included in an integrated circuit may decrease, and the effects of parasitic components of the wires may increase. In addition, the supply voltage of the integrated circuit may be reduced to reduce power consumption, increase operating speed, etc., and therefore, the effects of parasitic components of the wires on the integrated circuit may become more significant. Therefore, the need for methods of designing integrated circuits with efficient routing and vias increases. Summary of the invention

[0005] The present disclosure provides an integrated circuit capable of increasing wiring resources and improving area efficiency by using a backside wiring layer to supply power to a power gate switch, and a method of designing the integrated circuit.

[0006] According to one aspect of the present disclosure, an integrated circuit is provided, which may include: a backside wiring layer on the backside of a substrate, the backside wiring layer including a first backside pattern and a second backside pattern isolated from each other; and a power gate switch on the front side of the substrate, the power gate switch connected to the first backside pattern and the second backside pattern. The power gate switch may include: a first source / drain region, the first source / drain region is connected to the first backside pattern and is configured to receive a first power supply voltage from the first backside pattern; a gate line structure, the gate line structure is configured to receive a power gate signal; and a second source / drain region, the second source / drain region is connected to the second backside pattern, and is configured to receive a power signal from the first source / drain region based on the power gate signal.

[0007] According to another aspect of the present disclosure, an integrated circuit is provided, the integrated circuit may include: a backside wiring layer on the backside of a substrate, the backside wiring layer including a first backside pattern and a second backside pattern, the first backside pattern and the second backside pattern each extending in a first direction and being isolated from each other in a second direction intersecting the first direction; a contact on the front side of the substrate, the contact extending in the second direction; and a power gate switch on the front side of the substrate, the power gate switch connected to the first backside pattern and the second backside pattern. The power gate switch may include: a first source / drain region, the first source / drain region being configured to receive a first power supply voltage from the first backside pattern through the contact; a gate line structure, the gate line structure being configured to receive a power gate signal; and a second source / drain region, the second source / drain region being connected to the second backside pattern and configured to receive a power signal from the first source / drain region based on the power gate signal.

[0008] According to another aspect of the present disclosure, an integrated circuit is provided, which may include: a backside wiring layer on the backside of a substrate, the backside wiring layer including a first backside pattern and a second backside pattern isolated from each other; a power gate switch on the front side of the substrate; a first backside via layer, the first backside via layer connected to the power gate switch and including a first backside via and a second backside via; and a second backside via layer between the backside wiring layer and the first backside via layer, the second backside via layer including a third backside via on the first backside pattern and a fourth backside via on the second backside pattern. The first backside via may be on the third backside via, and the second backside via may be on the fourth backside via. The power gate switch may include: a first source / drain region, the first source / drain region being configured to receive a first power supply voltage from the first back side pattern through the third back side via and the first back side via; a gate line structure, the gate line structure being configured to receive a power gate signal; and a second source / drain region, the second source / drain region being connected to the second back side pattern through the fourth back side via and the second back side via, and being configured to receive a power signal from the first source / drain region based on the power gate signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 shows a layout of an integrated circuit according to one or more embodiments;

[0011] Figure 2 is a circuit diagram of a power gate switch according to one or more embodiments;

[0012] Figure 3A According to one or more embodiments, Figure 1 A cross-sectional view taken along line X1-X1', and Figure 3B According to one or more embodiments, Figure 1 A cross-sectional view taken along line X2-X2';

[0013] Figure 4 shows a layout of an integrated circuit according to one or more embodiments;

[0014] Figure 5 is a circuit diagram of a power gate switch according to one or more embodiments;

[0015] Fig. 6A According to one or more embodiments, Figure 4 A cross-sectional view taken along line X3-X3', and Figure 6B According to one or more embodiments, Figure 4 A cross-sectional view taken along line X4-X4';

[0016] Figure 7 shows a layout of an integrated circuit according to one or more embodiments;

[0017] Fig. 8A According to one or more embodiments, Figure 7 A cross-sectional view taken along line X5-X5', and Figure 8B According to one or more embodiments, Figure 7 A cross-sectional view taken along line X6-X6'.

[0018] Fig. 9 shows a layout of an integrated circuit according to one or more embodiments;

[0019] Fig. 10A According to one or more embodiments, Fig. 9 A cross-sectional view taken along line X7-X7', and Fig. 10B According to one or more embodiments, Fig. 9 A cross-sectional view taken along line X8-X8';

[0020] Fig.11 shows a layout of an integrated circuit according to one or more embodiments;

[0021] Fig.12 An integrated circuit according to one or more embodiments is shown;

[0022] Fig.13An integrated circuit according to one or more embodiments is shown;

[0023] Fig.14 shows a layout of an integrated circuit according to one or more embodiments;

[0024] Fig.15 According to one or more embodiments Fig.14 A perspective view of an integrated circuit;

[0025] Fig.16 shows a layout of an integrated circuit according to one or more embodiments;

[0026] Fig.17 According to one or more embodiments Fig.16 A perspective view of an integrated circuit;

[0027] Fig.18 shows a layout of an integrated circuit according to one or more embodiments;

[0028] Fig.19 is a circuit diagram of a power gate switch according to one or more embodiments;

[0029] Fig. 20A According to one or more embodiments, Fig.18 A cross-sectional view taken along line X9-X9', and Fig. 20B According to one or more embodiments, Fig.18 A cross-sectional view taken along line X10-X10';

[0030] Fig.21 shows a layout of an integrated circuit according to one or more embodiments;

[0031] Fig.22A According to one or more embodiments, Fig.21 A cross-sectional view taken along line X11-X11', and Fig. 22B According to one or more embodiments, Fig.21 A cross-sectional view taken along line X12-X12';

[0032] Fig.23 shows a layout of an integrated circuit according to one or more embodiments;

[0033] Fig.24 is a circuit diagram of a power gate switch according to one or more embodiments;

[0034] Fig.25A According to one or more embodiments, Fig.23 A cross-sectional view taken along line X13-X13', and Fig.25B According to one or more embodiments, Fig.23 A cross-sectional view taken along line X14-X14';

[0035] Fig.26 shows a layout of an integrated circuit according to one or more embodiments;

[0036] Fig. 27 is a circuit diagram of a power gate switch according to one or more embodiments;

[0037] Fig.28A According to one or more embodiments, Fig.26 A cross-sectional view taken along line X15-X15', and Fig.28B According to one or more embodiments, Fig.26 A cross-sectional view taken along line X16-X16';

[0038] FIG. 29A to FIG. 29D is a diagram illustrating a device according to some embodiments;

[0039] Fig.30 is a flow chart of a method of manufacturing an integrated circuit according to one or more embodiments;

[0040] Fig.31 is a block diagram of a system on a chip according to one or more embodiments; and

[0041] Fig.32 is a block diagram of a computing system including a memory storing programs according to one or more embodiments. DETAILED DESCRIPTION

[0042] Hereinafter, the present disclosure will be described more comprehensively with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. In the accompanying drawings, the same reference numerals may refer to the same elements, and the repeated description of the same elements will be omitted. It should be understood that when an element or layer is referred to as "on ... ", "above ... ", "above ... ", "below ... ", "below ... ", "below ... ", "connected to " or "coupled to " another element or layer, it can be directly on another element or layer, above, above, below, below, below, connected or coupled to another element or layer, or there may be an intermediate element or layer. On the contrary, when an element is referred to as "directly on another element or layer", "directly above another element or layer", "directly above another element or layer", "directly below another element or layer", "directly below another element or layer", "directly below another element or layer", "directly below another element or layer", "directly connected to another element or layer" or "directly coupled to another element or layer", there is no intermediate element or layer.

[0043] Herein, the X-axis direction may be referred to as a first horizontal direction or a first direction, the Y-axis direction may be referred to as a second horizontal direction or a second direction, and the Z-axis direction may be referred to as a vertical direction. A plane formed by the X-axis and the Y-axis may be referred to as a horizontal plane.

[0044] Figure 1 A layout of an integrated circuit 10 is shown in accordance with one or more embodiments.

[0045] refer to Figure 1 , the integrated circuit 10 may include active regions RX1 and RX2, a gate line structure GT, a backside contact BCA, a first backside via BVA, and a first backside wiring layer BM1. The active regions RX1 and RX2 may each extend in a first direction X and may be spaced apart from each other in a second direction Y. The gate line structures GT may each extend in the second direction Y and may be spaced apart from each other in the first direction X. The active regions RX1 and RX2 and the gate line structure GT may constitute a transistor.

[0046] The integrated circuit 10 may include a power gate switch PG1 implemented with the active region RX1 and the gate line structure GT1, and the power gate switch PG1 may correspond to Figure 2 The power gate switch PG1 of the integrated circuit 10 is provided. According to one or more embodiments, the power gate switch PG1 may be referred to as a power gate circuit or a power switch. According to one or more embodiments, the first backside wiring layer BM1 may be used to provide a supply voltage to the power gate switch PG1, thereby improving the power performance area (PPA) of the integrated circuit 10.

[0047] The first backside wiring layer BM1 may include a first backside pattern 11a, a second backside pattern 11b, and a third backside pattern 11c, each extending in a first direction X. The first backside pattern 11a and the second backside pattern 11b may be spaced apart from each other in the first direction X, and the third backside pattern 11c may be spaced apart from the first backside pattern 11a and the second backside pattern 11b in the second direction Y. For example, the first backside pattern 11a and the second backside pattern 11b may be generated by applying a cutting layer to the backside wiring extending in the first direction (X). In this way, the area of ​​the integrated circuit 10 may be reduced by applying different voltages to patterns (e.g., the first backside pattern 11a and the second backside pattern 11b) disposed on the same trace of the same layer (such as the first backside wiring layer BM1) using a cutting layer. According to one or more embodiments, an extending direction of each of the first, second, and third backside patterns 11a, 11b, and 11c and an arrangement of the first, second, and third backside patterns 11a, 11b, and 11c may vary.

[0048] The first backside via BVA may be disposed on the first backside wiring layer BM1 and may be electrically connected to the first backside wiring layer BM1. The first backside via BVA may include a backside via 12a electrically connected to the first backside pattern 11a and the third backside pattern 11c, and a backside via 12b electrically connected to the second backside pattern 11b. The backside via 12a may extend in the second direction Y. According to one or more embodiments, the extension direction of each of the backside vias 12a and 12b and the arrangement of the backside vias 12a and 12b may vary.

[0049] The backside contact BCA may be disposed on the first backside via BVA and may be electrically connected to the first backside via BVA. The backside contact BCA may include a backside contact 13a electrically connected to the first via 12a and a backside contact 13b electrically connected to the backside via 12b. The source / drain region of the active region RX2 may be electrically connected to the third backside pattern 11c through the backside contact 13c and the backside via 12a. The source / drain region (e.g., Figure 3A SD1 in the active region RX1) can be electrically connected to the first backside pattern 11a through the backside contact 13a and the backside via 12a, and the source / drain region of the active region RX1 (eg, Figure 3A The back side pattern SD2) in the embodiment may be electrically connected to the second back side pattern 11b through the back side contact 13b and the back side via 12b.

[0050] Figure 2 is a circuit diagram of a power gate switch PG1 according to one or more embodiments.

[0051] Reference together Figure 1 and Figure 2 , the power gate switch PG1 may include a transistor TR including a source receiving a first power supply voltage, a gate receiving a power gate signal PGE, and a drain providing a second power supply voltage. For example, the first power supply voltage may correspond to a global power supply voltage VDDG or an external power supply voltage VDDPE, and the second power supply voltage may correspond to a virtual power supply voltage VDD or an internal power supply voltage VDDP. The power gate switch PG1 may selectively connect a global power supply line (e.g., backside pattern 11a) to which the global power supply voltage VDDG is applied to a virtual power supply line (e.g., backside pattern 11b) to which the virtual power supply voltage VDD is provided. Therefore, the driving voltage (i.e., virtual power supply voltage VDD) provided to the logic transistor included in the integrated circuit 10 may be adjusted, and thus the power mode of the integrated circuit 10 may be adjusted.

[0052] In the power-on mode, when the power gate signal PGE is at an enable level (e.g., a logic low level), the transistor TR may be turned on, and the global power supply voltage VDDG applied to the source may be delivered to, for example, the drain of the transistor TR as a power signal, so that the drain of the transistor TR may provide a virtual power supply voltage VDD to another circuit element based on the power signal from the source. For example, the power gate switch PG1 may provide a virtual power supply voltage VDD to a logic transistor (e.g., Figure 7 The LOGIC in the integrated circuit 10 provides a virtual power supply voltage VDD, and thus the logic transistors of the integrated circuit 10 can operate normally. Here, the virtual power supply voltage VDD may not be equal to the global power supply voltage VDDG. For example, due to an IR drop at a channel structure connecting the source region and the drain region, the virtual power supply voltage VDD may be less than the global power supply voltage VDDG.

[0053] In the power-off mode, when the power gate signal PGE is at a disabled level (e.g., a logic high level), the transistor TR may be turned off, and the global power supply voltage VDDG applied to the source of the transistor TR may not be delivered to the drain of the transistor TR. Therefore, the power gate switch PG1 may not provide the virtual power supply voltage VDD to the logic transistor, and thus the power consumption of the integrated circuit 10 may be reduced.

[0054] Figure 3A According to one or more embodiments, Figure 1 A cross-sectional view taken along line X1-X1', and Figure 3B According to one or more embodiments, Figure 1 A cross-sectional view taken along line X2-X2'.

[0055] Reference together Figures 1 to 3B , the integrated circuit 10 may be implemented as a semiconductor device, and a substrate SUB on which the semiconductor device is formed may have a first surface or first side FS and a second surface or second side BS. For example, the first side FS may be a side on which a circuit device such as a transistor is disposed, and the first side FS may be referred to as a “front side FS”. The second side BS may be a side opposite to the first side FS, and the second side BS may be referred to as a “back side BS”.

[0056] The integrated circuit 10 may implement a power distribution network (PDN) using a front-side wiring layer and a back-side wiring layer. Therefore, some signals and / or power applied to the integrated circuit 10 may be transmitted through the front-side wiring layer (i.e., the front-side PDN (FSPDN)), and other signals and / or power may be transmitted through the back-side wiring layer (i.e., the back-side PDN (BSPDN)). Therefore, compared with a structure in which wires are arranged only on the front side FS of the substrate SUB, the wiring complexity may be greatly reduced, and the length of each wire or each via may also be reduced, thereby improving the performance of the integrated circuit 10.

[0057] The substrate SUB may include any one of silicon, silicon on insulator, silicon on sapphire, germanium, silicon germanium, and gallium arsenide. A bottom dielectric (or diffusion) isolation (BDI) layer may be provided over the substrate SUB. The BDI layer may include an insulating material. The insulating material may include any one of an oxide layer, a nitride layer, and an oxynitride layer.

[0058] According to some embodiments, the substrate SUB may correspond to a bulkless substrate. In the process of manufacturing the integrated circuit 10, a gate line structure, a source / drain region, a contact, a via, and / or a wiring layer may be formed on the front surface of the substrate SUB, thereby forming a device wafer. Subsequently, the device wafer may be temporarily bonded to a carrier wafer, and a back grinding process may be performed on the device wafer, thereby removing at least a portion of the substrate SUB. Therefore, a wafer obtained by back grinding the substrate so that the height of the substrate is equal to or less than the reference height may be referred to as a "bulkless wafer" or "bulkless substrate".

[0059] The active regions RX1 and RX2 may be limited by a device isolation layer (e.g., shallow trench isolation (STI)) and may be referred to as diffusion regions. Diffusion regions are regions doped with impurities that change the electrical properties of the substrate material and may form source / drain regions SD of the transistor. The source / drain regions SD may include epitaxial regions of semiconductor materials such as silicon, boron, phosphorus, germanium, carbon, SiGe, and / or SiC.

[0060] The nanosheet stack NS extending in the first direction X may be disposed on the front side FS of the substrate SUB. The nanosheet stack NS may include a plurality of nanosheets overlapping in the vertical direction Z, for example, a first nanosheet NS1 to a third nanosheet NS3. For example, the nanosheet stack NS may be doped with N-type impurities and may form an N-type transistor. As another example, the nanosheet stack NS may be doped with P-type impurities and may form a P-type transistor. The nanosheet stack NS may include Si, Ge, or SiGe. According to one or more other embodiments, the nanosheet stack NS may include InGaAs, InAs, GaSb, InSb, or a combination thereof.

[0061] The gate line structures GT may each extend in the second direction Y and may be spaced apart from each other in the first direction X. Each of the gate line structures GT may surround the first to third nanosheets NS1 to NS3 while surrounding the nanosheet stack NS. Therefore, the first to third nanosheets NS1 to NS3 may have a gate-all-around (GAA) structure. The gate line structure GT may be defined as a conductive segment including a conductive material such as polysilicon or one or more metals. A gate insulating layer may be interposed between each of the gate line structures GT and the first to third nanosheets NS1 to NS3.

[0062] Therefore, the integrated circuit 10 may include a nanosheet stack NS, but the present disclosure is not limited thereto. According to some embodiments, the integrated circuit 10 may include a fin structure instead of a nanosheet stack NS, and therefore, the transistor included in the integrated circuit 10 may be implemented as a fin field effect transistor (FinFET). The power gate switch according to the embodiment is now shown as a multi-bridge channel field effect transistor (MBCFET) including a nanosheet stack NS. However, this is only one or more embodiments, and the power gate switch according to the embodiment may be implemented in various ways, such as referring to FIG. 29A to FIG. 29D Described in more detail.

[0063] The first backside pattern 11a may be electrically connected to the source / drain region SD1 through the backside via 12a and the backside contact 13a. The source / drain region SD1 may correspond to the source region of the power gate switch PG1. The second backside pattern 11b may be electrically connected to the source / drain region SD2 through the backside via 12b and the backside contact 13b. The source / drain region SD2 may correspond to the drain region of the power gate switch PG1. The third backside pattern 11c may be electrically connected to the source / drain region SDa through the backside via 12a and the backside contact 13c.

[0064] In this way, the backside vias 12a and 12b and the backside contacts 13a to 13c can connect the layers and elements on the back side BS to the elements on the front side FS, such as the source / drain regions SD1-SD3. The structure that connects the contact to the bottom surface of each of the source / drain regions SD1-SD3 may be referred to as a "direct backside contact (DBC)". According to one or more embodiments, the DBC may include a backside contact and / or a backside via. However, the present disclosure is not limited thereto, and according to one or more other embodiments, the backside contact and the backside via connected thereto may be formed as a single contact structure in the form of a through hole.

[0065] The gate line structure GT1 and the source / drain regions SD1 and SD2 may form a power gate switch PG1. The gate line structure GT1 may be driven according to a power gate signal PGE. The first backside pattern 11a may receive a first power supply voltage, such as an always-on power supply or a global power supply voltage VDDG, and may therefore be referred to as a global power supply line. The second backside pattern 11b may receive a second power supply voltage, such as a power supply voltage or a virtual power supply voltage VDD, and may therefore be referred to as a virtual power supply line.

[0066] The source / drain region SD1 (e.g., source region) may be electrically connected to the first backside pattern 11a through the backside contact 13a and the backside via 12a, and may receive the global power supply voltage VDDG from the first backside pattern 11a. The source / drain region SD2 (e.g., drain region) may transmit the second power supply voltage (e.g., virtual power supply voltage VDD) to the second backside pattern 11b through the backside contact 13b and the backside via 12b. The integrated circuit 10 may respond to the control signal (e.g., Figure 2 The power gate signal PGE of the integrated circuit 10 selectively connects the first backside pattern 11a to the second backside surface pattern 11b, thereby selectively transmitting the global power supply voltage VDDG applied to the first backside pattern 11a to the second backside pattern 11b. Therefore, the driving voltage and power mode of the elements included in the integrated circuit 10 can be adjusted, and thus the power consumption of the integrated circuit 10 can be improved.

[0067] As described above, the integrated circuit 10 can implement the PDN by using the backside wiring layer including the first backside wiring layer BM1. Therefore, the power applied to the source / drain region can be transmitted through the backside wiring layer, and the signal applied to the source / drain region and / or the gate line structure can be transmitted through the frontside wiring layer. Therefore, according to the present embodiment, compared with the structure in which the wires are arranged only on the front side of the substrate, the wiring complexity can be greatly reduced, and the length of each wire or each via can also be reduced, thereby improving the performance of the integrated circuit 10. In addition, the global power supply voltage VDDG applied to the source / drain region SDa on the active region RX2 can also be transmitted to the source / drain region SD1 on the active region RX1 that has been powered by the global power supply voltage VDDG through the backside via 12a. Therefore, the virtual power supply voltage VDD provided from the source / drain region SD2 connected to the source / drain region SD1 can have a further improved power supply performance.

[0068] Figure 4 A layout of an integrated circuit 20 is shown according to one or more embodiments.

[0069] refer to Figure 4 , the integrated circuit 20 may correspond to Figure 1A modification of the integrated circuit 10 and with Figure 1 Compared with the integrated circuit 10, the integrated circuit 20 may further include a second backside via BV1 and a second backside wiring layer BM2. According to one or more embodiments, the integrated circuit 20 may include a power gate circuit or a power gate switch PG2 implemented with the active region RX1 and the gate line structures GT1, GT2 and GT3, and the power gate switch PG2 may correspond to Figure 5 The power gate switch PG1.

[0070] The first backside wiring layer BM1 may include backside patterns 21a to 21d. The second backside wiring layer BM2 may include backside wirings 22a and 22b insulated from each other. Each of the backside wirings 22a and 22b may be implemented as a polygon including a bidirectional pattern including a pattern extending in the first direction X and a pattern extending in the second direction Y. The backside wiring 22a may receive a first power supply voltage (e.g., a global power supply voltage VDDG), and the backside wiring 22b may receive a second power supply voltage (e.g., a virtual power supply voltage VDD). The second backside vias BV1 may be respectively disposed between the second backside wiring layer BM2 and the first backside wiring layer BM1. The first backside vias BVA may be respectively disposed between the first backside wiring layer BM1 and the backside contacts BCA. The first backside vias BVA may include backside vias 23a and 23b, each of which extends in the second direction Y.

[0071] Figure 5 is a circuit diagram of a power gate switch PG2 according to one or more embodiments.

[0072] Reference together Figure 4 and Figure 5 , the power gate switch PG2 may include a first transistor TR1, a second transistor TR2, and a third transistor TR3 connected in parallel to each other. Each of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may include a source receiving a first power supply voltage, a gate receiving a power gate signal PGE, and a drain providing a second power supply voltage. For example, the first power supply voltage may correspond to a global power supply voltage VDDG or an external power supply voltage VDDPE, and the second power supply voltage may correspond to a virtual power supply voltage VDD or an internal power supply voltage VDDP. The power gate switch PG2 may selectively connect a global power supply line (e.g., backside wiring 22a) to which the global power supply voltage VDDG is applied to a virtual power supply line (e.g., backside wiring 22b) to which the virtual power supply voltage VDD is provided. Therefore, the driving voltage (i.e., virtual power supply voltage VDD) provided to the logic transistor included in the integrated circuit 20 may be adjusted, and thus the power mode of the integrated circuit 20 may be adjusted.

[0073] In the power-on mode, when the power gate signal PGE is at an enable level (e.g., a logic low level), the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be turned on, and the global power supply voltage VDDG applied to the sources of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be transmitted to the drains of the first transistor TR1, the second transistor TR2, and the third transistor TR3 as a power signal (e.g., a virtual power supply voltage VDD), so that the drains of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may provide the virtual power supply voltage VDD to another circuit element. For example, the power gate switch PG2 may provide the virtual power supply voltage VDD to a logic transistor (e.g., a logic transistor 100) included in the integrated circuit 20. Figure 7 LOGIC in the integrated circuit 20), and thus the logic transistors of the integrated circuit 20 can operate normally.

[0074] In the power-off mode, when the power gate signal PGE is at a disabled level (e.g., a logic high level), the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be turned off, and the global power supply voltage VDDG applied to the source of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may not be transmitted to the drain of the first transistor TR1, the second transistor TR2, and the third transistor TR3. Therefore, the power gate switch PG2 may not provide the virtual power supply voltage VDD to the logic transistor, so the power consumption of the integrated circuit 20 may be reduced.

[0075] The active region RX1 and the gate line structure GT1 may form a first transistor TR1, the active region RX1 and the gate line structure GT2 may form a second transistor TR2, and the active region RX1 and the gate line structure GT3 may form a third transistor TR3. Fig. 6A and 6B Integrated circuit 20 is described in more detail.

[0076] Fig. 6A According to one or more embodiments, Figure 4 A cross-sectional view taken along line X3-X3', and Figure 6B According to one or more embodiments, Figure 4 A cross-sectional view taken along line X4-X4'.

[0077] Reference together Figures 4 to 6B, the backside wiring 22a can receive a first power supply voltage, such as a global power supply voltage VDDG. The backside patterns 21a and 21b can receive the first power supply voltage from the backside wiring 22a through the second backside via BV1, respectively. The first backside vias 23a and 23b can be respectively disposed on the backside patterns 21a and 21b, and can each extend in the second direction Y. Therefore, the first backside vias 23a and 23b can receive the first power supply voltage from the backside wiring 22a through the backside patterns 21a and 21b and the second backside via BV1, respectively.

[0078] The source / drain region SD may include first, second, third and fourth source / drain regions SD1, SD2, SD3 and SD4. The gate line structure GT1 and the first source / drain region SD1 and the second source / drain region SD2 may form a first transistor TR1, the gate line structure GT2 and the second source / drain region SD2 and the third source / drain region SD3 may form a second transistor TR2, and the gate line structure GT3 and the third source / drain region SD3 and the fourth source / drain region SD4 may form a third transistor TR3.

[0079] In the first transistor TR1, the first source / drain region SD1 may correspond to the drain region, and the second source / drain region SD2 may correspond to the source region. The second source / drain region SD2 may be electrically connected to the first backside via 23a through the backside contact BCA. The second source / drain region SD2 may receive the first power supply voltage from the backside wiring 22a through the second backside via BV1, the backside pattern 21a, the first backside via 23a, and the backside contact BCA. When the power gate signal PGE is at the enable level, the first transistor TR1 may be turned on, and the first source / drain region SD1 may transmit the virtual power supply voltage VDD to the backside wiring 22b through the backside contact BCA, the first backside via BVA, the backside pattern 21c, and the second backside via BV1.

[0080] In the second transistor TR2, the second source / drain region SD2 may correspond to the source region, and the third source / drain region SD3 may correspond to the drain region. The second source / drain region SD2 may be electrically connected to the first backside via 23a through the backside contact BCA. The second source / drain region SD2 may receive the first power supply voltage from the backside wiring 22a through the second backside via BV1, the backside pattern 21a, the first backside via, and the backside contact BCA. When the power gate signal PGE is at the enable level, the second transistor TR2 may be turned on, and the third source / drain region SD3 may transmit the virtual power supply voltage VDD to the backside wiring 22b through the backside contact BCA, the first backside via BVA, the backside pattern 21d, and the second backside via BV1.

[0081] In the third transistor TR3, the third source / drain region SD3 may correspond to the drain region, and the fourth source / drain region SD4 may correspond to the source region. The fourth source / drain region SD4 may be electrically connected to the first backside via 23b through the backside contact BCA. The fourth source / drain region SD4 may receive the first power supply voltage from the backside wiring 22a through the second backside via BV1, the backside pattern 21b, the first backside via 23b and the backside contact BCA. When the power gate signal PGE is at the enable level, the third transistor TR3 may be turned on, and the third source / drain region SD3 may transmit the virtual power supply voltage VDD to the backside wiring 22b through the backside contact BCA, the first backside via BVA, the backside pattern 21d and the second backside via BV1.

[0082] Figure 7 A layout of an integrated circuit 20 a is shown according to one or more embodiments. Fig. 8A According to one or more embodiments, Figure 7 A cross-sectional view taken along line X5-X5', and Figure 8B According to one or more embodiments, Figure 7 A cross-sectional view taken along line X6-X6'.

[0083] refer to Figures 7 to 8B , the integrated circuit 20a may correspond to Figure 4 A modification of the integrated circuit 20 and with Figure 4 Compared with the integrated circuit 20, the backside wiring 22a may further include a logic transistor LOGIC implemented in the active area RX3. For example, the logic transistor LOGIC may include a P-type transistor, but the present disclosure is not limited thereto. The first backside wiring layer BM1 may include backside patterns 21a to 21f. The second backside wiring layer BM2 may include backside wirings 22a and 22b' insulated from each other. Each of the backside wirings 22a and 22b' may be implemented as a polygon including a bidirectional pattern including a pattern extending in a first direction X and a pattern extending in a second direction Y. For example, the backside wiring 22a may receive a first power supply voltage, such as a global power supply voltage VDDG, and the backside wiring 22b' may receive a second power supply voltage, such as a virtual power supply voltage VDD.

[0084] When the power gate signal PGE is at the enable level, the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be turned on, and the virtual power supply voltage VDD may be supplied to the backside patterns 21c and 21d. The backside patterns 21c and 21d may be electrically connected to the backside wiring 22b' through the second backside via BV1, and thus, the backside wiring 22b' may receive the virtual power supply voltage VDD. In the logic transistor LOGIC, the source / drain region SDa may be electrically connected to the backside wiring 22b' through the backside contact BCA, the first backside via BVA, the backside pattern 21e, and the second backside via BV1, and the source / drain region SDb may be electrically connected to the backside wiring 22b' through the backside contact BCA, the first backside via BVA, the backside pattern 21f, and the second backside via BV1. Therefore, the source / drain regions SDa and SDb may receive the virtual film voltage VDD from the backside wiring 22b', and the P-type transistor included in the logic transistor LOGIC may operate normally.

[0085] Fig. 9 A layout of an integrated circuit 30 is shown according to one or more embodiments. Fig. 10A According to one or more embodiments, Fig. 9 A cross-sectional view taken along line X7-X7', and Fig. 10B According to one or more embodiments, Fig. 9 A cross-sectional view taken along line X8-X8'.

[0086] Reference together Figures 9 to 10B , the integrated circuit 30 may include active regions RX1 to RX3, a gate line structure GT, a contact CA, a backside contact BCA, a first backside via BVA, and a first backside wiring layer BM1. The active regions RX1 to RX3 may each extend in a first direction X and may be spaced apart from each other in a second direction Y. The gate line structures GT may each extend in the second direction Y and may be spaced apart from each other in the first direction X. The active regions RX1 to RX3 and the gate line structure GT may constitute a transistor. The integrated circuit 30 may include a power gate circuit or a power gate switch PG2 implemented with the active region RX1 and the gate line structures GT1, GT2, and GT3, and the power gate switch PG2 may correspond to Figure 5 The power gate switch PG2.

[0087] The contact CA may be disposed in the front side FS of the substrate SUB and may include contacts 33a and 33b each extending in the second direction Y. The first backside wiring layer BM1 may include backside patterns 31a to 31d. The backside patterns 31a and 31b may each extend in the first direction X and may be spaced apart from each other in the second direction Y. The first backside via BVA may be disposed on the first backside wiring layer BM1 and may be electrically connected to the first backside wiring layer BM1. The first backside via BVA may include a backside via 32a electrically connected to the backside patterns 31b and 31c and a backside via 32b electrically connected to the backside patterns 31b and 31d. The backside vias 32a and 32b may each extend in the second direction Y. The backside contact BCA may be disposed on the first backside via BVA and may be electrically connected to the first backside via BVA. According to one or more embodiments, an extending direction of each of the backside patterns 31a to 31d, the backside vias 32a and 32b, and the backside contacts BCA and an arrangement of the backside patterns 31a to 31d, the backside vias 32a and 32b, and the backside contacts BCA may vary.

[0088] The back pattern 31a can receive a first power supply voltage, such as a global power supply voltage VDDG. The back pattern 31a can be electrically connected to the source / drain regions SDa and SDb of the active region RX2 through the first back via BVA and the back contact BCA, respectively. Contacts 33a and 33b can be respectively arranged on the source / drain regions SDa and SDb. The source / drain regions SD2 and SD4 of the active region RX1 can be electrically connected to the source / drain regions SDa and SDb of the active region RX2 through contacts 33a and 33b, respectively. Therefore, the source / drain regions SD2 and SD4 can receive the first power supply voltage from the back pattern 31a through contacts 33a and 33b, source / drain regions SDa and SDb, back contacts BCA, and back vias BVA.

[0089] The gate line structures GT1 to GT3 and the source / drain regions SD1 to SD4 may form a power gate switch PG2, and the gate line structures GT1 to GT3 may be driven according to the power gate signal PGE. The source / drain regions SD1 and SD3 may transmit a second power supply voltage (e.g., a virtual power supply voltage VDD) to the backside pattern 31b through the backside contact BCA and the backside vias 32a and 32b, respectively. In addition, the logic transistor LOGIC may receive the virtual power supply voltage VDD through the backside vias 32a and 32b.

[0090] Fig.11 A layout of an integrated circuit 40 is shown according to one or more embodiments.

[0091] refer to Fig.11, the integrated circuit 40 may include active regions RX1 and RX2, a gate line structure GT, a backside contact BCA, a first backside via BVA, and a first backside wiring layer BM1. The integrated circuit 40 may include a power gate circuit or a power gate switch PG2 implemented with the active region RX1 and the gate line structures GT1, GT2, and GT3, and the power gate switch PG2 may correspond to Figure 5 The power gate switch PG2.

[0092] The first backside wiring layer BM1 may include backside patterns 41a to 41c. The backside pattern 41a may extend in the first direction X and may be spaced apart from the backside patterns 41b and 41c in the second direction Y. The backside pattern 41a may at least partially overlap with the active region RX2. The backside patterns 41b and 41c may at least partially overlap with the active region RX1. The first backside via BVA may be disposed on the first backside wiring layer BM1 and may be electrically connected to the first backside wiring layer BM1. The first backside via BVA may include backside vias 42a and 42b, each of which extends along the second direction Y on the backside pattern 41a. The backside contact BCA may be disposed on the first backside via BVA.

[0093] Fig.12 An integrated circuit 40 a according to one or more embodiments is shown.

[0094] refer to Fig.12 , the integrated circuit 40a may correspond to Fig.11 An implementation example of an integrated circuit 40 of the present invention. The integrated circuit 40a may include a power gate switch PG2a and an N-type transistor NFET. The power gate switch PG2a may include a first transistor TR1 including a gate line structure GT1, a second transistor TR2 including a gate line structure GT2, and a third transistor TR3 including a gate line structure GT3. The source region of each of the first transistor TR1 to the third transistor TR3 may receive a global power supply voltage VDDG from an epitaxial region (i.e., a source / drain region) of the N-type transistor NFET through a front wiring layer or a back wiring layer. For example, the N-type transistor NFET may be a dummy transistor. For example, the input terminal of the N-type transistor NFET may be floating.

[0095] Fig.13 An integrated circuit 40 b according to one or more embodiments is shown.

[0096] refer to Fig.13 , the integrated circuit 40b may correspond to Fig.11An implementation example of an integrated circuit 40 of the present invention is provided. The integrated circuit 40b may include a power gate switch PG2b and a P-type transistor PFET. The power gate switch PG2b may include a first transistor TR1 including a gate line structure GT1, a second transistor TR2 including a gate line structure GT2, and a third transistor TR3 including a gate line structure GT3. The drain region of each of the first transistor TR1 to the third transistor TR3 may transmit the virtual power supply voltage VDD to the epitaxial region, i.e., the source / drain region, of the P-type transistor PFET through the front wiring layer or the back wiring layer. For example, the P-type transistor PFET may be an actual transistor and may constitute a logic transistor. Therefore, one terminal of the P-type transistor PFET may provide a signal or an output signal.

[0097] Fig.14 A layout of an integrated circuit 50 is shown according to one or more embodiments. Fig.15 According to one or more embodiments Fig.14 A perspective view of an integrated circuit 50 is shown.

[0098] Reference together Fig.14 and Fig.15 , the integrated circuit 50 may include active regions RX1 and RX2, a gate line structure GT, a back contact BCA, a first back via layer BVA1, a second back via layer BVA2, and a first back wiring layer BM1. In this case, the first back via layer BVA1 and the second back via layer BVA2 may be disposed between the first back wiring layer BM1 and the back contact BCA, and may be stacked in the vertical direction Z. The second back via layer BVA2 may be disposed on the first back wiring layer BM1, the first back via layer BVA1 may be disposed on the second back via layer BVA2, and the back contact BCA may be disposed on the first back via layer BVA1. The integrated circuit 50 may include a power gate circuit or a power gate switch PG2 implemented with the active region RX2 and the gate line structures GT1, GT2, and GT3, and the power gate switch PG2 may correspond to Figure 5 The power gate switch PG2.

[0099] The first backside wiring layer BM1 may include backside patterns 51a and 51b, each extending in the first direction X and spaced apart from each other in the second direction Y. The active region RX1 may overlap the backside pattern 51a, and the active region RX2 may overlap the backside pattern 51b. The backside pattern 51a may receive a first power supply voltage, such as a global power supply voltage VDDG, and the backside pattern 51b may receive a second power supply voltage, such as a virtual power supply voltage VDD.

[0100] The second backside via layer BVA2 may include second backside vias 52a and 52c disposed on the backside pattern 51a, and second backside vias 52b and 52d disposed on the backside pattern 51b. The first backside via layer BVA1 may include first backside vias 53a to 53d disposed on the second backside vias 52a to 52d, respectively. In this case, the first backside vias 53a and 53c may each extend in the second direction Y. In this way, according to the present embodiment, two layers including a first layer (e.g., a first backside via layer BVA1) and a second layer (e.g., a second backside via layer BVA2) may be arranged between the first backside wiring layer BM1 and the backside contact BCA, thereby realizing the power gate switch PG2 without forming a dummy transistor.

[0101] Fig.16 A layout of an integrated circuit 50 a is shown according to one or more embodiments. Fig.17 According to one or more embodiments Fig.16 1 is a perspective view of an integrated circuit 50a.

[0102] Reference together Fig.16 and Fig.17 , the integrated circuit 50a may include active regions RX1 and RX2, a gate line structure GT, a backside contact BCA, a first backside via layer BVA1, a second backside via layer BVA2, and a first backside wiring layer BM1. The integrated circuit 50a may correspond to Fig.14 For example, the integrated circuit 50a may include a power gate switch circuit or power gate switch PG2' including a first transistor TR1, a second transistor TR2, a third transistor TR3, and a fourth transistor TR4 connected in parallel to each other.

[0103] The second backside via layer BVA2 may include second backside vias 52e to 52i electrically connected to the backside pattern 51a and second backside vias 52e' to 52h' electrically connected to the backside pattern 51b. The first backside via layer BVA1 may include first backside vias 53e to 53i electrically connected to the second backside vias 52e to 52i and first backside vias 53e' to 53h' electrically connected to the second backside vias 52e' to 52h'.

[0104] The sources of the first transistor TR1 and the second transistor TR2 may receive the first power supply voltage from the back pattern 51a through the first back via 53f and the back contact BCA extending in the second direction Y, and the source of the fourth transistor TR4 may receive the first power supply voltage from the back pattern 51a through the first back via 53i and the back contact BCA extending in the second direction Y. In this way, according to the present embodiment, two layers including a first layer (e.g., a first back via layer BVA1) and a second layer (e.g., a second back via layer BVA2) may be arranged between the first back wiring layer BM1 and the back contact BCA, thereby realizing the power gate switch PG2' without forming a dummy transistor.

[0105] Fig.18 A layout of an integrated circuit 60 is shown according to one or more embodiments.

[0106] refer to Fig.18 , the integrated circuit 60 may include active regions RX1 and RX2, a gate line structure GT, a contact CA, a via VA, a front wiring layer M1, a back contact BCA, a back via BVA, and a back wiring layer BM1. The integrated circuit 60 may correspond to Figure 1 The integrated circuit 10 or Figure 4 A modification of the integrated circuit 20 and with Figure 4 Compared with the integrated circuit 20 of FIG. 1 , the integrated circuit 60 may further include a contact CA, a via VA, a front wiring layer M1, and a back contact BVA. According to one or more embodiments, the integrated circuit 60 may include a power gate switch PG3 implemented with the active region RX1 and the gate line structures GT1, GT2, and GT3, and the power gate switch PG3 may correspond to Fig.19 The integrated circuit 60 may further include a logic transistor, such as a P-type transistor PFET, implemented in the active region RX2. Fig.19 The power gate switch PG3 is described.

[0107] Fig.19 is a circuit diagram of a power gate switch PG3 according to one or more embodiments.

[0108] Reference together Fig.18 and Fig.19 , the power gate switch PG3 may include a first transistor TR1, a second transistor TR2, and a third transistor TR3 connected in series with each other. The active region RX1 and the gate line structure GT1 may form the first transistor TR1, the active region RX1 and the gate line structure GT2 may form the second transistor TR2, and the active region RX1 and the gate line structure GT3 may form the third transistor TR3. In addition, the second transistor TR2 and the third transistor TR3 may be used as dummy transistors.

[0109] The first transistor TR1 may include a source receiving a first power supply voltage (such as a global power supply voltage VDDG), a gate receiving a power supply gate signal PGE, and a drain providing a second power supply voltage (such as a virtual power supply VDD). The respective gates of the second transistor TR2 and the third transistor TR3 may receive the power supply gate signal PGE. The source and drain of the second transistor TR2 may be commonly connected to the drain of the first transistor TR1. The source and drain of the third transistor TR3 may be commonly connected to the drain of the first transistor TR1.

[0110] Fig. 20A According to one or more embodiments, Fig.18 A cross-sectional view taken along line X9-X9', and Fig. 20B According to one or more embodiments, Fig.18 A cross-sectional view taken along line X10-X10'.

[0111] Reference together Figures 18 to 20B , the backside wiring layer BM1 may include a backside pattern 61a extending in the first direction X under the substrate SUB. The first backside via BVA may be provided on the backside wiring layer BM1, and may include a first backside via 62 extending in the second direction Y. The backside contact BCA may be provided on the first backside via 62, and include backside contacts 63a and 63b spaced apart from each other in the second direction Y. The contact CA may be placed above the active region RX1. The vias VA may be provided on the contacts CA, respectively. The frontside wiring layer M1 may include a frontside pattern 64a extending in the first direction X.

[0112] The first backside via 62 may extend in the second direction Y on the backside pattern 61a. For example, the first backside via 62 may at least partially overlap the active regions RX1 and RX2. The backside contact 63a may be placed between the first backside via 62 and the source / drain region SD1 of the active region RX1, and the backside contact 63b may be placed between the first backside via 62 and the source / drain region SDa of the active region RX2. The source / drain region SDa may be electrically connected to the first backside pattern 61a through the backside contact 63a and the backside via 62, and may receive a first power supply voltage, such as a global power supply voltage VDDG, from the first backside pattern 61a.

[0113] The contacts CA may be disposed on the source / drain regions SD2, SD3, and SD4 of the active region RX1, respectively. The front side pattern 64a may be electrically connected to the source / drain regions SD2, SD3, and SD4 through the vias VA and the contacts CA. The source / drain regions SD2, SD3, and SD4 may transmit a second power supply voltage (e.g., a virtual power supply voltage VDD) to the front side pattern 64a through the contacts CA and the vias VA.

[0114] Fig.21 A layout of an integrated circuit 60 a is shown according to one or more embodiments. Fig.22A According to one or more embodiments, Fig.21 A cross-sectional view taken along line X11-X11', and Fig. 22B According to one or more embodiments, Fig.21 A cross-sectional view taken along line X12-X12'.

[0115] Reference together Figures 21 to 22B , the integrated circuit 60a may correspond to Fig.18 Modification of the integrated circuit 60. The backside wiring layer BM1 may include a backside pattern 61b extending in the first direction X, and the frontside wiring layer M1 may include a frontside pattern 64b extending in the first direction X. The contact CA may extend in the second direction Y above the substrate SUB. The contact CA may at least partially overlap with the active regions RX1 and RX2. The contact CA may receive a first power supply voltage, such as a global power supply voltage VDDG, from the frontside pattern 64b through the via VA. The source / drain region SDa of the active region RX2 may be electrically connected to the frontside pattern 64b through the contact CA and the via VA.

[0116] The backside vias BVA may be disposed on the backside pattern 61b and may be spaced apart from each other in the first direction X. The backside contacts BCA may be disposed on the backside vias BVA, respectively. Therefore, the source / drain regions SD2, SD3, and SD4 may be electrically connected to the backside pattern 61b through the backside contacts BCA and the backside vias BVA. The source / drain regions SD2, SD3, and SD4 may transmit a second power supply voltage (e.g., a virtual power supply voltage VDD) to the backside pattern 61b through the backside contacts BCA and the backside vias BVA.

[0117] Fig.23 A layout of an integrated circuit 70 is shown according to one or more embodiments.

[0118] refer to Fig.23 , the integrated circuit 70 may include active regions RX1 and RX2, a gate line structure GT, a contact CA, a backside contact BCA, a backside via BVA, and a backside wiring layer BM1. The integrated circuit 70 may correspond to Figure 1The integrated circuit 10 or Figure 4 A modification of the integrated circuit 20 and with Figure 4 Compared with the integrated circuit 20, the integrated circuit 70 may further include a contact CA. According to one or more embodiments, the integrated circuit 70 may include a power gate switch PG4 implemented with active regions RX1 and RX2 and gate line structures GT1 to GT4, and the power gate switch PG4 may correspond to Fig.24 The power gate switch PG4 is shown below. Fig.24 The power gate switch PG4 is described.

[0119] Fig.24 is a circuit diagram of a power gate switch PG4 according to one or more embodiments.

[0120] Reference together Fig.23 and Fig.24 , the power gate switch PG4 may include a first transistor TR1, a second transistor TR2', and a third transistor TR3' connected in series with each other, and a fourth transistor TR4, a fifth transistor TR5, and a sixth transistor TR6 connected in series with each other. The active regions RX1 and RX2 and the gate line structure GT1 may form the first transistor TR1, the active regions RX1 and RX2 and the gate line structure GT2 may form the second transistor TR2', and the active region RX1 and the gate line structure GT3 may form the third transistor TR3'. In addition, the active regions RX1 and RX2 and the gate line structure GT6 may form the fourth transistor TR4, the active regions RX1 and RX2 and the gate line structure GT5 may form the fifth transistor TR5, and the active region RX1 and the gate line structure GT4 may form the sixth transistor TR6.

[0121] The first transistor TR1 to the sixth transistor TR6 may be driven according to the power gate signal PGE. Each of the first transistor TR1 and the fourth transistor TR4 may include a source receiving a first power supply voltage (e.g., a global power supply voltage VDDG). The respective drains of the first transistor TR1 and the fourth transistor TR4 may be electrically connected to each other. The source and drain of the second transistor TR2' may be commonly connected to the drain of the first transistor TR1, and the source and drain of the fifth transistor TR5 may be commonly connected to the drain of the fourth transistor TR4. The respective drains of the second transistor TR2' and the fifth transistor TR5 may be electrically connected to each other. Therefore, the second transistor TR2' and the fifth transistor TR5 may be used as dummy transistors. Each of the third transistor TR3 and the sixth transistor TR6 may include a drain providing a second power supply voltage (e.g., a virtual power supply voltage VDD).

[0122] Fig.25A According to one or more embodiments, Fig.23A cross-sectional view taken along line X13-X13', and Fig.25B According to one or more embodiments, Fig.23 A cross-sectional view taken along line X14-X14'.

[0123] Reference together Figures 23 to 25B , the backside wiring layer BM1 may include backside patterns 71a to 71c, each of which extends in the first direction X below the substrate SUB. The backside via BVA may be provided on the backside wiring layer BM1, and may include backside vias 72a and 72b. The backside contact BCA may be provided on the backside via BVA, and may include, for example, backside contacts 73a and 73c on the backside via 72a that are spaced apart from each other in the second direction Y, and backside contacts 73b and 73d on the backside via 72b that are spaced apart from each other in the second direction Y. The contact CA may be provided over the active regions RX1 and RX2, and may include, for example, contacts 74a and 74b.

[0124] The back pattern 71a may receive a first power supply voltage, such as a global power supply voltage VDDG. The back through hole 72a may be disposed on the back pattern 71a and may extend in the second direction Y. The back contact 73a may be placed between the back through hole 72a and the source / drain region SD1 of the active region RX2, and the back contact 73c may be placed between the back through hole 72a and the source / drain region SD5 of the active region RX1. The source / drain region SD1 may be electrically connected to the back pattern 71a through the back contact 73a and the back through hole 72a, and may receive a first power supply voltage from the back pattern 71a. The source / drain region SD5 may be electrically connected to the back pattern 71a through the back contact 73c and the back through hole 72a, and may receive a first power supply voltage from the back pattern 71a. For example, the source of the first transistor TR1 may receive a global power supply voltage VDDG from the back pattern 71a.

[0125] The contact 74a may extend in the second direction Y and may be electrically connected to the source / drain regions SD2 and SD6. The contact 74a may extend in the second direction Y and may be electrically connected to the source / drain regions SD3 and SD7. The source / drain region SD8 may be electrically connected to the back pattern 71c through the back contact 73d and the back through hole 72b, and a second power supply voltage may be transmitted from the back pattern 71c. For example, the drain of the third transistor TR3 may transmit a virtual power supply voltage VDD from the back pattern 71c.

[0126] Fig.26 A layout of an integrated circuit 80 is shown according to one or more embodiments.

[0127] refer to Fig.26, the integrated circuit 80 may include active regions RX1 and RX2, a gate line structure GT, a contact CA, a via VA, a front wiring layer M1, a back contact BCA, a back via BVA, and a back wiring layer BM1. The integrated circuit 80 may correspond to Figure 1 The integrated circuit 10 or Figure 4 A modification of the integrated circuit 20 and with Figure 4 Compared with the integrated circuit 20 of FIG. 1 , the integrated circuit 80 may further include a contact CA, a via VA, and a front wiring layer M1. According to one or more embodiments, the integrated circuit 80 may include a power gate circuit or a power gate switch PG5 implemented with the active region RX1 and the gate line structures GT1, GT2, GT3, GT4, GT5, GT6, and GT7, and the power gate switch PG5 may correspond to Fig. 27 The integrated circuit 80 may further include a logic transistor LOGIC implemented in the active region RX2, such as a P-type transistor PFET. Fig. 27 The power gate switch PG5 is described.

[0128] Fig. 27 is a circuit diagram of a power gate switch PG5 according to one or more embodiments.

[0129] Reference Fig. 27 , the power gate switch PG5 may include a first transistor TR1, a second transistor TR2″ and a third transistor TR3′ connected in series with each other, and a fourth transistor TR4, a fifth transistor TR5′ and a sixth transistor TR6 connected in series with each other. The active region RX1 and the gate line structure GT1 may form a first transistor TR1, the active region RX1 and the gate line structure GT2 may form a second transistor TR2″, and the active region RX1 and the gate line structure GT3 may form a third transistor TR3′. In addition, the active regions RX1 and RX2 and the gate line structure GT7 may form a fourth transistor TR4, the active region RX1 and the gate line structure GT6 may form a fifth transistor TR5′, and the active region RX1 and the gate line structure GT5 may form a sixth transistor TR6. In this case, the gate line structure GT4 may correspond to a dummy gate line structure.

[0130] The first transistor TR1 to the sixth transistor TR6 may be driven according to the power gate signal PGE. Each of the first transistor TR1 and the fourth transistor TR4 may include a source that receives a first power supply voltage (e.g., a global power supply voltage VDDG). The source and the drain of the second transistor TR2" may be commonly connected to the drain of the first transistor TR1, and the source and the drain of the fifth transistor TR5' may be commonly connected to the drain of the fourth transistor TR4. Therefore, the second transistor TR2" and the fifth transistor TR5' may be used as dummy transistors. Each of the third transistor TR3 and the sixth transistor TR6 may include a drain that provides a second power supply voltage (e.g., a virtual power supply voltage VDD).

[0131] Fig.28A According to one or more embodiments, Fig.26 A cross-sectional view taken along line X15-X15', and Fig.28B According to one or more embodiments, Fig.26 A cross-sectional view taken along line X16-X16'.

[0132] Reference together Figures 26 to 28B , the backside wiring layer BM1 may include backside patterns 81a and 81b, each of which extends in the first direction X below the substrate SUB. The backside via BVA may be provided on the backside wiring layer BM1 and may include backside vias 82a and 82b. The backside contact BCA may be provided on the backside via BVA and may include, for example, backside contacts 83a and 83b on the backside via 82a that are spaced apart from each other in the second direction Y and a backside contact 83c on the backside via 82b. The contact CA may be placed above the active region RX1. The frontside wiring layer M1 may include frontside patterns 85a and 85b that each extend in the first direction X and are spaced apart from each other in the first direction X.

[0133] The back pattern 81b may receive a first power supply voltage, such as a global power supply voltage VDDG. The back through hole 82a may be disposed on the back pattern 81b and may extend in the second direction Y. The back contact 83a may be placed between the back through hole 82a and the source / drain region SD1 of the active region RX1, and the back contact 83b may be placed between the back through hole 82a and the source / drain region SD5 of the active region RX2. The source / drain region SD1 may be electrically connected to the back pattern 81b through the back contact 83a and the back through hole 82a, and may receive a first power supply voltage from the back pattern 81b. For example, the source of the first transistor TR1 may receive the global power supply voltage VDDG from the back pattern 81b.

[0134] The source / drain regions SD2 and SD3 may be electrically connected to the front pattern 84a through the contact CA and the via VA. Therefore, the source / drain regions SD2 and SD3 may be electrically connected to each other through the FSPDN. The source / drain region SD4 may be electrically connected to the back pattern 81a through the back contact 83c and the back via 82b. The drain of the third transistor TR3' may transmit a second power supply voltage (e.g., a virtual power supply voltage VDD) to the back pattern 81a.

[0135] Figures 29A to 29D is a diagram showing a device according to one or more embodiments. For example, Fig.29A A fin field-effect transistor (FinFET) 90a is shown. Fig.29B A gate-all-around field effect transistor (GAAFET) 90b is shown. Fig.29C A multi-bridge channel field effect transistor (MBCFET) 90c is shown, and Fig.29D A vertical field effect transistor (VFET) 90d is shown. For ease of illustration, Figures 29A to 29C shows a structure in which one of the two source / drain regions is removed, and Fig.29D A cross section of the VFET 90d cut along a plane parallel to another plane consisting of the second direction Y and the vertical direction Z and passing through the channel CH of the VFET 90d is shown.

[0136] refer to Fig.29A , the FinFET 90a may be formed of a fin-shaped active pattern extending in the first direction X between the STIs and a gate G extending in the second direction Y. The source / drain S / D may be formed on both sides of the gate G, and thus, the source and the drain (S / D) may be spaced apart from each other in the first direction X. An insulating layer may be formed between the channel CH and the gate G. According to one or more other embodiments, the FinFET 90a may be formed of a plurality of active patterns and the gate G spaced apart from each other in the second direction Y. For example, the FinFET 90a may be included in Figures 1 to 28B of integrated circuits 10 to 80. Included in Figures 1 to 28B The power gate switches in the integrated circuits 10 to 80 may be implemented by one or more of the FinFETs 90a.

[0137] refer to Fig.29B, the GAAFET 90b may be formed of an active pattern (ie, a nanowire), each of which extends in a first direction X and is spaced apart from each other in a vertical direction Z, and a gate G, which extends in a second direction Y. The source / drain S / D may be formed on both sides of the gate G, and thus, the source and drain S / D may be spaced apart from each other in the first direction X. An insulating layer may be formed between the channel CH and the gate G. The number of nanowires included in the GAAFET 90b is not limited to Fig.29B For example, GAAFET 90b may include Figures 1 to 28B of integrated circuits 10 to 80. Included in Figures 1 to 28B The power gate switches in the integrated circuits 10 to 80 may be implemented like the GAAFET 90b.

[0138] refer to Fig.29C , the MBCFET 90c may be formed of active patterns (i.e., nanosheets) each extending in the first direction X and spaced apart from each other in the vertical direction Z, and a gate G extending in the second direction Y. The source / drain S / D may be formed on both sides of the gate G, and thus, the source and drain S / D may be spaced apart from each other in the first direction X. An insulating layer may be formed between the channel CH and the gate G. The number of nanosheets included in the MBCFET 90c is not limited to Fig.29C For example, MBCFET 90c may include Figures 1 to 28B In the integrated circuit 10 to 80. For example, Figures 1 to 28B The power gate switches in the integrated circuits 10 to 80 may be implemented like the MBCFET 90c.

[0139] refer to Fig.29D , the VFET 90d may include a top source / drain T_SD and a bottom source / drain B_SD, the top source / drain T_SD and the bottom source / drain B_SD being spaced apart from each other in the vertical direction Z with a channel CH therebetween. The VFET 90d may include a gate G surrounding the circumference of the channel CH between the top source / drain T_SD and the bottom source / drain B_SD. An insulating layer may be formed between the channel CH and the gate G. For example, the VFET 90d may include Figures 1 to 28B of integrated circuits 10 to 80. Included in Figures 1 to 28B The power gate switches in the integrated circuits 10 to 80 may be implemented like the VFET 90d.

[0140] However, the transistor according to the above-described embodiment is not limited to the above-described structure. For example, the integrated circuit may include a forksheet FET having a structure in which a nanosheet for a P-type transistor and a nanosheet for an N-type transistor are separated from each other by a dielectric wall, so that the N-type transistor and the P-type transistor are closer to each other. The integrated circuit may include a bipolar junction transistor as well as a FET such as a complementary field effect transistor (CFET), a negative capacitance field effect transistor (NCFET), and a carbon nanotube (CNT) FET.

[0141] Fig.30 is a flow chart of a method of manufacturing an integrated circuit according to one or more embodiments. Fig.30 , the method according to the present embodiment is a method for manufacturing an integrated circuit IC including a standard cell, and may include a plurality of operations, namely, operation S10, operation S30, operation S50, operation S70, and operation S90. The cell library D12 (or standard cell library) may include information about the standard cell, for example, information about the function, characteristic, layout, etc. of the standard cell. According to some embodiments, the cell library D12 may define a tap cell and a dummy cell and a functional cell that generates an output signal from an input signal. According to some embodiments, the cell library D12 may define a memory cell and a dummy cell having the same footprint. The design rule D14 may include requirements that the layout of the integrated circuit IC needs to comply with. For example, the design rule D14 may include requirements for the space between patterns in the same layer, the minimum width of the pattern, the wiring direction of the wiring layer, etc. According to some embodiments, the design rule D14 may define the minimum spacing within the same trace of the wiring layer.

[0142] In operation S10, a logic synthesis operation may be performed to generate netlist data D13 from register transfer level (RTL) data D11. For example, a semiconductor design tool (e.g., a logic synthesis tool) may refer to a cell library D12 from RTL data D11 written in a hardware description language (HDL) such as VHSIC hardware description language (VHDL) and Verilog to perform logic synthesis, and may generate netlist data D13 including a bitstream or a netlist. The netlist data D13 may correspond to an input of placement and routing to be described later.

[0143] In operation S30, standard cells may be placed. For example, a semiconductor design tool (e.g., a placement and routing (P&R) tool) may place standard cells used by the netlist data D13 by referring to the cell library D12. According to some embodiments, the semiconductor design tool may place standard cells in a row extending along the X-axis direction or the Y-axis direction, and the placed standard cells may receive power from power rails extending along the boundary of the row.

[0144] In operation S50, the pins of the standard cell may be wired. For example, the semiconductor design tool may generate interconnections that electrically connect the output pins and input pins of the placed standard cell to each other, and may generate layout data D15 that defines the placed standard cell and the generated interconnections. The interconnections may include a pattern of vias and / or wiring layers in a via layer. The wiring layer may include a front wiring layer disposed above the front side of the substrate and a back wiring layer disposed on the back side of the substrate. The layout data D15 may have a format such as GDSII, and may include geometric information about the standard cell and geometric information about the interconnections. The semiconductor design tool may refer to the design rule D14 when wiring the pins of the standard cell. The layout data D15 may correspond to the output of placement and wiring. A separate operation S50 or operations S30 and S50 may be collectively referred to as a method for designing an integrated circuit.

[0145] Figures 1 to 28B The integrated circuits 10 to 80 may include a backside wiring layer BM disposed on the backside of the substrate, wherein the backside wiring layer BM may be directly connected to a power gate switch disposed on the front side of the substrate through a DBC including a backside via BVA and / or a backside contact BCA. Therefore, the wiring complexity of the frontside wiring layer disposed on the front side of the substrate may be reduced, and the IR drop between the backside wiring layer BM and the source / drain region may be reduced.

[0146] In operation S70, a mask may be manufactured. For example, optical proximity correction (OPC) for correcting distortion phenomena such as refraction due to characteristics of light in photolithography may be applied to the layout data D15. A pattern on the mask may be defined to form patterns to be arranged in a plurality of layers according to the data applied by the OPC, and at least one mask (or photomask) for forming corresponding patterns of the plurality of layers may be manufactured. According to one or more other embodiments, the layout of the integrated circuit IC may be limitedly modified in operation S70, and the limited modification of the integrated circuit IC in operation S70 is a post-processing for optimizing the structure of the integrated circuit IC, and may be referred to as design polishing.

[0147] In operation S90, an integrated circuit IC may be manufactured. For example, an integrated circuit IC may be manufactured by patterning a plurality of layers using at least one mask manufactured in operation S70. The front-end process (FEOL) may include, for example, operations of planarizing and cleaning the wafer, operations of forming a trench, operations of forming a well, operations of forming a gate line structure, and operations of forming a source and a drain. Various devices such as transistors, capacitors, resistors, etc. may be formed on a substrate by the FEOL. The back-end process (BEOL) may include, for example, operations of performing silicide of a gate, a source region, and a drain region, operations of adding a dielectric, operations of planarizing, operations of forming a hole, operations of adding a metal layer, operations of forming a through hole, and operations of forming a passivation layer. Various devices such as transistors, capacitors, resistors, etc. may be interconnected to each other by the BEOL. According to some embodiments, a middle-of-line process (MOL) may be performed between the FEOL and the BEOL, and contacts may be formed on various devices. Furthermore, a backside process may be performed on the backside of the substrate to form one or more of a backside wiring layer, a backside via, and a backside contact. Next, the integrated circuit IC may be packaged into a semiconductor package and may be used as a component part of various applications.

[0148] Fig.31 is a block diagram of a system on chip (SoC) 210 according to one or more embodiments. Fig.31 , SoC 210 may be referred to as an integrated circuit in which component parts of a computing system or other electronic system are integrated. For example, an application processor (AP) as an example of SoC 210 may include processors and components for other functions. SoC 210 may include a core 211, a digital signal processor (DSP) 212, a graphics processing unit (GPU) 213, an embedded memory 214, a communication interface (I / F) 215, and a memory I / F 216. The components of SoC 210 may communicate with each other via a bus 217.

[0149] The core 211 may process instructions and may control the operations of components included in the SoC 210. For example, the core 211 may drive an operating system by processing a series of instructions and execute an application on the operating system. The DSP 212 may generate useful data by processing a digital signal (e.g., a digital signal provided from the communication I / F 215). The GPU 213 may generate data for an image output through a display device from image data provided by the embedded memory 214 or the memory I / F 216, and may encode the image data. According to some embodiments, the integrated circuit described above with reference to the accompanying drawings may be included in the core 211, the DSP 212, the GPU 213, and / or the embedded memory 214.

[0150] The embedded memory 214 may store data required for the operation of the core 211, the DSP 212, and the GPU 213. The communication I / F 215 may provide an interface for a communication network or one-to-one communication. The memory I / F 216 may provide an interface for an external memory of the SoC 210, such as a dynamic random access memory (DRAM) or a flash memory.

[0151] Fig.32 is a block diagram of a computing system 220 including a memory for storing programs according to one or more embodiments. Fig.32 At least some operations (e.g., operations of the above-described flowchart) included in the method of designing an integrated circuit according to an embodiment may be performed in a computing system 220 (or a computer). The computing system 220 may include a processor 221, an input / output (I / O) device 222, a network interface 223, a random access memory (RAM) 224, a read-only memory (ROM) 225, and a storage device 226. The processor 221, the I / O device 222, the network interface 223, the RAM 224, the ROM 225, and the storage device 226 may be connected to a bus 227 and may communicate with each other via the bus 227.

[0152] The processor 221 may be referred to as a processing unit and may include at least one core capable of executing any instruction set (e.g., Intel Architecture-32 (IA-32), 64-bit extensions to IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, and IA-64), such as a microprocessor, AP, DSP, or GPU. For example, the processor 221 may access a memory, i.e., a RAM 224 or a ROM 225, via a bus 227 and may execute instructions stored in the RAM 224 or the ROM 225.

[0153] The RAM 224 may store a program 224_1 for a method of designing an integrated circuit or at least a portion of the program 224_1, and the program 224_1 may enable the processor 221 to perform at least some operations included in the method of designing an integrated circuit, for example, Fig.30 In other words, the program 224_1 may include a plurality of instructions executable by the processor 221, and the plurality of instructions included in the program 224_1 may enable the processor 221 to perform at least some of the operations included in the above-mentioned flowchart, for example.

[0154] The storage device 226 may not lose the stored data even when the power supplied to the computing system 220 is cut off. The storage device 226 may store the program 224_1, and before the processor 221 executes the program 224_1, the program 224_1 or at least a part thereof from the storage device 226 may be loaded into the RAM 224. Alternatively, the storage device 226 may store a file written in a programming language, and the program 224_1 or at least a part of the program 224_1 generated from the file by a compiler or the like may be loaded into the RAM 224. The storage device 226 may also store a database (DB) 226_1, and the DB 226_1 may include information required for designing an integrated circuit, for example, information about design blocks, Fig.30 Cell library D12 and / or Fig.30 Information on Design Rule D14.

[0155] The storage device 226 may store data to be processed by the processor 221 or data processed by the processor 221. In other words, according to the program 224_1, the processor 221 may generate data by processing the data stored in the memory 226, and may store the generated data in the storage device 226. For example, the storage device 226 may store Fig.30 RTL data D11, netlist data D13 and / or layout data D15.

[0156] I / O device 222 may include input devices (such as a keyboard or pointing device) and output devices (such as a printer or display). For example, through I / O device 222, a user may trigger processor 221 to execute program 224_1, and may input Fig.30 The RTL data D11 and / or netlist data D13 can be checked Fig.30 The layout data D15. The network interface 223 may provide access to a network external to the computing system 220. For example, the network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other type of links.

[0157] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit, comprising: a backside wiring layer on a backside of the substrate, the backside wiring layer comprising a first backside pattern and a second backside pattern isolated from each other; as well as a power gate switch on the front side of the substrate, the power gate switch connected to the first backside pattern and the second backside pattern, Wherein, the power gate switch comprises: a first source / drain region connected to the first backside pattern and configured to receive a first supply voltage from the first backside pattern; a gate line structure configured to receive a power gate signal; and A second source / drain region is connected to the second backside pattern and is configured to receive a power signal from the first source / drain region based on the power gate signal.

2. The integrated circuit according to claim 1, wherein: Based on the power gate signal being at an enable level, the second source / drain region of the power gate switch is configured to provide a second supply voltage to the second backside pattern based on the power signal.

3. The integrated circuit according to claim 2, wherein: The first supply voltage corresponds to a global supply voltage or an external supply voltage, and The second power supply voltage corresponds to a virtual power supply voltage or an internal power supply voltage.

4. The integrated circuit of claim 2, further comprising: a first backside contact on the first backside pattern; as well as a second backside contact on the second backside pattern, wherein the first source / drain region of the power gate switch is connected to the first backside pattern through the first backside contact, and The second source / drain region of the power gate switch is connected to the second back side pattern through the second back side contact.

5. The integrated circuit according to claim 4, wherein: The backside wiring layer further includes a third backside pattern isolated from the first backside pattern and the second backside pattern, wherein the first back side pattern and the third back side pattern are connected, and The first source / drain region of the power gate switch is configured to receive the first supply voltage from the third backside pattern.

6. The integrated circuit according to claim 4, wherein: The backside wiring layer further includes a third backside pattern spaced apart from the first backside pattern and the second backside pattern, wherein the second back side pattern is connected to the third back side pattern, and The integrated circuit further includes a third source / drain region, and the third source / drain region is configured to receive the second supply voltage through the third backside pattern.

7. The integrated circuit according to claim 2, further comprising a second backside wiring layer below the backside wiring layer in a vertical direction, in, The second backside wiring layer comprises: a first backside wiring connected to the first backside pattern and configured to receive the first power supply voltage; and A second backside wiring is connected to the second backside pattern and is configured to receive the second power supply voltage.

8. The integrated circuit of claim 4, wherein: The first backside contact passes through the substrate in a vertical direction and is connected to the first source / drain region of the power gate switch, and The second backside contact passes through the substrate in the vertical direction and is connected to the second source / drain region of the power gate switch.

9. The integrated circuit of claim 1, wherein: The power gate switch includes a plurality of transistors connected in parallel.

10. An integrated circuit comprising: a backside wiring layer on the backside of the substrate, the backside wiring layer including a first backside pattern and a second backside pattern, the first backside pattern and the second backside pattern each extending in a first direction and being isolated from each other in a second direction intersecting the first direction; contacts on the front side of the substrate, the contacts extending in the second direction; as well as a power gate switch on the front side of the substrate, the power gate switch connected to the first back side pattern and the second back side pattern, Wherein, the power gate switch comprises: a first source / drain region configured to receive a first supply voltage from the first backside pattern through the contact; a gate line structure configured to receive a power gate signal; and A second source / drain region is connected to the second backside pattern and is configured to receive a power signal from the first source / drain region based on the power gate signal.

11. The integrated circuit of claim 10, wherein: Based on the power gate signal being at an enable level, the second source / drain region is configured to provide a second power supply voltage to the second backside pattern based on the power signal.

12. The integrated circuit of claim 11, wherein: The first supply voltage corresponds to a global supply voltage or an external supply voltage, and The second power supply voltage corresponds to a virtual power supply voltage or an internal power supply voltage.

13. The integrated circuit of claim 11 , further comprising: a first backside contact on the first backside pattern; as well as a second backside contact on the second backside pattern, wherein the first source / drain region is connected to the first backside pattern through the first backside contact, and The second source / drain region is connected to the second back side pattern through the second back side contact.

14. The integrated circuit of claim 13, wherein: The backside wiring layer further includes a third backside pattern isolated from the second backside pattern, wherein the second back side pattern is connected to the third back side pattern, and The integrated circuit further includes a third source / drain region, and the third source / drain region is configured to receive the second supply voltage through the third backside pattern.

15. The integrated circuit of claim 13, wherein: The first backside contact passes through the substrate in a vertical direction, and The second backside contact passes through the substrate in the vertical direction and is connected to the second source / drain region.

16. An integrated circuit comprising: a backside wiring layer on a backside of the substrate, the backside wiring layer comprising a first backside pattern and a second backside pattern isolated from each other; a power gate switch on the front side of the substrate; a first backside via layer connected to the power gate switch and comprising a first backside via and a second backside via; as well as a second backside via layer between the backside wiring layer and the first backside via layer, the second backside via layer comprising a third backside via on the first backside pattern and a fourth backside via on the second backside pattern, wherein the first back side through hole is on the third back side through hole, and the second back side through hole is on the fourth back side through hole, and The power gate switch comprises: a first source / drain region configured to receive a first supply voltage from the first backside pattern through the third backside via and the first backside via; a gate line structure configured to receive a power gate signal; and A second source / drain region is connected to the second backside pattern through the fourth backside via and the second backside via and is configured to receive a power signal from the first source / drain region based on the power gate signal.

17. The integrated circuit of claim 16, wherein: Based on the power gate signal being at an enable level, the second source / drain region is configured to provide a second power supply voltage to the second backside pattern based on the power signal.

18. The integrated circuit of claim 17, wherein: The first supply voltage corresponds to a global supply voltage or an external supply voltage, and The second power supply voltage corresponds to a virtual power supply voltage or an internal power supply voltage.

19. The integrated circuit of claim 17, further comprising: a first backside contact on the first backside via; as well as a second back side contact on the second back side through hole, wherein the first source / drain region is connected to the first backside pattern through the first backside contact, the first backside via and the third backside via, and The second source / drain region is connected to the second back side pattern through the second back side contact, the second back side via and the fourth back side via.

20. The integrated circuit according to claim 19, in, The first backside contact passes through the substrate in a vertical direction, and The second backside contact passes through the substrate in the vertical direction.

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