Penetrating structure, image sensor and forming method of image sensor

Abstract

The embodiment of the invention relates to the field of image sensors, and provides a through structure, an image sensor and a forming method of the image sensor, the through structure at least comprises a first semiconductor and a second semiconductor, and the first semiconductor is located on the second semiconductor; the first semiconductor is provided with a first surface and a second surface which are oppositely arranged, and the first surface is positioned above the second surface; the through structure penetrates through the second surface from the first surface and enters the second semiconductor; the through structure comprises a central structure and a surrounding structure, the surrounding structure surrounds the central structure, and the bottom of the central structure penetrates through the second surface to enter the second semiconductor; the surrounding structure is formed by surrounding first parts and second parts which are alternately arranged, and at least the first parts are provided with steps.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of image sensors, and in particular to a penetration structure, an image sensor, and a method for forming the image sensor. Background Art

[0002] CMOS image sensor is the core component of modern image capture technology. It combines low-power logic circuits with high-quality pixel technology to convert external light signals into digital electrical signals. However, driven by the demand for high resolution and miniaturization, how to compress the size of CMOS image sensors and how to maintain the connection performance between various structures after the size is compressed have become technical problems that need to be solved urgently. Summary of the invention

[0003] The embodiments of the present disclosure provide a through structure, an image sensor, and a method for forming the image sensor, which are at least beneficial for reducing the size of the CMOS image sensor and maintaining the connection performance between the structures.

[0004] According to some embodiments of the present disclosure, the present disclosure provides a through structure, including:

[0005] Central structure;

[0006] Surrounding structures, the surrounding structures surround the central structure;

[0007] The surrounding structure is composed of first parts and second parts which are alternately arranged, and at least the first part has a step.

[0008] In some embodiments, the first part includes a first step structure and a second step structure, the first step structure surrounds part of the central structure, the second step structure surrounds the first step structure, the bottom surface of the central structure and the bottom surface of the first step structure have a first height difference along the vertical direction, the bottom surface of the first step structure and the bottom surface of the second step structure have a second height difference along the vertical direction, and the first height difference is greater than the second height difference.

[0009] In some embodiments, the bottom surface of the central structure is lower than the bottom surface of the first step structure, and the bottom surface of the first step structure is lower than the bottom surface of the second step structure.

[0010] In some embodiments, the second part has a step, and the second part includes a third step structure and a fourth step structure, the third step structure surrounds part of the central structure, the fourth step structure surrounds the third step structure, the bottom surface of the central structure and the bottom surface of the third step structure have a first height difference along the vertical direction, the bottom surface of the third step structure and the bottom surface of the fourth step structure have a second height difference along the vertical direction, and the first height difference is greater than the second height difference.

[0011] In some embodiments, the second portion has no step, and a bottom surface of the second portion is flush with a bottom surface of the central structure.

[0012] In some embodiments, the top surface of the surrounding structure is flush with the top surface of the central structure; and the through structure at least includes a conductive layer, a dielectric layer, and a filling layer.

[0013] Another aspect of the disclosed embodiment provides an image sensor, comprising: a first semiconductor and a second semiconductor, the first semiconductor being located on the second semiconductor;

[0014] The first semiconductor has a first surface and a second surface arranged opposite to each other, and the first surface is located above the second surface;

[0015] A through structure, the through structure passes from the first surface through the second surface into the second semiconductor;

[0016] The penetrating structure includes a central structure and a surrounding structure. The surrounding structure surrounds the central structure, and the bottom of the central structure passes through the second surface and enters the second semiconductor. The surrounding structure is composed of alternately arranged first and second parts, and at least the first part has a step.

[0017] In some embodiments, the first part includes a first step structure and a second step structure, the first step structure surrounds part of the central structure, the second step structure surrounds the first step structure, the bottom surface of the central structure and the bottom surface of the first step structure have a first height difference along a direction perpendicular to the first semiconductor, the bottom surface of the first step structure and the bottom surface of the second step structure have a second height difference along a direction perpendicular to the first semiconductor, and the first height difference is greater than the second height difference; the bottom surface of the central structure is lower than the bottom surface of the first step structure, and the bottom surface of the first step structure is lower than the bottom surface of the second step structure.

[0018] In some embodiments, the second part has a step, and the second part includes a third step structure and a fourth step structure, the third step structure surrounds part of the central structure, the fourth step structure surrounds the third step structure, the bottom surface of the central structure and the bottom surface of the third step structure have a first height difference along a direction perpendicular to the first semiconductor, the bottom surface of the third step structure and the bottom surface of the fourth step structure have a second height difference along a direction perpendicular to the first semiconductor, and the first height difference is greater than the second height difference; the bottom surface of the central structure is lower than the bottom surface of the third step structure, and the bottom surface of the third step structure is lower than the bottom surface of the fourth step structure.

[0019] In some embodiments, the second portion has no step, and a bottom surface of the second portion is flush with a bottom surface of the central structure.

[0020] In some embodiments, the top surface of the surrounding structure is flush with the top surface of the central structure; and the through structure at least includes a conductive layer, a dielectric layer, and a filling layer.

[0021] In some embodiments, the first semiconductor includes a first substrate and an epitaxial layer located on the first substrate; the second semiconductor includes a second substrate and a structural layer located on the second substrate, and a bonding layer is provided between the top surface of the structural layer and the bottom surface of the first substrate; the structural layer includes a structural conductive layer, and the through structure is electrically connected to the structural conductive layer.

[0022] In some embodiments, the first substrate includes an insulating layer, a metal layer, and a diffusion barrier layer stacked from top to bottom along a direction perpendicular to the first semiconductor, and the upper and lower metal layers are conductively connected through a contact structure; the metal layer includes at least a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer arranged in sequence from top to bottom, and the through structure is electrically connected to at least the third metal layer, the fourth metal layer, and the fifth metal layer.

[0023] In some embodiments, there is at least one first conductive structure between the fourth metal layer on a side close to the through-structure and the fifth metal layer; there is at least one second conductive structure between the third metal layer on a side close to the through-structure and the fourth metal layer; the first semiconductor also includes a transistor, the transistor has a source and a drain, and the source and the drain are electrically connected to the first metal layer.

[0024] In some embodiments, there is at least one first electrical connection structure between the first step structure and the structural conductive layer; there is at least one second electrical connection structure between the second step structure and the fifth metal layer; and the depth of the first electrical connection structure is greater than the depth of the second electrical connection structure.

[0025] In some embodiments, an isolation layer is provided on the epitaxial layer, and a first barrier layer is provided between the epitaxial layer and the first substrate. The first isolation structure is located on both sides of the penetrating structure and extends from the dielectric layer to the first barrier layer. A second barrier layer is provided on the structural conductive layer, and the central structure is electrically connected to the structural conductive layer through the second barrier layer.

[0026] In some embodiments, a metal grid structure is further provided on the first surface of the first semiconductor, and the metal grid structure is electrically connected to the through structure.

[0027] According to another aspect of the embodiments of the present disclosure, there is provided a method for forming an image sensor, comprising: providing a first semiconductor and a second semiconductor, wherein the first semiconductor is located on the second semiconductor;

[0028] The first semiconductor has a first surface and a second surface arranged opposite to each other, and the first surface is located above the second surface;

[0029] The first semiconductor includes a first substrate and an epitaxial layer located on the first substrate; the second semiconductor includes a second substrate and a structural layer located on the second substrate, the top surface of the structural layer is bonded to the bottom surface of the first substrate through a bonding layer; the structural layer includes a structural conductive layer;

[0030] The first substrate includes, from top to bottom, an insulating layer, a metal layer, and a diffusion barrier layer stacked in a direction perpendicular to the first semiconductor; the metal layer includes, from top to bottom, at least a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer sequentially arranged;

[0031] A through via is formed, which passes from the first surface through the second surface into the second semiconductor, and the through via at least exposes a portion of the structural conductive layer and a portion of the third metal layer, the fourth metal layer and the fifth metal layer.

[0032] In some embodiments, the through structure of any one of claims 1 to 6 is formed in a through via.

[0033] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: by merging the TSV (Through Silicon Via) and BSV (Back Side Via) in the peripheral area to form a through structure to compress the size of the CMOS image sensor, and the through structure includes a central structure and a surrounding structure, the surrounding structure surrounds the central structure, and the surrounding structure is composed of a first part and a second part that are alternately arranged, and at least the first part has a step, so that the contact area between the through structure and each metal layer is increased to improve the connection performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 is a schematic plan view of an image sensor device;

[0036] FIG. 2A to FIG. 2D It is a schematic diagram of a structure of the present disclosure, wherein Figure 2A and Figure 2B This is a top view of the penetrating structure. Figure 2C It is a cross-sectional view along the AA' direction. Figure 2D It is a cross-sectional view along the BB' direction;

[0037] FIG. 3A to FIG. 3D Another schematic diagram of the structure of the present invention is shown in FIG. Figure 3A and Figure 3B This is a top view of the penetrating structure. Figure 3C It is a cross-sectional view along the AA' direction. Figure 3D It is a cross-sectional view along the BB' direction;

[0038] FIG. 4A to FIG. 4C This is a schematic diagram of a through-structure material disclosed in the present invention, wherein Figure 4A It is a top view of the structure through the material. Figure 4B It is a cross-sectional view along CC' direction. Figure 4C It is a cross-sectional view along the DD' direction;

[0039] FIG. 5A to FIG. 5C This is a schematic diagram of a through-structure material disclosed in the present invention, wherein Figure 5A It is a top view of the structure through the material. Figure 5B It is a cross-sectional view along CC' direction. Figure 5C It is a cross-sectional view along the DD' direction;

[0040] FIG. 6A to FIG. 6C is a schematic diagram of an image sensor in an embodiment of the present disclosure, wherein Fig. 6A is a top view of the image sensor. Figure 6B It is a cross-sectional view along the EE' direction. Figure 6C It is a cross-sectional view along the FF' direction;

[0041] FIG. 7A to FIG. 7C Schematic diagram of an image sensor in another embodiment of the present disclosure, wherein Fig. 7A is a top view of the image sensor. Figure 7B It is a cross-sectional view along the EE' direction. Figure 7C It is a cross-sectional view along the FF' direction;

[0042] Figure 8 A schematic diagram of an image sensor in which a penetration structure is electrically connected to a metal mesh structure in an embodiment of the present disclosure;

[0043] Fig. 9A and Fig. 9B It is a top view schematic diagram of an image sensor in one embodiment of the present disclosure;

[0044] Fig. 10A and Fig. 10B It is a top view schematic diagram of an image sensor in another embodiment of the present disclosure;

[0045] FIG. 11A to FIG. 11C The figure is a schematic flow chart of a method for forming an image sensor in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] As can be seen from the background technology, CMOS image sensor is the core component of modern image capture technology. It combines low-power logic circuits with high-quality pixel technology and can convert external light signals into digital electrical signals. However, driven by the demand for high resolution and miniaturization, how to compress the size of CMOS image sensors and how to maintain the connection performance between various structures after the size is compressed have become technical problems that need to be solved urgently.

[0047] The present disclosure provides a through structure, an image sensor and a method for forming an image sensor. The through structure is formed by merging TSV (Through Silicon Via) and BSV (Back Side Via) in a peripheral area to compress the size of a CMOS image sensor. The through structure includes a central structure and a surrounding structure. The surrounding structure surrounds the central structure. The surrounding structure is composed of a first part and a second part that are alternately arranged. At least the first part has a step, so that the contact area between the through structure and each metal layer is increased to improve the connection performance.

[0048] The various embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The present disclosure is described in more detail by way of example with reference to the accompanying drawings in the following paragraphs. The advantages and features of the present disclosure will become clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0049] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0050] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0051] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0052] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0053] Figure 1 is a schematic plan view of an image sensor device;

[0054] FIG. 2A to FIG. 2D It is a schematic diagram of a structure of the present disclosure, wherein Figure 2A and Figure 2B This is a top view of the penetrating structure. Figure 2C It is a cross-sectional view along the AA' direction. Figure 2D It is a cross-sectional view along the BB' direction;

[0055] FIG. 3A to FIG. 3D Another schematic diagram of the structure of the present invention is shown in FIG. Figure 3A and Figure 3B This is a top view of the penetrating structure. Figure 3C It is a cross-sectional view along the AA' direction. Figure 3D It is a cross-sectional view along the BB' direction;

[0056] FIG. 4A to FIG. 4C This is a schematic diagram of a through-structure material disclosed in the present invention, wherein Figure 4A It is a top view of the structure through the material. Figure 4B It is a cross-sectional view along CC' direction. Figure 4C It is a cross-sectional view along the DD' direction;

[0057] FIG. 5A to FIG. 5C This is another schematic diagram of a through-structure material disclosed in the present invention, wherein Figure 5A It is a top view of the structure through the material. Figure 5B It is a cross-sectional view along CC' direction. Figure 5C It is a cross-sectional view along the DD' direction;

[0058] FIG. 6A to FIG. 6C is a schematic diagram of an image sensor in an embodiment of the present disclosure, wherein Fig. 6A is a top view of the image sensor. Figure 6B It is a cross-sectional view along the EE' direction. Figure 6C It is a cross-sectional view along the FF' direction;

[0059] FIG. 7A to FIG. 7C Schematic diagram of an image sensor in another embodiment of the present disclosure, wherein Fig. 7A is a top view of the image sensor. Figure 7B It is a cross-sectional view along the EE' direction. Figure 7C It is a cross-sectional view along the FF' direction;

[0060] Figure 8 A schematic diagram of an image sensor in which a penetration structure is electrically connected to a metal mesh structure in an embodiment of the present disclosure;

[0061] Fig. 9A and Fig. 9B It is a top view schematic diagram of an image sensor in one embodiment of the present disclosure;

[0062] Fig. 10A and Fig. 10B It is a top view schematic diagram of an image sensor in another embodiment of the present disclosure;

[0063] FIG. 11A to FIG. 11C The figure is a schematic flow chart of a method for forming an image sensor in one embodiment of the present disclosure.

[0064] Please refer to Figure 1 The image sensor device includes a pixel area A1 and a peripheral area A2, wherein the peripheral area A2 is located on at least one side of the pixel area A1. Figure 1It is shown in the figure that the peripheral area A2 is located around the pixel area A1. Of course, the peripheral area A2 can also be located on two sides or three sides of the pixel area A1, and can be set according to needs. The pixel area A1 is the core area of ​​the image sensor, which is mainly responsible for capturing light and converting light signals into electrical signals; the pixel area A1 mainly includes: photodiode, transfer transistor, reset transistor, source follower or amplification transistor, and row select transistor, etc. The peripheral area surrounds the pixel area and is mainly responsible for signal processing, control and interface functions; it mainly includes: readout circuitry, control circuitry, row / column driver circuits, timing and logic circuits, interface circuits, memory circuits, power management circuits, etc. In the peripheral area A2, there are usually TSV (Through Silicon Via) and BSV (Back Side Via) for signal connection and transmission. TSV and BSV will occupy a large area; however, with the demand for high resolution and miniaturization of CMOS image sensors, how to compress the size of CMOS image sensors and how to maintain the connection performance between various structures after the size is compressed have become technical problems that need to be solved urgently. In order to reduce the size of the CMOS image sensor in this application, TSV and BSV are combined to form a through structure.

[0065] FIG. 2A to FIG. 3D Two schematic diagrams of penetrating structures are provided for the embodiments of the present disclosure. A penetrating structure 100 includes: a central structure 10; a surrounding structure 20, wherein the surrounding structure 20 surrounds the central structure 10; the surrounding structure 20 is composed of a first part 201 and a second part 202 arranged alternately, and at least the first part 201 has a step 30'. FIG. 2A to FIG. 2D This is a schematic diagram of one of the through structures. FIG. 2A to FIG. 2D The first portion 201 of the through-structure 100 shown has a step 30 ′, and the second portion does not have a step 30 ′. FIG. 3A to FIG. 3D Another schematic diagram of the through structure is shown in FIG. FIG. 3A to FIG. 3DThe first portion 201 of the through-structure 100 shown has a step 30 ′, and the second portion also has a step 30 ′.

[0066] For details, please refer to FIG. 2A to FIG. 2D This is a schematic diagram of a through structure disclosed in the present invention, wherein Figure 2A and Figure 2B This is a top view of the penetrating structure. Figure 2C It is a cross-sectional view along the AA' direction. Figure 2D It is a cross-sectional view along the BB' direction. Figure 2A and Figure 2B The difference is that the number of the first part 201 and the second part 202 arranged alternately is different. Figure 2A The surrounding structure 20 is shown to be composed of four first parts 201 and four second parts 202. Figure 2B The surrounding structure 20 is shown to be composed of 8 first parts 201 and 8 second parts 202. The specific number of the first parts 201 and the second parts 202 can be set according to actual needs and is not limited here, but it should be noted that at least the number of the first parts 201 is not less than the number of the second parts 202. Since the first part 201 is provided with a step 30', the presence of the step 30' can increase the contact area between the penetration structure 100 and the subsequent structure, thereby improving the contact performance. The number of the first parts 201 is not less than the number of the second parts 202, so that there are more steps 30', so as to improve the contact performance.

[0067] like FIG. 2A to FIG. 2D As shown, a through structure 100 includes: a central structure 10; a surrounding structure 20, the surrounding structure 20 surrounds the central structure 10; the surrounding structure 20 is composed of a first part 201 and a second part 202 arranged alternately, the first part 201 has a step 30', and the second part 202 does not have a step 30'. The alternating arrangement mentioned here means that the first part 201 and the second part 202 are arranged along the surrounding direction. The first part 201 includes a first step structure 2011 and a second step structure 2012, the first step structure 2011 surrounds part of the central structure 10, and the second step structure 2012 surrounds the first step structure 2011, the bottom surface of the central structure 10 and the bottom surface of the first step structure 2011 have a first height difference H1 along the vertical direction, the bottom surface of the first step structure 2011 and the bottom surface of the second step structure 2012 have a second height difference H2 along the vertical direction, the first height difference H1 is greater than the second height difference H2, and the vertical placement mentioned here refers to the direction perpendicular to the upper surface of the through structure 100. The bottom surface of the central structure 10 is lower than the bottom surface of the first step structure 2011, and the bottom surface of the first step structure 2011 is lower than the bottom surface of the second step structure 2012. Figure 2CAs shown, the bottom surface of the central structure 10, the bottom surface of the first step structure 2011 and the bottom surface of the second step structure 2012 form a step-by-step ascending shape, the bottom surface of the central structure 10 is located at the bottom, the bottom surface of the second step structure 2012 is located at the top, and the bottom surface of the first step structure 2011 is located between the bottom surface of the central structure 10 and the bottom surface of the second step structure 2012. Figure 2D As shown, the second portion 202 does not have the step 30 ′, and the bottom surface of the second portion 202 is flush with the bottom surface of the central structure 10 . The top surface of the surrounding structure 20 is flush with the top surface of the central structure 10 .

[0068] For details, please refer to FIG. 3A to FIG. 3D This is another schematic diagram of the through structure disclosed in the present invention, wherein Figure 3A and Figure 3B This is a top view of the penetrating structure. Figure 3C It is a cross-sectional view along the AA' direction. Figure 3D It is a cross-sectional view along the BB' direction. Figure 2A and Figure 2B The difference is that the number of the first part 201 and the second part 202 arranged alternately is different. Figure 2A The surrounding structure 20 is shown to be composed of four first parts 201 and four second parts 202. Figure 2B It is shown that the surrounding structure 20 is composed of 8 first parts 201 and 8 second parts 202. The specific number of the first parts 201 and the second parts 202 can be set according to actual needs and is not limited here.

[0069] like FIG. 3A to FIG. 3DAs shown, a through structure 100 includes: a central structure 10; a surrounding structure 20, the surrounding structure 20 surrounds the central structure 10; the surrounding structure 20 is composed of a first part 201 and a second part 202 arranged alternately, the first part 201 has a step 30', and the second part 202 also has a step 30'. The alternating arrangement here means that the first part 201 and the second part 202 are arranged along the surrounding direction. The first part 201 includes a first step structure 2011 and a second step structure 2012, wherein the first step structure 2011 surrounds part of the central structure 10, and the second step structure 2012 surrounds the first step structure 2011; the second part 202 includes a third step structure 2021 and a fourth step structure 2022, wherein the third step structure 2021 surrounds part of the central structure 10, and the fourth step structure 2022 surrounds the third step structure 2021; a first height difference H1 is provided between the bottom surface of the central structure 10 and the bottom surface of the first step structure 2011 in a vertical direction, a second height difference H2 is provided between the bottom surface of the first step structure 2011 and the bottom surface of the second step structure 2012 in a vertical direction, and the first height difference H1 is greater than the second height difference H2; a first height difference H1 is provided between the bottom surface of the central structure 10 and the bottom surface of the third step structure 2021 in a vertical direction, and a second height difference H2 is provided between the bottom surface of the third step structure 2021 and the bottom surface of the fourth step structure 2022 in a vertical direction, and the first height difference H1 is greater than the second height difference H2. That is, the bottom surface of the first step structure 2011 is flush with the bottom surface of the third step structure 2021, the bottom surface of the second step structure 2012 is flush with the bottom surface of the fourth step structure 2022, the bottom surface of the central structure 10 is lower than the bottom surfaces of the first step structure 2011 and the third step structure 2021, and the bottom surfaces of the first step structure 2011 and the third step structure 2021 are lower than the bottom surfaces of the second step structure 2012 and the fourth step structure 2022; Figure 3C As shown, the bottom surface of the central structure 10, the bottom surface of the first step structure 2011 and the bottom surface of the second step structure 2012 form a step-by-step ascending step shape, as shown in FIG. Figure 3D As shown, the bottom surface of the central structure 10, the bottom surface of the third step structure 2021 and the bottom surface of the fourth step structure 2022 form a step-by-step ascending shape. The top surface of the surrounding structure 20 is flush with the top surface of the central structure 10.

[0070] FIG. 4A to FIG. 4C This is a schematic diagram of a through-structure material disclosed in the present invention, wherein Figure 4A It is a top view of the structure through the material. Figure 4B It is a cross-sectional view along CC' direction. Figure 4C It is a cross-sectional view along the DD' direction. FIG. 4A to FIG. 4CAs shown, the through structure 100 includes a central structure 10 and a surrounding structure 20, the surrounding structure 20 is arranged around the central structure 10, the surrounding structure 20 includes a first part 201 and a second part 202, the first part 201 has a step 30', the second part 202 does not have a step 30', the first part 201 includes a first step structure 2011 and a second step structure 2012; the through structure 100 is at least composed of a conductive layer 301, a dielectric layer 302 and a filling layer 303, the conductive layer 301 is located at the outermost side, the dielectric layer 302 covers the conductive layer 301, and the filling layer 303 fills the space surrounded by the dielectric layer 302. Figure 4B For along Figure 4A A cross-sectional view in the CC' direction is shown in the figure. As shown in the figure, the first step structure 2011 surrounds part of the central structure 10, and the second step structure 2012 surrounds the first step structure 2011. The bottom and side walls of the central structure 10 below the bottom surface of the first step structure 2011 have a conductive layer 301, the dielectric layer 302 covers the conductive layer 301, and the remaining part is filled with a filling layer; the bottom and side walls of the first step structure 2011 below the bottom surface of the second step structure 2012 have a conductive layer 301, the dielectric layer 302 covers the conductive layer 301, and the remaining part is filled with a filling layer 303; the bottom and side surfaces of the second step structure 2012 have a conductive layer 301, the dielectric layer 302 covers the conductive layer 301, and the remaining part is filled with a filling layer 303. Figure 4C For along Figure 4A A DD' direction cross-sectional view is shown in the figure. As shown in the figure, the second part 202 surrounds the central structure 10, the bottom of the central structure 10 has a conductive layer 301, the dielectric layer 302 covers the conductive layer 301, and the rest is filled with a filling layer; the bottom and side surfaces of the second part 202 have a conductive layer 301, the dielectric layer 302 covers the conductive layer 301, and the rest is filled with a filling layer.

[0071] FIG. 5A to FIG. 5C This is another schematic diagram of a through-structure material disclosed in the present invention, wherein Figure 5A It is a top view of the structure through the material. Figure 5B It is a cross-sectional view along CC' direction. Figure 5C It is a cross-sectional view along the DD' direction. FIG. 5A to FIG. 5CAs shown, the through structure 100 includes a central structure 10 and a surrounding structure 20. The surrounding structure 20 is arranged around the central structure 10. The surrounding structure 20 includes a first part 201 and a second part 202. The first part 201 has a step 30', and the second part 202 also has a step 30'; the first part 201 includes a first step structure 2011 and a second step structure 2012, and the second part 202 includes a third step structure 2021 and a fourth step structure 2022. The through structure 100 is composed of at least a conductive layer 301, a dielectric layer 302 and a filling layer 303. The conductive layer 301 is located at the outermost side, the dielectric layer 302 covers the conductive layer 301, and the filling layer 303 fills the space surrounded by the dielectric layer 302. Figure 5B For along Figure 5A A CC' direction cross-sectional view is shown in the figure. As shown in the figure, the first step structure 2011 surrounds part of the central structure 10, and the second step structure 2012 surrounds the first step structure 2011. The bottom and side walls of the central structure 10 below the bottom surface of the first step structure 2011 have a conductive layer 301, the dielectric layer 302 covers the conductive layer 301, and the remaining part is filled with a filling layer 303; the bottom and side walls of the first step structure 2011 below the bottom surface of the second step structure 2012 have a conductive layer 301, the dielectric layer 302 covers the conductive layer 301, and the remaining part is filled with a filling layer 303; the bottom and side surfaces of the second step structure 2012 have a conductive layer 301, the dielectric layer 302 covers the conductive layer 301, and the remaining part is filled with a filling layer 303. Figure 5C For along Figure 5A A DD' direction cross-sectional view is shown in the figure. As shown in the figure, the third step structure 2021 surrounds part of the central structure 10, and the fourth step structure 2022 surrounds the third step structure 2021. The bottom and side walls of the central structure 10 below the bottom surface of the third step structure 2021 have a conductive layer 301, the dielectric layer 302 covers the conductive layer 301, and the remaining part is filled with a filling layer 303; the bottom and side walls of the third step structure 2021 below the bottom surface of the fourth step structure 2022 have a conductive layer 301, the dielectric layer 302 covers the conductive layer 301, and the remaining part is filled with a filling layer 303; the bottom and side surfaces of the fourth step structure 2022 both have a conductive layer 301, the dielectric layer 302 covers the conductive layer 301, and the remaining part is filled with a filling layer 303.

[0072] 6A to 7CSchematic diagrams of two image sensors provided in the present disclosure, an image sensor 1000, including: a first semiconductor 1 and a second semiconductor 2, the first semiconductor 1 is located on the second semiconductor 2; the first semiconductor 1 has a first surface S1 and a second surface S2 arranged opposite to each other, the first surface S1 is located above the second surface S2; a penetrating structure 100, the penetrating structure 100 passes through the second surface S2 from the first surface S1 to enter the second semiconductor 2; the penetrating structure 100 includes a central structure 10 and a surrounding structure 20, the surrounding structure 20 surrounds the central structure 10, and the bottom of the central structure 10 passes through the second surface S2 to enter the second semiconductor 2; the surrounding structure 20 is composed of a first part 201 and a second part 202 arranged alternately, and at least the first part 201 has a step 30'. FIG. 6A to FIG. 6C The diagram shows an image sensor in which the first portion 201 has a step 30' and the second portion 202 does not have a step 30'; FIG. 7A to FIG. 7C The diagram shows an image sensor in which the first portion 201 has a step 30 ′ and the second portion 202 also has a step 30 ′.

[0073] For details, please refer to FIG. 6A to FIG. 6C , FIG. 6A to FIG. 6C is a schematic diagram of an image sensor in an embodiment of the present disclosure, wherein Fig. 6A is a top view of the image sensor. Figure 6B It is a cross-sectional view along the EE' direction. Figure 6C It is a cross-sectional view along the FF' direction; an image sensor 1000, comprising: a first semiconductor 1 and a second semiconductor 2, the first semiconductor 1 is located on the second semiconductor 2; the first semiconductor 1 has a first surface S1 and a second surface S2 arranged opposite to each other, the first surface S1 is located above the second surface S2; a penetrating structure 100, the penetrating structure 100 passes through the second surface S2 from the first surface S1 to enter the second semiconductor 2; the penetrating structure 100 comprises a central structure 10 and a surrounding structure 20, the surrounding structure 20 surrounds the central structure 10, and the bottom of the central structure 10 passes through the second surface S2 to enter the second semiconductor 2; the surrounding structure 20 is composed of a first part 201 and a second part 202 arranged alternately, the first part 201 has a step 30', and the second part 202 does not have a step 30'. Figure 6BAs shown, the first part 201 includes a first step structure 2011 and a second step structure 2012, the first step structure 2011 surrounds part of the central structure 10, the second step structure 2012 surrounds the first step structure 2011, the bottom surface of the central structure 10 and the bottom surface of the first step structure 2011 have a first height difference H1 along a direction perpendicular to the first semiconductor 1, the bottom surface of the first step structure 2011 and the bottom surface of the second step structure 2012 have a second height difference H2 along a direction perpendicular to the first semiconductor 1, and the first height difference H1 is greater than the second height difference H2; the bottom surface of the central structure 10 is lower than the bottom surface of the first step structure 2011, and the bottom surface of the first step structure 2011 is lower than the bottom surface of the second step structure 2012. Figure 6C As shown, the second part 202 does not have a step 30', and the bottom surface of the second part 202 is flush with the bottom surface of the central structure 10. The top surface of the surrounding structure 20 is flush with the top surface of the central structure 10; the through structure 100 at least includes a conductive layer 301, a dielectric layer 302 and a filling layer 303, the conductive layer 301 is located at the outermost side, the dielectric layer 302 covers the conductive layer 301, and the filling layer 303 fills the space surrounded by the dielectric layer 302. The material of the conductive layer 301 can be tungsten, the material of the dielectric layer 302 can be silicon nitride, silicon oxide or silicon oxynitride, and the material of the filling layer 303 can be silicon nitride, silicon oxide or silicon oxynitride, or can be a filter material such as a color filter.

[0074] like Figure 6B and 6CAs shown, the first semiconductor 1 includes a first substrate 1001 and an epitaxial layer 1002 located on the first substrate 1001; the second semiconductor 2 includes a second substrate 2001 and a structural layer 2002 located on the second substrate 2001, and a bonding layer 101 is provided between the top surface of the structural layer 2002 and the bottom surface of the first substrate 1001; the bonding method can be direct bonding or wafer bonding. The structural layer 2002 includes a structural conductive layer 2003, and the through structure 100 is electrically connected to the structural conductive layer 2003. The image sensor provided in the present application may be a backside illuminated image sensor (BSI-CIS: Backside Illuminated Complementary Metal-Oxide-Semiconductor Image Sensor); the first semiconductor 1 may be a pixel wafer (Pixel Wafer), which may be a wafer specifically used to manufacture a pixel array in an image sensor, on which a large number of pixel units are integrated, each pixel unit including a photodiode, a transfer transistor, a reset transistor, an amplifying transistor and other structures, for capturing light and converting it into an electrical signal; the first semiconductor 2 may be an application specific integrated circuit wafer (ASIC Wafer), on which peripheral circuits such as a readout circuit, a control circuit, a row / column driving circuit, a timing and logic circuit, an interface circuit, and a power management circuit are integrated, for processing the signal output by the pixel array, and realizing the readout, processing and transmission of the image. The pixel wafer and the ASIC wafer are combined by bonding technology to form a complete image sensor 1000. As can be seen from the above, the existing image sensor TSV and BSV will occupy a large area. With the demand for high resolution and miniaturization of CMOS image sensors, how to compress the size of CMOS image sensors has become a technical problem that needs to be solved urgently. In this application, in order to reduce the size of the CMOS image sensor, TSV and BSV are combined to form a through structure 100. The through structure 100 can realize the function of TSV to electrically connect the first semiconductor 1 and the second semiconductor 2, and can also realize the function of BSV to electrically connect the metal layer M.

[0075] The first substrate 1001 includes an insulating layer 1003, a metal layer M and a diffusion barrier layer 1004 stacked from top to bottom along a direction perpendicular to the first semiconductor 1, and the upper and lower metal layers M are connected through a contact structure 1005; the metal layer M includes at least a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4 and a fifth metal layer M5 arranged in sequence from top to bottom, and the through structure 100 is at least electrically connected to the third metal layer M3, the fourth metal layer M4 and the fifth metal layer M5. There is at least one first conductive structure C1 between the side of the fourth metal layer M4 close to the through structure 100 and the fifth metal layer M5; there is at least one second conductive structure C2 between the side of the third metal layer M3 close to the through structure 100 and the fourth metal layer M4. The material of the metal layer can be copper or tungsten, and the diffusion barrier layer 1004 is used to prevent the diffusion of the metal layer M. The first semiconductor further includes a transistor T, which has a source S, a drain D and a gate G, and the source S and the drain D are electrically connected to the first metal layer M1; it should be noted that the metal layers of the same layer may not be completely connected due to reasons such as wiring density, signal isolation and thermal management, such as Figure 6BAs shown, the source S and the drain D are both electrically connected to the first metal layer M1, but since the first metal layer M1 is not continuous, the source and the drain can transmit signals through the metal layer respectively; in order to achieve different wiring functions, the first metal layer M1 and the second metal layer M2 are not electrically connected to the through structure 100. There is at least one first electrical connection structure V1 between the first step structure 2011 and the structural conductive layer 2003; there is at least one second electrical connection structure V2 between the second step structure 2012 and the fifth metal layer M5; the depth of the first electrical connection structure V1 is H3, and the depth of the second electrical connection structure V2 is H4, and H3 is greater than H4. In a specific embodiment, the material of the first conductive structure C1, the second conductive structure C2, the first electrical connection structure V1, and the second electrical connection structure V2 can be the same as the material of the conductive layer 301, such as tungsten. The epitaxial layer 1002 also has an isolation layer 3, which may include a first isolation layer 3001 and a second isolation layer 3002, wherein the first isolation layer 3001 may be a high-K dielectric layer, and the second isolation layer 3002 may be an oxide layer, and the isolation layer 3 may reduce the dark current of the image sensor. A first barrier layer 1011 is also provided between the epitaxial layer 1002 and the first substrate 1001, and a first isolation structure 4 is located on both sides of the through structure 100 and extends from the dielectric layer 3 to the first barrier layer 1011; the first isolation structure 4 is used to isolate the through structure 100 in the epitaxial layer 1002 to prevent the isolation through structure 100 from affecting other structures in the epitaxial layer 1002. A second barrier layer 2011 is also provided on the structural conductive layer 2003, and the central structure 100 is electrically connected to the structural conductive layer 2003 through the second barrier layer 2011. In the process, the first barrier layer 1011 and the second barrier layer 2011 are both used as etching barrier layers to prevent over-etching from affecting other structures.

[0076] In order to reduce the size of the CMOS image sensor, in the embodiment of the present application, TSV and BSV are combined to form a through structure 100. The through structure 100 can realize the function of TSV to electrically connect the first semiconductor 1 and the second semiconductor 2, and can also realize the function of BSV to electrically connect the metal layer M. Replacing TSV and BSV with the through structure 100 can further compress the size of the CMOS image sensor. On the other hand, if the through-structure 100 is directly electrically connected to the metal layer M, there may be a problem of electrical abnormality due to failure to connect or poor connection performance. In order to solve this problem, the present application at least sets the first part 201 into a step shape to increase the contact area between the through-structure 100 and the fourth metal layer M4 and the fifth metal layer M5, thereby improving the contact performance. On the other hand, at least one first conductive structure C1 is formed between the side of the fourth metal layer M4 close to the through-structure 100 and the fifth metal layer M5, and at least one second conductive structure C2 is formed between the side of the third metal layer M3 close to the through-structure 100 and the fourth metal layer M4. The presence of C1 and C2 can increase the contact area between the through-structure 100 and M3 and M4 to a greater extent, thereby improving the contact performance between the through-structure 100 and the metal layer M. The problem of electrical abnormality due to failure to connect or poor connection performance between the through-structure 100 and the metal layer M can be solved by setting the step structure and the first conductive structure C1 and the second conductive structure C2. In addition, there may be a certain tensile stress in the through structure 100, which may cause the structural conductive layer 2003 connected thereto to warp. The warping of the structural conductive layer 2003 may cause the structural conductive layer 2003 and the structural layer 2002 to peel off. In order to prevent this situation from happening, the present application also sets at least one first electrical connection structure V1 between the first step structure 2011 and the structural conductive layer 2003, and sets at least one second electrical connection structure V2 between the second step structure 2012 and the fifth metal layer M5. The existence of the first electrical connection structure V1 and the second electrical connection structure V2 can release the stress generated during the formation of the through structure 100, prevent the structural conductive layer 2003 and the structural layer 2002 from peeling off, and improve the structural stability of the image sensor 1000.

[0077] FIG. 7A to FIG. 7C Schematic diagram of an image sensor in another embodiment of the present disclosure, wherein Fig. 7A is a top view of the image sensor 1000, Figure 7B It is a cross-sectional view along the EE' direction. Figure 7C The same parts as the previous embodiment are not described again. The difference between this embodiment and the previous embodiment is that the first part 201 has a step 30', and the second part 202 also has a step 30'. Figure 7B and Figure 7CAs shown, the penetration structure 100 includes a central structure 10 and a surrounding structure 20, the surrounding structure 20 is arranged around the central structure 10, and the surrounding structure 20 includes a first part 201 and a second part 202, the first part 201 has a step 30', and the second part 202 also has a step 30'; the first part 201 includes a first step structure 2011 and a second step structure 2012, and the second part 202 includes a third step structure 2021 and a fourth step structure 2022. The penetration structure 100 is composed of at least a conductive layer 301, a dielectric layer 302 and a filling layer 303, the conductive layer 301 is located at the outermost side, the dielectric layer 302 covers the conductive layer 301, and the filling layer 303 fills the space surrounded by the dielectric layer 302. In the embodiment of the present application, by setting steps in both the first part 201 and the second part 202, the contact area between the penetration structure 100 and the fourth metal layer M4 and the fifth metal layer M5 is larger, which further improves the contact performance, and improves the structural stability and yield of the image sensor 1000.

[0078] Figure 8 FIG. 1 is a schematic diagram of an image sensor in which a through structure and a metal grid structure are electrically connected in one embodiment of the present disclosure. Figure 8 As shown, a metal grid structure 5 is also provided on the first surface S1 of the first semiconductor 1. The metal grid structure 5 is electrically connected to the through structure 100. Specifically, the metal grid structure 5 is electrically connected to the conductive layer 301 of the through structure 100. The metal grid structure 5 is also covered with a dielectric layer 302. The metal grid structure 5 can be specifically a backside metal grid (BMG). The function of the BMG is to reduce the crosstalk when the light is incident from the back side of the first semiconductor 1, that is, the first surface S1, so as to improve the image quality. In addition to reducing the crosstalk and optimizing the optical path, the metal grid structure 5 can also be used as a part of the signal transmission path. In the embodiment of the present application, the metal grid structure 5 is electrically connected to the through structure 100, so that the signal of the image sensor 1000 can be transmitted from the back side S1 to the circuit layer of the front side S2, and then transmitted to the first semiconductor 2, so as to realize the electrical connection between the pixel unit and the peripheral circuit and then realize the analog-to-digital conversion.

[0079] Fig. 9A and Fig. 9B Schematic diagram of a top view of an image sensor in an embodiment of the present disclosure; Fig. 6AThe difference between the top view of the image sensor in FIG. 1 is that the first conductive structure C1, the second conductive structure C2, the first electrical connection structure V1, and the second electrical connection structure V2 are schematically indicated in the embodiment of the present application. Although the first conductive structure C1, the second conductive structure C2, the first electrical connection structure V1, and the second electrical connection structure V2 cannot be directly seen in the top view, in order to more clearly indicate the positions of the first conductive structure C1, the second conductive structure C2, the first electrical connection structure V1, and the second electrical connection structure V2, the embodiment of the present application schematically indicates them. Please refer to FIG. 6A to FIG. 6C as well as Fig. 9A and Fig. 9B , Fig. 9A and Fig. 9B The image sensor 1000 shown in the figure has a step 30' only in the first part 201, and has no step 30' in the second part 202. In the embodiment of the present application, only the first part 201 has a first conductive structure C1, a second conductive structure C2, a first electrical connection structure V1, and a second electrical connection structure V2. Fig. 9A and Fig. 9B As shown, there are two first conductive structures C1 between the side of the fourth metal layer M4 close to the through structure 100 and the fifth metal layer M5, and there are two second conductive structures C2 between the side of the third metal layer M3 close to the through structure 100 and the fourth metal layer M4. Of course, the number of the first conductive structures C1 and the second conductive structures C2 can be three or more, which is subject to actual needs. There are four first electrical connection structures V1 between the first step structure 2011 and the structural conductive layer 2003, and there are four second electrical connection structures V2 between the second step structure 2012 and the fifth metal layer M5. Of course, the number of the first electrical connection structures V1 and the second electrical connection structures V2 can be two, three, five or more, which is subject to actual needs. Fig. 9B and Fig. 9A The difference is, Fig. 9A The first conductive structure C1, the second conductive structure C2, the first electrical connection structure V1 and the second electrical connection structure V2 may be circular. Fig. 9B The first conductive structure C1, the second conductive structure C2, the first electrical connection structure V1 and the second electrical connection structure V2 can be rectangular, square or other polygonal shapes, and the number of the first conductive structure C1, the second conductive structure C2, the first electrical connection structure V1 and the second electrical connection structure V2 can be set according to needs and space.

[0080] Fig. 10A and Fig. 10B FIG. 1 is a top view schematic diagram of an image sensor in another embodiment of the present disclosure. Fig. 10A and Fig. 10B and Fig. 9A and Fig. 9BThe difference is that, in this embodiment, the first part 201 has a step 30', and the second part 202 also has a step 30'. In the embodiment of the present application, the first part 201 and the second part 202 both have a first conductive structure C1, a second conductive structure C2, a first electrical connection structure V1, and a second electrical connection structure V2. The shapes of the first conductive structure C1, the second conductive structure C2, the first electrical connection structure V1, and the second electrical connection structure V2 can be circular or rectangular, square, or other polygonal shapes, and the number of the first conductive structure C1, the second conductive structure C2, the first electrical connection structure V1, and the second electrical connection structure V2 can be set according to needs and space.

[0081] In order to reduce the size of the CMOS image sensor, in the embodiment of the present application, TSV and BSV are combined to form a through structure 100. The through structure 100 can realize the function of TSV to electrically connect the first semiconductor 1 and the second semiconductor 2, and can also realize the function of BSV to electrically connect the metal layer M. Replacing TSV and BSV with the through structure 100 can further compress the size of the CMOS image sensor. On the other hand, if the through-structure 100 is directly electrically connected to the metal layer M, there may be a problem of electrical abnormality due to failure to connect or poor connection performance. In order to solve this problem, the present application at least sets the first part 201 into a step shape to increase the contact area between the through-structure 100 and the fourth metal layer M4 and the fifth metal layer M5, thereby improving the contact performance. On the other hand, at least one first conductive structure C1 is formed between the side of the fourth metal layer M4 close to the through-structure 100 and the fifth metal layer M5, and at least one second conductive structure C2 is formed between the side of the third metal layer M3 close to the through-structure 100 and the fourth metal layer M4. The presence of C1 and C2 can increase the contact area between the through-structure 100 and M3 and M4 to a greater extent, thereby improving the contact performance between the through-structure 100 and the metal layer M. The problem of electrical abnormality due to failure to connect or poor connection performance between the through-structure 100 and the metal layer M can be solved by setting the step structure and the first conductive structure C1 and the second conductive structure C2. In addition, there may be a certain tensile stress in the through structure 100, which may cause the structural conductive layer 2003 connected thereto to warp. The warping of the structural conductive layer 2003 may cause the structural conductive layer 2003 and the structural layer 2002 to peel off. In order to prevent this situation from happening, the present application also sets at least one first electrical connection structure V1 between the first step structure 2011 and the structural conductive layer 2003, and sets at least one second electrical connection structure V2 between the second step structure 2012 and the fifth metal layer M5. The existence of the first electrical connection structure V1 and the second electrical connection structure V2 can release the stress generated during the formation of the through structure 100, prevent the structural conductive layer 2003 and the structural layer 2002 from peeling off, and improve the structural stability of the image sensor 1000.

[0082] FIG. 11A to FIG. 11C The figure is a schematic flow chart of a method for forming an image sensor in one embodiment of the present disclosure.

[0083] like FIG. 11A to FIG. 11C As shown, a method for forming an image sensor 1000 includes: providing a first semiconductor 1 and a second semiconductor 2, wherein the first semiconductor 1 is located on the second semiconductor 2; the first semiconductor 1 has a first surface S1 and a second surface S2 arranged opposite to each other, wherein the first surface S1 is located above the second surface S2; the first semiconductor 1 includes a first substrate 1001 and an epitaxial layer 1002 located on the first substrate 1001; the second semiconductor 2 includes a second substrate 2001 and a structural layer 2002 located on the second substrate 2001, wherein the top surface of the structural layer 2002 is aligned with the bottom surface of the first substrate 1001. The surface is bonded through a bonding layer 101; the structural layer 2002 includes a structural conductive layer 2003; the first substrate 1001 includes a stacked insulating layer 1003, a metal layer M and a diffusion barrier layer 1004 from top to bottom along a direction 1 perpendicular to the first semiconductor; the metal layer M includes at least a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4 and a fifth metal layer M5 arranged in sequence from top to bottom; the first metal layer M1, the second metal layer M2, the third metal layer M3, the fourth metal layer M4 and the fifth metal layer M5 have a step shape. The epitaxial layer 1002 also has an isolation layer 3, and the isolation layer 3 also has a photoresist layer 6, the photoresist layer 6 has an initial through hole K', and etching continues along the initial through hole K' to form Fig. 11B The through hole K shown in the figure, the through hole K passes through the second surface S2 from the first surface S1 into the second semiconductor 2, and the through hole K exposes at least part of the structural conductive layer 2003 and part of the third metal layer M3, the fourth metal layer M4 and the fifth metal layer M5. The through hole K also includes a first conductive hole C1', a second conductive hole C2', a first electrical connection hole V1' and a second electrical connection hole V2'. Fig. 11C , a conductive layer 301 , a dielectric layer 302 and a filling layer 303 are deposited in the through hole K to form the through structure 100 of the present application, and then a metal mesh structure 5 may be further formed to finally form the image sensor 1000 .

[0084] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A through structure, characterized in that: include: Central structure; a surrounding structure, the surrounding structure surrounding the central structure; The surrounding structure is composed of a first part and a second part which are alternately arranged, and at least the first part has a step.

2. The penetration structure according to claim 1, characterized in that: The first part includes a first step structure and a second step structure, the first step structure surrounds part of the central structure, the second step structure surrounds the first step structure, the bottom surface of the central structure and the bottom surface of the first step structure have a first height difference along the vertical direction, the bottom surface of the first step structure and the bottom surface of the second step structure have a second height difference along the vertical direction, and the first height difference is greater than the second height difference.

3. The penetration structure according to claim 2, characterized in that: The bottom surface of the central structure is lower than the bottom surface of the first step structure, and the bottom surface of the first step structure is lower than the bottom surface of the second step structure.

4. The penetration structure according to claim 1, characterized in that: The second part has a step, and the second part includes a third step structure and a fourth step structure, the third step structure surrounds part of the central structure, and the fourth step structure surrounds the third step structure, the bottom surface of the central structure and the bottom surface of the third step structure have a first height difference along the vertical direction, and the bottom surface of the third step structure and the bottom surface of the fourth step structure have a second height difference along the vertical direction, and the first height difference is greater than the second height difference.

5. The penetration structure according to claim 1, characterized in that: The second portion has no step, and a bottom surface of the second portion is flush with a bottom surface of the central structure.

6. The penetration structure according to claim 1, characterized in that: The top surface of the surrounding structure is flush with the top surface of the central structure; and the penetrating structure at least includes a conductive layer, a dielectric layer and a filling layer.

7. An image sensor, characterized in that: include: a first semiconductor and a second semiconductor, wherein the first semiconductor is located on the second semiconductor; The first semiconductor has a first surface and a second surface that are opposite to each other, and the first surface is located above the second surface; a penetrating structure, the penetrating structure passing from the first surface through the second surface into the second semiconductor; The penetrating structure includes a central structure and a surrounding structure, wherein the surrounding structure surrounds the central structure, and the bottom of the central structure passes through the second surface and enters the second semiconductor; the surrounding structure is composed of a first part and a second part that are alternately arranged, and at least the first part has a step.

8. The image sensor according to claim 7, characterized in that: The first part includes a first step structure and a second step structure, the first step structure surrounds part of the central structure, the second step structure surrounds the first step structure, the bottom surface of the central structure and the bottom surface of the first step structure have a first height difference along a direction perpendicular to the first semiconductor, the bottom surface of the first step structure and the bottom surface of the second step structure have a second height difference along a direction perpendicular to the first semiconductor, and the first height difference is greater than the second height difference; the bottom surface of the central structure is lower than the bottom surface of the first step structure, and the bottom surface of the first step structure is lower than the bottom surface of the second step structure.

9. The image sensor according to claim 7, characterized in that: The second part has a step, and the second part includes a third step structure and a fourth step structure, the third step structure surrounds part of the central structure, and the fourth step structure surrounds the third step structure, the bottom surface of the central structure and the bottom surface of the third step structure have a first height difference along a direction perpendicular to the first semiconductor, the bottom surface of the third step structure and the bottom surface of the fourth step structure have a second height difference along a direction perpendicular to the first semiconductor, and the first height difference is greater than the second height difference; the bottom surface of the central structure is lower than the bottom surface of the third step structure, and the bottom surface of the third step structure is lower than the bottom surface of the fourth step structure.

10. The image sensor according to claim 7, characterized in that: The second portion has no step, and a bottom surface of the second portion is flush with a bottom surface of the central structure.

11. The image sensor according to claim 7, characterized in that: The top surface of the surrounding structure is flush with the top surface of the central structure; and the penetrating structure at least includes a conductive layer, a dielectric layer and a filling layer.

12. The image sensor according to claim 8, characterized in that The first semiconductor includes a first substrate and an epitaxial layer located on the first substrate; the second semiconductor includes a second substrate and a structural layer located on the second substrate, and a bonding layer is provided between the top surface of the structural layer and the bottom surface of the first substrate; the structural layer includes a structural conductive layer, and the through structure is electrically connected to the structural conductive layer.

13. The image sensor according to claim 12, characterized in that: The first substrate includes, from top to bottom, a stacked insulating layer, a metal layer, and a diffusion barrier layer along a direction perpendicular to the first semiconductor, and the upper and lower metal layers are conductively connected via a contact structure; the metal layers include, from top to bottom, at least a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer arranged in sequence, and the through structure is electrically connected to at least the third metal layer, the fourth metal layer, and the fifth metal layer.

14. The image sensor according to claim 13, characterized in that: There is at least one first conductive structure between the fourth metal layer and the fifth metal layer on one side close to the through structure; there is at least one second conductive structure between the third metal layer and the fourth metal layer on one side close to the through structure; the first semiconductor also includes a transistor, the transistor has a source and a drain, and the source and the drain are electrically connected to the first metal layer.

15. The image sensor according to claim 12, characterized in that: There is at least one first electrical connection structure between the first step structure and the structural conductive layer; there is at least one second electrical connection structure between the second step structure and the fifth metal layer; the depth of the first electrical connection structure is greater than the depth of the second electrical connection structure.

16. The image sensor according to claim 12, characterized in that: An isolation layer is also provided on the epitaxial layer, and a first barrier layer is also provided between the epitaxial layer and the first substrate. A first isolation structure is located on both sides of the through structure and extends from the dielectric layer to the first barrier layer. A second barrier layer is also provided on the structural conductive layer, and the central structure is electrically connected to the structural conductive layer through the second barrier layer.

17. The image sensor according to any one of claims 7 to 16, characterized in that: A metal grid structure is also provided on the first surface of the first semiconductor, and the metal grid structure is electrically connected to the through structure.

18. A method for forming an image sensor, characterized in that: include: Providing a first semiconductor and a second semiconductor, wherein the first semiconductor is located on the second semiconductor; The first semiconductor has a first surface and a second surface that are opposite to each other, and the first surface is located above the second surface; The first semiconductor includes a first substrate and an epitaxial layer located on the first substrate; the second semiconductor includes a second substrate and a structural layer located on the second substrate, the top surface of the structural layer is bonded to the bottom surface of the first substrate via a bonding layer; the structural layer includes a structural conductive layer; The first substrate includes, from top to bottom, an insulating layer, a metal layer, and a diffusion barrier layer stacked in a direction perpendicular to the first semiconductor; the metal layer includes, from top to bottom, at least a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer sequentially arranged; A through via is formed, the through via passing from the first surface through the second surface into the second semiconductor, the through via exposing at least a portion of the structural conductive layer and a portion of the third metal layer, the fourth metal layer and the fifth metal layer.

19. The method for forming an image sensor according to claim 18, wherein: The through structure according to any one of claims 1 to 6 is formed in the through hole.

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