Display device and manufacturing method thereof

Abstract

The invention relates to a display device and a manufacturing method thereof. According to one embodiment, a display device includes: an insulating layer; a lower electrode disposed above the insulating layer; a rib layer having a pixel opening overlapping the lower electrode; a partition wall including a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion; an organic layer that covers the lower electrode through the pixel opening and emits light in response to application of a voltage; and an upper electrode covering the organic layer. In addition, the lower electrode includes: a reflective layer that reflects light emitted from the organic layer; and a metal layer disposed between the reflective layer and the insulating layer, the metal layer having an end portion protruding from the reflective layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-147026 filed on September 11, 2023, and cites all the contents described in the Japanese patent application. Technical Field

[0003] Embodiments of the present invention relate to a display device and a method for manufacturing the same. Background Art

[0004] In recent years, display devices using organic light emitting diodes (OLEDs) as display elements have been put into practical use. In such display devices, a technology capable of improving the yield is required. Summary of the invention

[0005] In general, according to an embodiment, a display device includes: an insulating layer; a lower electrode disposed above the insulating layer; a rib layer having a pixel opening overlapping the lower electrode; a partition wall including a lower portion disposed above the rib layer and an upper portion having an end protruding from a side surface of the lower portion; an organic layer covering the lower electrode through the pixel opening and emitting light in response to application of a voltage; and an upper electrode covering the organic layer. In addition, the lower electrode includes: a reflective layer reflecting light emitted by the organic layer; and a metal layer disposed between the reflective layer and the insulating layer and having an end protruding from the reflective layer.

[0006] In addition, according to an embodiment, a method for manufacturing a display device includes: forming an insulating layer, forming a lower electrode above the insulating layer, the lower electrode including a reflective layer that reflects light emitted by the organic layer, and a metal layer that is arranged between the reflective layer and the insulating layer and has an end protruding from the reflective layer, forming a rib layer covering the lower electrode, forming a partition wall, the partition wall including a lower portion arranged above the rib layer, and an upper portion having an end protruding from a side surface of the lower portion, before or after the formation of the partition wall, forming a pixel opening in the rib layer, forming an organic layer, the organic layer covers the lower electrode through the pixel opening and emits light in response to the application of a voltage, and forming an upper electrode covering the organic layer.

[0007] According to the embodiment, the yield of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a diagram showing a configuration example of a display device according to the first embodiment.

[0009] Figure 2 This is a schematic plan view showing an example of the layout of sub-pixels according to the first embodiment.

[0010] Figure 3 It is along Figure 2 Schematic cross-sectional view of the display device taken along line III-III.

[0011] Figure 4 This is a diagram showing an example of a layer structure that can be applied to an organic layer.

[0012] Figure 5 It is a schematic enlarged cross-sectional view of the organic insulating layer, rib layer, partition wall, and lower electrode according to the first embodiment.

[0013] Figure 6 It is a schematic cross-sectional view showing the manufacturing process of the display device according to the first embodiment.

[0014] Figure 7 It means next Figure 6 A schematic cross-sectional view of the process.

[0015] Figure 8 It means next Figure 7 A schematic cross-sectional view of the process.

[0016] Fig. 9 It means next Figure 8 A schematic cross-sectional view of the process.

[0017] Fig.10 It means next Fig. 9 A schematic cross-sectional view of the process.

[0018] Fig.11 It means next Fig.10 A schematic cross-sectional view of the process.

[0019] Fig.12 It means next Fig.11 A schematic cross-sectional view of the process.

[0020] Fig.13 It means next Fig.12 A schematic cross-sectional view of the process.

[0021] Fig.14 It means next Fig.13 A schematic cross-sectional view of the process.

[0022] Fig.15 It means next Fig.14 A schematic cross-sectional view of the process.

[0023] Fig.16 It means next Fig.15 A schematic cross-sectional view of the process.

[0024] Fig.17 It means next Fig.16 A schematic cross-sectional view of the process.

[0025] Fig.18 It means next Fig.17 A schematic cross-sectional view of the process.

[0026] Fig.19 It means next Fig.18 A schematic cross-sectional view of the process.

[0027] Fig. 20 It means next Fig.19 A schematic cross-sectional view of the process.

[0028] Fig.21 This is a diagram for explaining an example of the effects achieved by the first embodiment.

[0029] Fig. 22 It is a schematic plan view showing an example of the layout of sub-pixels according to the second embodiment.

[0030] Fig.23 It is along Fig. 22 A schematic cross-sectional view of the display device taken along line XXIII-XXIII in FIG.

[0031] Fig.24 It is a schematic cross-sectional view of the structure of a comparative example.

[0032] Fig.25 This is a schematic cross-sectional view of the structure of another comparative example. DETAILED DESCRIPTION

[0033] Several embodiments will be described with reference to the drawings.

[0034] The disclosed content is only an example, and appropriate changes that can be easily thought of by those skilled in the art while maintaining the main idea of ​​the invention are of course included in the scope of the present invention. In addition, with respect to the drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically shown compared with the actual method, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, for the constituent elements that have the same or similar functions as the constituent elements described in the drawings that have appeared, the same reference numerals are marked, and sometimes repeated detailed descriptions are appropriately omitted.

[0035] It should be noted that, for ease of understanding, mutually orthogonal X-axis, Y-axis and Z-axis are recorded in the drawings as needed. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of the plane including the X-direction and the Y-direction. In addition, the situation of observing various elements parallel to the Z-direction is called top-down observation.

[0036] The display device of each embodiment is an organic electroluminescent display device having an organic light emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, vehicle-mounted equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0037] [First embodiment]

[0038] Figure 1 1 is a diagram showing a configuration example of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 includes a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be glass or a flexible resin film.

[0039] In the present embodiment, the shape of the substrate 10 in a plan view is a rectangle, however, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0040] The display area DA includes a plurality of pixels PX arranged in a matrix in the X direction and the Y direction. The pixel PX includes a plurality of sub-pixels SP that display different colors. In the present embodiment, it is assumed that the pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. However, the pixel PX may also include a sub-pixel SP of another color such as white together with the sub-pixels SP1, SP2, and SP3 or instead of any of the sub-pixels SP1, SP2, and SP3.

[0041] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0042] In the display area DA, a plurality of scanning lines GL for supplying scanning signals to the pixel circuits 1 of the sub-pixels SP, a plurality of signal lines SL for supplying video signals to the pixel circuits 1 of the sub-pixels SP, and a plurality of power supply lines PL are arranged. Figure 1 In the example of FIG. 5 , the scanning lines GL and the power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0043] The gate electrode of the pixel switch 2 is connected to the scanning line GL. The source electrode of the pixel switch 2 is connected to the signal line SL. The drain electrode of the pixel switch 2 is connected to the gate electrode of the driving transistor 3 and the capacitor 4. The source electrode of the driving transistor 3 is connected to the power line PL and the capacitor 4. The drain electrode of the driving transistor 3 is connected to the display element DE.

[0044] It should be noted that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0045] Figure 2 1 is a schematic top view showing an example of the layout of sub-pixels SP1, SP2, and SP3. Figure 2 In the example of FIG. 1 , the sub-pixels SP2 and SP3 are arranged in the X direction with the sub-pixel SP1. In addition, the sub-pixel SP2 and the sub-pixel SP3 are arranged in the Y direction.

[0046] When the sub-pixels SP1, SP2, and SP3 are arranged in this manner, columns in which the sub-pixels SP2 and SP3 are alternately arranged in the Y direction and columns in which a plurality of sub-pixels SP1 are repeatedly arranged in the Y direction are formed in the display area DA. These columns are alternately arranged in the X direction. It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 Example.

[0047] The rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. Figure 2 In the example, the pixel opening AP1 is larger than the pixel opening AP2, and the pixel opening AP2 is larger than the pixel opening AP3. That is, among the sub-pixels SP1, SP2, and SP3, the sub-pixel SP1 has the largest opening ratio, and the sub-pixel SP3 has the smallest opening ratio. It should be noted that the sizes of the pixel openings AP1, AP2, and AP3 are not limited to this example. For example, at least two of the pixel openings AP1, AP2, and AP3 may have the same size.

[0048] The sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 respectively overlapping with the pixel opening AP1. The sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 respectively overlapping with the pixel opening AP2. The sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 respectively overlapping with the pixel opening AP3.

[0049] The lower electrode LE1, the upper electrode UE1, and the portion of the organic layer OR1 that overlaps with the pixel opening AP1 constitute the display element DE1 of the sub-pixel SP1. The lower electrode LE2, the upper electrode UE2, and the portion of the organic layer OR2 that overlaps with the pixel opening AP2 constitute the display element DE2 of the sub-pixel SP2. The lower electrode LE3, the upper electrode UE3, and the portion of the organic layer OR3 that overlaps with the pixel opening AP3 constitute the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cover layer described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0050] The partition wall 6 is disposed in the display area DA. The partition wall 6 is located above the rib layer 5 and overlaps with the rib layer 5 as a whole. Figure 2 In the example of FIG. 1 , the partition wall 6 has the same planar shape as the rib layer 5. That is, the partition wall 6 has openings in the sub-pixels SP1, SP2, and SP3, respectively. From another point of view, the rib layer 5 and the partition wall 6 are lattice-shaped when viewed from above, and surround each of the display elements DE1, DE2, and DE3. The partition wall 6 has a function as a wiring for supplying a common voltage to the upper electrodes UE1, UE2, and UE3.

[0051] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP along line III-III in FIG. A circuit layer 11 is arranged on the substrate 10. The circuit layer 11 includes Figure 1 The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that planarizes the unevenness generated in the circuit layer 11.

[0052] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Figure 3 The cross section of FIG. 1 is not shown, but the lower electrodes LE1, LE2, and LE3 are connected to the pixel circuit 1 ( 10 ) of the circuit layer 11 through contact holes provided in the organic insulating layer 12. Figure 1 The drain electrode of the driving transistor 3 shown is connected.

[0053] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. Thus, both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called a cantilever shape.

[0054] exist Figure 3 In the example of FIG. 5 , the lower portion 61 has a bottom layer 63 and a shaft layer 64. The bottom layer 63 is located between the shaft layer 64 and the rib layer 5. Figure 3 In the example of FIG. 6 , the upper portion 62 includes a first top layer 65 and a second top layer 66 . The first top layer 65 is disposed on the shaft layer 64 . The second top layer 66 is disposed on the first top layer 65 .

[0055] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and is opposite to the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and is opposite to the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and is opposite to the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side of the lower portion 61 of the partition wall 6.

[0056] The display element DE1 includes a cover layer CP1 covering the upper electrode UE1. The display element DE2 includes a cover layer CP2 covering the upper electrode UE2. The display element DE3 includes a cover layer CP3 covering the upper electrode UE3. The cover layers CP1, CP2, and CP3 respectively have the function of serving as optical adjustment layers to improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3.

[0057] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is referred to as the stacked film FL3.

[0058] A portion of the laminate film FL1 is located above the upper portion 62. This portion is separated from the portion of the laminate film FL1 located around the partition wall 6 (the portion constituting the display element DE1). Similarly, a portion of the laminate film FL2 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL2 located around the partition wall 6 (the portion constituting the display element DE2). In addition, a portion of the laminate film FL3 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL3 located around the partition wall 6 (the portion constituting the display element DE3).

[0059] Seal layers SE11, SE12, and SE13 covering the laminate films FL1, FL2, and FL3, respectively, are provided in the sub-pixels SP1, SP2, and SP3. Specifically, the seal layer SE11 continuously covers the cap layer CP1 and the partition wall 6 around the sub-pixel SP1. The seal layer SE12 continuously covers the cap layer CP2 and the partition wall 6 around the sub-pixel SP2. The seal layer SE13 continuously covers the cap layer CP3 and the partition wall 6 around the sub-pixel SP3.

[0060] exist Figure 3In the example, the laminated film FL1 and the sealing layer SE11 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE12 on the partition wall 6. In addition, the laminated film FL1 and the sealing layer SE11 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition wall 6.

[0061] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are continuously provided at least in the entire display area DA, and a part of them also reaches the peripheral area SA.

[0062] A cover member such as a polarizing plate, a protective film or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0063] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx) or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of resin materials (organic insulating materials) such as epoxy resin and acrylic resin.

[0064] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), etc. For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0065] Figure 4 : is a diagram showing an example of a layer structure that can be applied to the organic layers OR1, OR2, and OR3. The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including a light-emitting layer EML. In the present embodiment, it is assumed that the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL are sequentially stacked in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures such as a so-called series structure including a plurality of light-emitting layers EML.

[0066] The cover layers CP1, CP2, and CP3, for example, have a stacked structure formed by overlapping multiple transparent layers. These transparent layers may include layers formed by inorganic materials and layers formed by organic materials. In addition, these transparent layers have different refractive indices from each other. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the refractive indices of the sealing layers SE11, SE12, and SE13. It should be noted that at least one of the cover layers CP1, CP2, and CP3 may also be omitted.

[0067] A common voltage is supplied to the partition wall 6. The common voltage is supplied to the upper electrodes UE1, UE2, UE3 in contact with the lower portion 61. The lower electrodes LE1, LE2, LE3 are supplied with pixel voltages corresponding to the video signals of the signal lines SL through the pixel circuits 1 of the sub-pixels SP1, SP2, SP3.

[0068] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, if a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EML of the organic layer OR1 emits light in a blue wavelength region. If a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EML of the organic layer OR2 emits light in a green wavelength region. If a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EML of the organic layer OR3 emits light in a red wavelength region.

[0069] As another example, the light-emitting layers EML of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layer EML into light of a color corresponding to the sub-pixels SP1, SP2, and SP3. In addition, the display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layer EML to generate light of a color corresponding to the sub-pixels SP1, SP2, and SP3.

[0070] Figure 5 1 is a schematic enlarged cross-sectional view of the organic insulating layer 12, the rib layer 5, the partition wall 6, and the lower electrodes LE1 and LE2. Figure 5 In the example of , the bottom layer 63 protrudes from the side of the shaft layer 64. In addition, the width of the second top layer 66 is smaller than the width of the first top layer 65. Thus, the upper surface near both ends of the first top layer 65 is exposed from the second top layer 66. The shaft layer 64 is formed to be thicker than the bottom layer 63, the first top layer 65, and the second top layer 66.

[0071] The bottom layer 63 and the shaft layer 64 are formed of, for example, a metal material. As the metal material of the bottom layer 63, for example, molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW) or molybdenum-niobium alloy (MoNb) can be used. As the metal material of the shaft layer 64, for example, aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY) or aluminum-silicon alloy (AlSi) can be used. It should be noted that at least one of the bottom layer 63 and the shaft layer 64 may have a stacked structure of multiple layers. In addition, the shaft layer 64 may also include a layer formed of an insulating material. In addition, the lower portion 61 may have a single-layer structure formed of a conductive material.

[0072] For example, the first top layer 65 is formed of a metal material, and the second top layer 66 is formed of a transparent conductive oxide. As the metal material of the first top layer 65, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy can be used. As the conductive oxide of the second top layer 66, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide) can be used. It should be noted that the upper portion 62 may have a single-layer structure formed of a specific material. In addition, the upper portion 62 may include a layer formed of an insulating material.

[0073] The lower electrode LE1 has an end portion E1. Figure 2 As shown in FIG. 1 , the end portion E1 overlaps the partition wall 6 (lower portion 61 ) over the entire circumference of the lower electrode LE1 in a plan view. Figure 5 As shown, the end E1 is located below the shaft layer 64. The end E2 of the lower electrode LE2 and the end E3 of the lower electrode LE3 are also located below the shaft layer 64 over the entire circumference of the lower electrodes LE2 and LE3, respectively. However, each of the end E1, E2, and E3 may have a portion that does not overlap with the shaft layer 64 when viewed from above.

[0074] like Figure 5 As shown in FIG. 1 , a step portion ST is generated on the upper surface of the rib layer 5 due to the end portions E1 and E2 of the lower electrodes LE1 and LE2. Figure 5 Although not shown in the cross section, a step portion ST caused by the end E3 of the lower electrode LE3 is also generated on the upper surface of the rib layer 5. In the present embodiment, these step portions ST are covered by the bottom layer 63 and the shaft layer 64. The upper surfaces of the shaft layer 64, the first top layer 65, and the second top layer 66 can also be deformed corresponding to the step portions ST.

[0075] like Figure 5As shown in the enlarged view in FIG. 1 , the lower electrode LE1 includes a reflective layer RL and a metal layer ML. The reflective layer RL reflects light emitted by the organic layer OR1 in the Z direction. The metal layer ML is disposed between the reflective layer RL and the organic insulating layer 12 .

[0076] The lower electrode LE1 further includes a first covering layer V1 and a second covering layer V2. The first covering layer V1 covers the lower surface of the reflective layer RL opposite to the metal layer ML. The second covering layer V2 covers the upper surface of the reflective layer RL. The first covering layer V1 improves the adhesion between the reflective layer RL and the metal layer ML. The second covering layer V2 protects the reflective layer RL from various etching effects when manufacturing the display device DSP.

[0077] The reflective layer RL may be formed of a metal material having excellent light reflectivity such as silver. Each of the coating layers V1 and V2 may be formed of a transparent conductive oxide such as ITO, IZO or IGZO. The metal layer ML may be formed of titanium, titanium nitride, tungsten or a molybdenum-tungsten alloy.

[0078] exist Figure 5 In the example of , the metal layer ML, the first coating layer V1, and the second coating layer V2 are all thinner than the reflective layer RL. In addition, the first coating layer V1 is thinner than the metal layer ML and the second coating layer V2. However, the relationship between the thicknesses of the reflective layer RL, the metal layer ML, the first coating layer V1, and the second coating layer V2 is not limited to the relationship exemplified here.

[0079] As an example, the thickness of the reflective layer RL is 40 to 150 nm, the thickness of the metal layer ML is 10 to 50 nm, the thickness of the first covering layer V1 is 5 to 10 nm, and the thickness of the second covering layer V2 is 5 to 50 nm.

[0080] The end portion E1 of the lower electrode LE1 includes the end portion Em of the metal layer ML, the end portion Er of the reflective layer RL, the end portion Ec1 of the first cover layer V1, and the end portion Ec2 of the second cover layer V2.

[0081] In the present embodiment, the end Em protrudes more than the end Er. In addition, the ends Ec1 and Ec2 are set back from the end Er. The protrusion length L of the metal layer ML from the reflective layer RL is, for example, greater than or equal to the thickness of the reflective layer RL.

[0082] exist Figure 5 In the example of FIG. 1 , the end Em is tapered in a gradually decreasing thickness. The inclined surface of the end Em forms an angle of 60° or less with respect to the upper surface of the organic insulating layer 12 , for example.

[0083] Next, an example of a method for manufacturing the display device DSP according to the present embodiment will be described.

[0084] Figures 6 to 20The schematic cross-sectional views show the manufacturing process of the display device DSP. In these drawings, the substrate 10 and the circuit layer 11 are omitted.

[0085] When manufacturing the display device DSP, firstly, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10. Then, Figure 6 As shown, a metal layer MLa (first layer) formed of a metal material, a first covering layer V1a formed of a transparent conductive oxide, a reflective layer RLa (second layer) formed of a metal material, and a second covering layer V2a formed of a transparent conductive oxide are sequentially formed on the organic insulating layer 12.

[0086] The metal layer MLa, the first covering layer V1a, the reflective layer RLa and the second covering layer V2a are layers processed into the metal layer ML, the first covering layer V1, the reflective layer RL and the second covering layer V2, respectively. These layers are formed in the entire display area DA and the peripheral area SA by sputtering, for example.

[0087] The thickness of the metal layer MLa, the first coating layer V1a, the reflective layer RLa, and the second coating layer V2a can be determined within the above-mentioned numerical range as the thickness of the metal layer ML, the first coating layer V1, the reflective layer RL, and the second coating layer V2. If a specific example is given, the metal layer MLa is 30 nm, the reflective layer RLa is 100 nm, the first coating layer V1a is 10 nm, and the second coating layer V2a is 25 nm.

[0088] Next, if Figure 7 As shown in FIG. 1 , a resist R0 having a shape corresponding to the lower electrodes LE1, LE2, and LE3 is disposed on the second covering layer V2a. Figure 7 to Figure 12 , the lower electrode LE1 is gradually formed. The lower electrodes LE2 and LE3 are also formed at the same time as the lower electrode LE1.

[0089] After the resist R0 is formed, wet etching is performed on the second covering layer V2a. In this wet etching, the portion of the second covering layer V2a exposed from the resist R0 is removed. Figure 8 As shown, the second coating layer V2 is formed. Figure 8 In the example of FIG. 1 , a second covering layer V2 having a width slightly smaller than that of the resist R0 is formed.

[0090] Next, wet etching (first etching) is performed on the reflective layer RLa. In this wet etching, the portion of the reflective layer RLa exposed from the resist R0 is removed. Fig. 9 As shown in FIG. 1 , a reflective layer RL is formed. In addition, in this wet etching, the width of the reflective layer RL is slightly reduced compared to the width of the resist R0. Fig. 9In the example of , a reflective layer RL having a width slightly smaller than that of the second covering layer V2 is formed.

[0091] After forming the reflective layer RL, the first covering layer V1a is subjected to wet etching. In the wet etching, the portion of the first covering layer V1a exposed from the resist R0 is removed. Fig.10 As shown, the first coating layer V1 is formed. Fig.10 In the example of FIG. 1 , a first coating layer V1 having a width slightly smaller than that of the reflective layer RL is formed. In addition, the second coating layer V2 may also be corroded during the wet etching. Fig.10 In the example of , the width of the second covering layer V2 is slightly smaller than that of the reflecting layer RL.

[0092] The material of the metal layer MLa is preferably not easily corroded by the etching solution used in the wet etching of the reflective layer RLa and the coating layers V1a and V2a. For example, in the wet etching of the reflective layer RLa, an etching solution containing phosphoric acid, nitric acid and acetic acid is used. The material of the metal layer MLa is formed of, for example, a metal material whose etching rate in such an etching solution is slower than that of the reflective layer RLa.

[0093] After forming the first coating layer V1, dry etching (second etching) is performed on the metal layer MLa. In this dry etching, the portion of the metal layer MLa exposed from the resist R0 is removed. Fig.11 As shown, a metal layer ML is formed.

[0094] The anisotropy of the dry etching is higher than that of the wet etching. Therefore, the metal layer ML is patterned into a planar shape closer to the resist R0 than the reflective layer RL, the first coating layer V1, and the second coating layer V2. As a result, Fig.11 As shown, the end Em of the metal layer ML protrudes from the end Er of the reflective layer RL.

[0095] In addition, the resist R0 is also slightly eroded during the dry etching. As a result, the width of the resist R0 is gradually reduced during the dry etching. As a result, the end Em of the metal layer ML becomes tapered.

[0096] After the metal layer ML, the first coating layer V1, the reflective layer RL, and the second coating layer V2 are formed in this way, the resist R0 is removed. Fig.12 As shown in FIG. 1 , the lower electrode LE1 is completed. The lower electrodes LE2 and LE3 are completed in the same manner.

[0097] After forming the lower electrodes LE1, LE2, LE3, as Fig.13 As shown in FIG. 1 , a rib layer 5 is formed to cover the lower electrodes LE1, LE2, and LE3. In addition, a partition wall 6 having a lower portion 61 and an upper portion 62 is formed on the rib layer 5. Figure 5As shown, the lower portion 61 includes a bottom layer 63 and an axis layer 64. Figure 5 As shown, the upper portion 62 includes a first top layer 65 and a second top layer 66. Fig.13 The structure of the lower electrodes LE1, LE2, and LE3 is shown in a simplified diagram.

[0098] After forming the partition wall 6, as Fig.14 As shown, the pixel openings AP1, AP2, and AP3 are formed in the rib layer 5. As another example, the pixel openings AP1, AP2, and AP3 may be formed before the partition 6 is formed.

[0099] Next, a process for forming display elements DE1, DE2, and DE3 is performed. In this embodiment, display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed. However, the order of forming display elements DE1, DE2, and DE3 is not limited to this example.

[0100] When forming the display element DE1, first, as Fig.15 As shown in FIG. 1 , a laminated film FL1 and a sealing layer SE11 are formed. Figure 3 As shown, the stacked film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1 , an upper electrode UE1 covering the organic layer OR1 , and a cap layer CP1 covering the upper electrode UE1 .

[0101] The organic layer OR1, the upper electrode UE1 and the cap layer CP1 are formed by evaporation. In addition, the sealing layer SE11 is formed by CVD (Chemical Vapor Deposition). The laminate film FL1 is partitioned into a plurality of parts by the cantilever partition wall 6. The sealing layer SE11 continuously covers the partitioned parts of the laminate film FL1 and the partition wall 6.

[0102] After forming the stacked film FL1 and the sealing layer SE11, as shown in FIG. Fig.15 As shown in FIG. 1 , a resist R1 is disposed on the sealing layer SE11 . The resist R1 covers the sub-pixel SP1 and a part of the partition wall 6 around it.

[0103] Then, if Fig.16 As shown, the portions of the laminated film FL1 and the sealing layer SE11 exposed from the resist R1 are removed by etching using the resist R1 as a mask. Thus, a display element DE1 is formed in the sub-pixel SP1. For example, the etching includes wet etching and dry etching sequentially performed on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, the resist R1 is removed.

[0104] The display element DE2 is formed in the same steps as the display element DE1. That is, when forming the display element DE2, Fig.17 As shown in FIG. 1 , the stacked film FL2 and the sealing layer SE12 are formed in the entire display area DA. Figure 3 As shown, the stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2.

[0105] The organic layer OR2, the upper electrode UE2 and the cap layer CP2 are formed by evaporation. In addition, the sealing layer SE12 is formed by CVD. The laminate film FL2 is partitioned into a plurality of parts by the cantilever partition wall 6. The sealing layer SE12 continuously covers the partitioned parts of the laminate film FL2 and the partition wall 6.

[0106] After forming the stacked film FL2 and the sealing layer SE12, as shown in FIG. Fig.17 As shown in FIG. 1 , a resist R2 is disposed on the sealing layer SE12 . The resist R2 covers the sub-pixel SP2 and a part of the partition wall 6 around it.

[0107] Then, by etching with the resist R2 as a mask, as Fig.18 As shown, the portions of the laminated film FL2 and the sealing layer SE12 exposed from the resist R2 are removed. Thus, a display element DE2 is formed in the sub-pixel SP2. For example, the etching includes wet etching and dry etching sequentially performed on the sealing layer SE12, the cap layer CP2, the upper electrode UE2, and the organic layer OR2. After these etchings, the resist R2 is removed.

[0108] The display element DE3 is formed in the same steps as the display elements DE1 and DE2. That is, when forming the display element DE3, Fig.19 As shown in FIG. 1 , the stacked film FL3 and the sealing layer SE13 are formed in the entire display area DA. Figure 3 As shown, the stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3.

[0109] The organic layer OR3, the upper electrode UE3 and the cap layer CP3 are formed by evaporation. In addition, the sealing layer SE13 is formed by CVD. The laminate film FL3 is partitioned into a plurality of parts by the cantilever partition wall 6. The sealing layer SE13 continuously covers the partitioned parts of the laminate film FL3 and the partition wall 6.

[0110] After forming the stacked film FL3 and the sealing layer SE13, as shown in FIG. Fig.19As shown in FIG. 1 , a resist R3 is disposed on the sealing layer SE13 . The resist R3 covers the sub-pixel SP3 and a part of the partition wall 6 around it.

[0111] Then, if Fig. 20 As shown, by etching using the resist R3 as a mask, the portions of the laminated film FL3 and the sealing layer SE13 exposed from the resist R3 are removed. Thus, a display element DE3 is formed in the sub-pixel SP3. For example, the etching includes wet etching and dry etching sequentially performed on the sealing layer SE13, the cap layer CP3, the upper electrode UE3, and the organic layer OR3. After these etchings, the resist R3 is removed.

[0112] After forming display elements DE1, DE2, and DE3, Figure 3 The resin layer RS1, the sealing layer SE2 and the resin layer RS2 are shown. After such steps, the display device DSP is completed.

[0113] In the present embodiment described above, a display device DSP including display elements DE1 , DE2 , DE3 can be obtained, wherein the display elements DE1 , DE2 , DE3 are separated for each sub-pixel SP1 , SP2 , SP3 by the cantilever-shaped partition wall 6 and are individually sealed.

[0114] Furthermore, according to the configuration of the lower electrodes LE1, LE2, and LE3 of this embodiment, the yield and reliability of the display device DSP can be improved. This effect will be described below.

[0115] Fig.21 1 is a diagram for explaining an example of the effect of this embodiment, and shows the structure near the end E1 of the lower electrode LE1. In order to improve the reflectivity of the lower electrode LE1, it is necessary to form the reflective layer RL thicker. In addition, it is difficult for the end Er of the reflective layer RL formed of a metal material such as silver and processed by wet etching to be formed into a tapered shape like the end Em of the metal layer ML. Therefore, the end Er can be formed as Figure 5 As shown in FIG. 1 , the shape is formed to be substantially parallel to the Z direction, or as shown in FIG. Fig.21 As shown, it is formed into a cantilever shape with a protruding upper end.

[0116] In addition, in the present embodiment, the rib layer 5 is formed of an inorganic insulating material. In this case, a crack CK extending from the end Er to the step portion ST on the upper surface of the rib layer 5 may be generated. Assuming that the lower electrode LE1 does not have a metal layer ML, a moisture path is formed from the organic insulating layer 12 to the upper surface of the rib layer 5 through the crack CK. If the moisture of the organic insulating layer 12 reaches the upper surface of the rib layer 5 through the moisture path, the organic layer OR1 disposed thereon may be corroded, and display failure may occur.

[0117] In contrast, in the present embodiment, the metal layer ML having the end Em protruding from the reflective layer RL is disposed. Thus, even when the crack CK is generated, the water path connecting the crack CK and the organic insulating layer 12 can be blocked by the metal layer ML.

[0118] In this embodiment, the metal layer ML is formed thinner than the reflective layer RL. In addition, the end Em of the metal layer ML is tapered. Thus, the generation of cracks CK caused by the end Em is suppressed.

[0119] In addition, in the present embodiment, the step portion ST on the upper surface of the rib layer 5 caused by the lower electrode LE1 is covered by the lower portion 61. In this case, the lower portion 61 can also block the moisture path caused by the crack CK.

[0120] Here, the effects achieved by the present embodiment have been described with focus on the lower electrode LE1 , but since the lower electrodes LE2 and LE3 also have the same configuration as the lower electrode LE1 , they achieve the same effects as the lower electrode LE1 .

[0121] [Second embodiment]

[0122] The second embodiment will be described. Configurations not particularly mentioned in this embodiment are the same as those in the first embodiment.

[0123] Fig. 22 1 is a schematic top view showing an example of the layout of the sub-pixels SP1, SP2, and SP3 of this embodiment. Fig. 22 As shown, the lower electrode LE1 has ends E1a, E1b, E1c, and E1d. The lower electrode LE2 has ends E2a, E2b, E2c, and E2d. The lower electrode LE3 has ends E3a, E3b, E3c, and E3d. The ends E1a, E1b, E2a, E2b, E3a, and E3b extend parallel to the Y direction. In addition, the ends E1c, E1d, E2c, E2d, E3c, and E3d extend parallel to the X direction. Each end is covered by the rib layer 5.

[0124] Fig. 22 The partition wall 6 shown corresponds to the shape of the lower portion 61, more specifically, to the shape of the shaft layer 64. In the present embodiment, a portion (first end) of each end of the lower electrodes LE1, LE2, and LE3 overlaps with the shaft layer 64, and the remaining portion (second end) does not overlap with the shaft layer 64. Here, the overlap of the ends of the lower electrodes LE1, LE2, and LE3 with the lower portion 61 means that these ends are located below the lower portion 61.

[0125] Specifically, the ends E1b and E1c of the lower electrode LE1 overlap with the lower portion 61, and the ends E1a and E1d do not overlap with the lower portion 61. In addition, the ends E2b, E2c, and E2d of the lower electrode LE2 overlap with the lower portion 61, and the end E2a does not overlap with the lower portion 61. In addition, the ends E3b and E3c of the lower electrode LE3 overlap with the lower portion 61, and the ends E3a and E3d do not overlap with the lower portion 61.

[0126] For example, if we focus on the lower electrodes LE1, LE2 and the lower portion 61 therebetween, one of the ends of the lower electrodes LE1, LE2 overlaps with the lower portion 61, and the other does not overlap with the lower portion 61. Thus, the relationship that the lower portion 61 overlaps with one end of the adjacent lower electrode and does not overlap with the other end is established in most of the lower portion 61. However, a portion 61X located between the pixel openings AP2, AP3 in the lower portion 61 overlaps with both the end E2d of the lower electrode LE2 and the end E3c of the lower electrode LE3. For example, a contact hole provided in the organic insulating layer 12 for connecting the lower electrodes LE2, LE3 to the pixel circuit 1 of the circuit layer 11 is arranged below the portion 61X.

[0127] Fig.23 It is along Fig. 22 A schematic cross-sectional view of the display device DSP along the line XXIII-XXIII in FIG. Figure 5 Similarly, the organic insulating layer 12 , the rib layer 5 , the partition wall 6 , and the lower electrodes LE1 , LE2 are shown, and other elements are omitted.

[0128] The step portion ST generated on the upper surface of the rib layer 5 due to the end portion located below the partition wall 6, such as the end portion E2b, is covered by the bottom layer 63 and the shaft layer 64. On the other hand, the step portion ST generated by the end portion not located below the partition wall 6, such as the end portion E1a, is not covered by the bottom layer 63 and the shaft layer 64.

[0129] The rib layer 5 has a width Wa. The partition wall 6 has a width Wb smaller than the width Wa (Wa>Wb). The width Wa corresponds to the distance between the pixel openings AP1 and AP2. The width Wb corresponds to the width of the upper portion 62, more specifically, the width of the first top layer 65. The distance Da between the metal layers ML of the lower electrodes LE1 and LE2 is smaller than the width Wa (Da<Wa). The distance Da is, for example, equal to the width Wb.

[0130] The end E1a of the lower electrode LE1 and the upper portion 62 are separated from each other in a plan view. The distance Db between the end E1a and the upper portion 62 in a plan view is, for example, 1 / 2 or more of the total thickness T of the rib layer 5 and the lower portion 61 (the bottom layer 63 and the shaft layer 64). It should be noted that the distance Db is more specifically equivalent to the distance between the end of the metal layer ML at the end E1a and the first top layer 65 in a plan view.

[0131] In the present embodiment, the distance Dc1 between the end E1a and the pixel opening AP1 when viewed from above is smaller than the distance Dc2 between the end E2b and the pixel opening AP2 when viewed from above (Dc1<Dc2). It should be noted that the distance Dc1 is more specifically equivalent to the distance between the end of the metal layer ML at the end E1a and the pixel opening AP1 when viewed from above. In addition, the distance Dc2 is more specifically equivalent to the distance between the end of the metal layer ML at the end E2b and the pixel opening AP2 when viewed from above.

[0132] Fig.23 The structure shown can also be applied to the structure near the adjacent lower electrodes LE1 and LE3, the structure near the adjacent lower electrodes LE2 and LE3, and the structure near the two adjacent lower electrodes LE1.

[0133] Even if a portion of each of the lower electrodes LE1, LE2, and LE3 overlaps with the lower portion 61 and the remaining portion does not overlap with the lower portion 61 as in the present embodiment, the effect of blocking the moisture path caused by the cracks in the rib layer 5 by the metal layer ML can be obtained in the same manner as in the first embodiment.

[0134] Fig.24 and Fig.25 are schematic cross-sectional views of the structures of the comparative examples. Fig.23 Similarly, attention is paid to the end portions E1 a and E2 b of the lower electrodes LE1 and LE2 , the rib layers 5 , and the barrier ribs 6 .

[0135] exist Fig.24 In the embodiment, the end E1a of the lower electrode LE1 and the end E2b of the lower electrode LE2 are not located below the partition wall 6 . Therefore, the step portion ST formed by the end portions E1a and E2b is exposed from the lower portion 61 .

[0136] When forming the partition wall 6, the layers for processing into the bottom layer 63, the shaft layer 64, the first top layer 65 and the second top layer 66 are formed in the entire display area DA. These layers may be deformed according to the step portion ST. Assuming that the step portion ST is designed to be close to the lower portion 61, the end of the upper portion 62 (the first top layer 65 and the second top layer 66) protruding from the lower portion 61 will include a portion deformed by the influence of the step portion ST. Specifically, the end of the upper portion 62 may be warped upward.

[0137] The layers constituting the stacked films FL1, FL2, and FL3 are formed by evaporation over the entire display area DA, and are then partitioned by the cantilevered partition wall 6. If the end of the upper portion 62 is tilted upward, for example, the organic layers OR1, OR2, and OR3 may adhere to a large area of ​​the lower portion 61, which may hinder the contact between the upper electrodes UE1, UE2, and UE3 formed later and the lower portion 61.

[0138] Therefore, in Fig.24 In the structure, the ends E1a and E2b of the lower electrodes LE1 and LE2 need to be sufficiently separated from the partition wall 6. For example, by setting the distance Db between the upper portion 62 and the ends E1a and E2b in a plan view to be greater than 1 / 2 of the total thickness T of the rib layer 5 and the lower portion 61 (Db ≥ T / 2) as described above, the shape defects of the ends of the upper portion 62 can be suppressed.

[0139] However, in Fig.24 In the structure, it is necessary to ensure a distance Db on both sides of the partition 6. As a result, the width Wa of the rib layer 5 is also increased. If the width Wa of the rib layer 5 is increased, the pixel openings AP1, AP2, and AP3 are correspondingly reduced, and the aperture ratio of the sub-pixels SP1, SP2, and SP3 is reduced.

[0140] exist Fig.25 In the embodiment, both ends E1a and E2b of the lower electrodes LE1 and LE2 are located below the lower portion 61. Thus, both step portions ST caused by the ends E1a and E2b are covered by the lower portion 61. In this case, shape defects of the ends of the upper portion 62 caused by the step portions ST can be suppressed.

[0141] However, due to processing constraints, it is difficult to sufficiently reduce the distance Da between the lower electrodes LE1, LE2, and LE3. Fig.25 In the structure of , it is necessary to increase the width Wb of the partition wall 6 to a certain extent.

[0142] In addition, near the partition wall 6, the evaporation material emitted by the evaporation source is blocked by the upper portion 62, so the thickness of the laminated films FL1, FL2, and FL3 is reduced. Therefore, in order to form the laminated films FL1, FL2, and FL3 with a good thickness at the pixel openings AP1, AP2, and AP3, the partition wall 6 must be separated from the pixel openings AP1, AP2, and AP3 to a certain extent. If such a margin is taken into account, Fig.25 In the example, we also need Fig.24 The width Wa of the rib layer 5 is of the same degree.

[0143] With respect to these comparative examples, if Fig.23The structure of this embodiment shown can suppress the shape defect of the upper portion 62, reduce the width Wa of the rib layer 5, and increase the aperture ratio of the sub-pixels SP1, SP2, and SP3. This can improve the yield of the display device DSP and improve the display quality.

[0144] Specifically, in Fig.23 In the structure, since the step portion ST generated by the end E2b of the lower electrode LE2 is covered by the lower portion 61, the shape defect of the upper portion 62 caused by the step portion ST is suppressed. In addition, by setting the distance Db to be greater than 1 / 2 of the total thickness T, the shape defect of the upper portion 62 caused by the step portion ST generated by the end E1a of the lower electrode LE1 is also suppressed.

[0145] In addition, Fig.23 In the structure of FIG. 1 , since the distance Db is ensured, even if the distance Dc1 between the end E1a and the pixel opening AP1 is reduced, a laminated film FL2 with a good thickness can be formed in the pixel opening AP2. Thus, the width Wa of the rib layer 5 can be made smaller than Fig.24 and Fig.25 The comparative example is small.

[0146] It should be noted that, here, Fig.23 , Fig.24 and Fig.25 As shown, the effect of this embodiment is described with focus on the structure near the ends of adjacent lower electrodes LE1 and LE2, but the same effect can be obtained based on the structure near the ends of adjacent lower electrodes LE1 and LE3, the structure near the ends of adjacent lower electrodes LE2 and LE3, and the structure near the ends of two adjacent lower electrodes LE1.

[0147] The positional relationship between the end portions of the lower electrodes LE1, LE2, LE3 and the lower portion 61 is not limited to Fig. 22 In addition, various forms can be applied to the positional relationship between the end portions of the lower electrodes LE1 , LE2 , and LE3 and the lower portion 61 .

[0148] As long as the gist of the present invention is included, all display devices and methods of manufacturing the same that can be implemented by a person skilled in the art by appropriately changing the design based on the display device and method of manufacturing the same disclosed in the above embodiments also fall within the scope of the present invention.

[0149] Within the scope of the concept of the present invention, those skilled in the art can think of various variations, and these variations should also be understood to belong to the scope of the present invention. For example, the scheme obtained by adding, deleting or designing the above-mentioned embodiments appropriately by those skilled in the art, or the scheme obtained by adding, omitting or changing the conditions of the processes, as long as they have the gist of the present invention, is also included in the scope of the present invention.

[0150] In addition, regarding other effects brought about by the scheme described in the above-mentioned embodiment, the effects that can be clearly understood from the description of this specification or the technical effects that can be appropriately thought of by those skilled in the art should of course be understood as the effects brought about by the present invention.

Claims

1. A display device comprising: Insulation layer; A lower electrode, which is arranged above the insulating layer; a rib layer having a pixel opening overlapping the lower electrode; a partition wall including a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion; an organic layer, which covers the lower electrode through the pixel opening and emits light in response to application of a voltage; and an upper electrode covering the organic layer, The lower electrode comprises: a reflective layer that reflects light emitted from the organic layer; and The metal layer is disposed between the reflective layer and the insulating layer and has an end portion protruding from the reflective layer.

2. The display device according to claim 1, wherein: The rib layer is formed of an inorganic insulating material.

3. The display device according to claim 1, wherein: The metal layer is thinner than the reflective layer.

4. The display device according to claim 1, wherein: The reflective layer is formed of silver, The metal layer is formed of titanium, titanium nitride, tungsten or a molybdenum-tungsten alloy. 5 . The display device according to claim 1 , further comprising a first covering layer, the first covering layer being formed of a transparent conductive oxide and covering a lower surface of the reflective layer facing the metal layer.

6. The display device according to claim 5, wherein: The first coating layer is thinner than the metal layer.

7. The display device according to claim 5, wherein: An end portion of the first covering layer is set back from an end portion of the reflecting layer. 8 . The display device according to claim 5 , further comprising a second covering layer, the second covering layer being formed of a transparent conductive oxide and covering an upper surface of the reflecting layer.

9. The display device according to claim 8, wherein: The second covering layer is thicker than the first covering layer and thinner than the reflecting layer.

10. The display device according to claim 8, wherein: An end portion of the second covering layer is set back from an end portion of the reflecting layer.

11. The display device according to claim 1, wherein: The protrusion length of the metal layer from the reflective layer is greater than or equal to the thickness of the reflective layer.

12. The display device according to claim 1, wherein: The end portion of the metal layer is in a tapered shape with a thickness gradually decreasing.

13. The display device according to claim 1, wherein: The end portion of the metal layer entirely overlaps the lower portion in a plan view.

14. The display device according to claim 1, wherein: The metal layer has: a first end portion overlapping the lower portion in a plan view; and The second end portion does not overlap with the lower portion in a plan view.

15. The display device according to claim 14, wherein: A distance between the second end portion and the upper portion in a plan view is equal to or greater than 1 / 2 of a total thickness of the rib layer and the lower portion.

16. A method for manufacturing a display device, comprising: Forming an insulating layer, A lower electrode is formed above the insulating layer, the lower electrode including a reflective layer for reflecting light and a metal layer disposed between the reflective layer and the insulating layer and having an end protruding from the reflective layer, forming a rib layer covering the lower electrode, forming a partition wall including a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion, Before or after forming the partition wall, a pixel opening is formed in the rib layer. forming an organic layer, the organic layer covering the lower electrode through the pixel opening and emitting light in response to application of a voltage, An upper electrode covering the organic layer is formed.

17. The method for manufacturing a display device according to claim 16, wherein: The forming of the lower electrode comprises: forming a first layer of the material of the metal layer on the insulating layer, forming a second layer of the material of the reflective layer on the first layer, disposing a resist on the second layer, The reflective layer is formed by removing a portion of the second layer exposed from the resist by a first etching process, The metal layer is formed by removing the portion of the first layer exposed from the resist by second etching.

18. The method for manufacturing a display device according to claim 17, wherein: The first etching reduces the width of the second layer compared to the width of the resist.

19. The method for manufacturing a display device according to claim 17, wherein: The first etching is wet etching, The second etching is dry etching.

20. The method for manufacturing a display device according to claim 19, wherein: The first layer is formed of a metal material having an etching rate in the etching solution of the first etching lower than that of the second layer.

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