Display device and manufacturing method thereof

Abstract

The invention relates to a display device and a manufacturing method thereof. A display device according to one embodiment includes: an organic insulating layer disposed in a display region and a peripheral region; a lower electrode disposed above the organic insulating layer in the display region; a rib layer having a pixel opening; a first partition wall disposed above the rib layer in the display region; a second partition wall disposed above the rib layer in the peripheral region; an organic layer in contact with the lower electrode through the pixel opening; an upper electrode that covers the organic layer and is in contact with the first partition wall; a sealing layer covering the laminated film including the organic layer and the upper electrode; and a resin layer covering the sealing layer. Each of the first partition wall and the second partition wall includes a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion. The resin layer directly covers the rib layer and the second partition wall in at least a part of the peripheral region.

Description

[0001] Cross-references to related applications

[0002] This application claims the priority based on Japanese Patent Application No. 2023-147023 filed on September 11, 2023, and cites all the contents described in the Japanese Patent Application. Technical Field

[0003] Embodiments of the present invention relate to a display device and a method for manufacturing the same. Background Art

[0004] In recent years, display devices using organic light emitting diodes (OLEDs) as display elements have been put into practical use. In such display devices, a technology capable of improving the yield is required. Summary of the invention

[0005] In general, according to one embodiment, a display device includes: an organic insulating layer, which is arranged in a display area for displaying an image and a peripheral area around the display area; a lower electrode, which is arranged above the organic insulating layer in the display area; a rib layer, which is arranged in the display area and the peripheral area and has a pixel opening overlapping with the lower electrode; a first partition wall, which is arranged above the rib layer in the display area; a second partition wall, which is arranged above the rib layer in the peripheral area; an organic layer, which contacts the lower electrode through the pixel opening and emits light in response to the application of a voltage; an upper electrode, which covers the organic layer and contacts the first partition wall; a sealing layer, which covers a laminated film including the organic layer and the upper electrode; and a resin layer, which is arranged in the display area and the peripheral area and covers the sealing layer. Each of the first partition wall and the second partition wall includes a lower portion arranged above the rib layer and an upper portion having an end protruding from a side surface of the lower portion. The resin layer directly covers the rib layer and the second partition wall in at least a portion of the peripheral region.

[0006] According to another embodiment, a display device comprises: an organic insulating layer, which is arranged in a display area for displaying an image and a peripheral area around the above-mentioned display area; a first lower electrode, a second lower electrode and a third lower electrode arranged above the above-mentioned organic insulating layer in the above-mentioned display area; a rib layer, which is arranged in the above-mentioned display area and the above-mentioned peripheral area, and has a first pixel opening, a second pixel opening and a third pixel opening respectively overlapping with the above-mentioned first lower electrode, the above-mentioned second lower electrode and the above-mentioned third lower electrode; a first partition wall, which is arranged above the above-mentioned rib layer in the above-mentioned display area; a second partition wall, which is arranged above the above-mentioned rib layer in the above-mentioned peripheral area; a first organic layer, a second organic layer and a third organic layer, wherein the above-mentioned first organic layer, the second organic layer and the third organic layer The organic layer is in contact with the first lower electrode, the second lower electrode and the third lower electrode respectively through the first pixel opening, the second pixel opening and the third pixel opening, and emits light in response to the application of voltage; the first upper electrode, the second upper electrode and the third upper electrode, the first upper electrode, the second upper electrode and the third upper electrode respectively cover the first organic layer, the second organic layer and the third organic layer, and contact the first partition wall; the first sealing layer covers the first stacked film including the first organic layer and the first upper electrode; the second sealing layer covers the second stacked film including the second organic layer and the second upper electrode; and the third sealing layer covers the third stacked film including the third organic layer and the third upper electrode. The first partition wall and the second partition wall each include a lower portion arranged above the rib layer and an upper portion having an end protruding from a side surface of the lower portion. The wavelength of light emitted by the third organic layer is longer than the wavelength of light emitted by the first organic layer and the second organic layer. The third stacked film and the third sealing layer are also disposed in at least a portion of the peripheral region.

[0007] According to one embodiment, a method for manufacturing a display device includes: forming an organic insulating layer in a display area for displaying an image and in a peripheral area around the display area, forming a first lower electrode, a second lower electrode, and a third lower electrode above the organic insulating layer in the display area, forming a rib layer covering the first lower electrode, the second lower electrode, and the third lower electrode in the display area and the peripheral area, forming a first partition wall in the display area, the first partition wall including a lower portion arranged above the rib layer, and an upper portion having an end protruding from a side surface of the lower portion, forming a second partition wall including the lower portion and the upper portion in the peripheral area, before or after the formation of the first partition wall and the second partition wall, forming a first pixel opening, a second pixel opening, and a third pixel opening respectively overlapping with the first lower electrode, the second lower electrode, and the third lower electrode in the rib layer, and forming a first stacked film in the display area and the peripheral area, the first stacked film including a voltage corresponding to a voltage The first organic layer that emits light in response to the application of voltage and the first upper electrode in contact with the lower portion are formed to form a first sealing layer covering the first stacked film, the first stacked film and the first sealing layer are left as portions located above the first lower electrode, and the other portions in the display area and the portion located in the peripheral area are removed, and a second stacked film is formed in the display area and the peripheral area, the second stacked film includes a second organic layer that emits light in response to the application of voltage and a second upper electrode in contact with the lower portion, to form a second sealing layer covering the second stacked film, the second stacked film and the second sealing layer are left as portions located above the second lower electrode, and the other portions in the display area and the portion located in the peripheral area are removed, and a third stacked film is formed in the display area and the peripheral area, the third stacked film includes a third organic layer that emits light in response to the application of voltage and a third upper electrode in contact with the lower portion, to form a third sealing layer covering the third stacked film.

[0008] According to each embodiment, the yield of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a diagram showing a configuration example of a display device according to the first embodiment.

[0010] Figure 2 It is a schematic plan view showing an example of the layout of sub-pixels according to the first embodiment.

[0011] Figure 3 It is along Figure 2 Schematic cross-sectional view of the display device taken along line III-III.

[0012] Figure 4 This is a diagram showing an example of a layer structure that can be applied to an organic layer.

[0013] Figure 5 It is a schematic plan view of the display device according to the first embodiment.

[0014] Figure 6 It is along Figure 5 A schematic cross-sectional view of the display device taken along line VI-VI in FIG.

[0015] Figure 7 It is along Figure 5 A schematic cross-sectional view of the display device taken along line VII-VII in FIG.

[0016] Fig. 8A This is a schematic cross-sectional view of a display region of a display device manufactured by the manufacturing method of the first embodiment.

[0017] Figure 8B This is a schematic cross-sectional view of the peripheral region of the display device manufactured by the manufacturing method of the first embodiment.

[0018] Fig. 9A It means next Fig. 8A A schematic cross-sectional view of a display area of ​​a manufacturing process.

[0019] Fig. 9B It means next Figure 8B A schematic cross-sectional view of the peripheral area of ​​the manufacturing process.

[0020] Fig. 10A It means next Fig. 9A A schematic cross-sectional view of a display area of ​​a manufacturing process.

[0021] Fig. 10B It means next Fig. 9B A schematic cross-sectional view of the peripheral area of ​​the manufacturing process.

[0022] Fig.11A It means next Fig. 10A A schematic cross-sectional view of a display area of ​​a manufacturing process.

[0023] Fig. 11B It means next Fig. 10B A schematic cross-sectional view of the peripheral area of ​​the manufacturing process.

[0024] Fig. 12A It means next Fig.11A A schematic cross-sectional view of a display area of ​​a manufacturing process.

[0025] Fig. 12B It means next Fig. 11B A schematic cross-sectional view of the peripheral area of ​​the manufacturing process.

[0026] Fig.13A It means next Fig. 12A A schematic cross-sectional view of a display area showing the manufacturing process.

[0027] Fig. 13B It means next Fig. 12B A schematic cross-sectional view of the peripheral area of ​​the manufacturing process.

[0028] Fig.14A It means next Fig.13A A schematic cross-sectional view of a display area showing the manufacturing process.

[0029] Fig. 14B It means next Fig. 13B A schematic cross-sectional view of the peripheral area of ​​the manufacturing process.

[0030] Fig.15A It means next Fig.14A A schematic cross-sectional view of a display area of ​​a manufacturing process.

[0031] Fig. 15B It means next Fig. 14B A schematic cross-sectional view of the peripheral area of ​​the manufacturing process.

[0032] Fig.16A It means next Fig.15A A schematic cross-sectional view of a display area of ​​a manufacturing process.

[0033] Fig. 16B It means next Fig. 15B A schematic cross-sectional view of the peripheral area of ​​the manufacturing process.

[0034] Fig.17 This is a schematic cross-sectional view of the peripheral region of the display device according to the second embodiment.

[0035] Fig.18 It is a schematic cross-sectional view showing a manufacturing process of the display device according to the second embodiment.

[0036] Fig.19 It means next Fig.18 A schematic cross-sectional view of the peripheral area of ​​the manufacturing process.

[0037] Fig. 20 It means next Fig.19 A schematic cross-sectional view of the peripheral area of ​​the manufacturing process.

[0038] Fig.21 This is a schematic cross-sectional view showing an example of a peripheral region of a display device according to a third embodiment.

[0039] Fig. 22 is with Fig.21Similarly, a schematic cross-sectional view of an example of a peripheral region of a display device according to the third embodiment is shown.

[0040] Fig.23 This is a schematic cross-sectional view showing another example of the peripheral region of the display device according to the third embodiment. DETAILED DESCRIPTION

[0041] Several embodiments will be described with reference to the drawings.

[0042] The disclosed content is only an example, and appropriate changes that can be easily thought of by those skilled in the art while maintaining the main idea of ​​the invention are of course included in the scope of the present invention. In addition, with respect to the drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically shown compared with the actual method, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, for the constituent elements that have the same or similar functions as the constituent elements described in the drawings that have appeared, the same reference numerals are marked, and sometimes repeated detailed descriptions are appropriately omitted.

[0043] It should be noted that, for ease of understanding, mutually orthogonal X-axis, Y-axis and Z-axis are recorded in the drawings as needed. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of the plane including the X-direction and the Y-direction. In addition, the situation of observing various elements parallel to the Z-direction is called top-down observation.

[0044] The display device of each embodiment is an organic electroluminescent display device having an organic light emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, vehicle-mounted equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0045] [First embodiment]

[0046] Figure 1 1 is a diagram showing a configuration example of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 includes a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be glass or a flexible resin film.

[0047] In the present embodiment, the shape of the substrate 10 in a plan view is a rectangle, however, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0048] The display area DA includes a plurality of pixels PX arranged in a matrix in the X direction and the Y direction. The pixel PX includes a plurality of sub-pixels SP that display different colors. In the present embodiment, it is assumed that the pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. However, the pixel PX may also include a sub-pixel SP of another color such as white together with the sub-pixels SP1, SP2, and SP3 or instead of any of the sub-pixels SP1, SP2, and SP3.

[0049] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0050] In the display area DA, a plurality of scanning lines GL for supplying scanning signals to the pixel circuits 1 of the sub-pixels SP, a plurality of signal lines SL for supplying video signals to the pixel circuits 1 of the sub-pixels SP, and a plurality of power supply lines PL are arranged. Figure 1 In the example of FIG. 5 , the scanning lines GL and the power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0051] The gate electrode of the pixel switch 2 is connected to the scanning line GL. The source electrode of the pixel switch 2 is connected to the signal line SL. The drain electrode of the pixel switch 2 is connected to the gate electrode of the driving transistor 3 and the capacitor 4. The source electrode of the driving transistor 3 is connected to the power line PL and the capacitor 4. The drain electrode of the driving transistor 3 is connected to the display element DE.

[0052] It should be noted that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0053] Figure 2 1 is a schematic top view showing an example of the layout of sub-pixels SP1, SP2, and SP3. Figure 2 In the example of FIG. 1 , the sub-pixels SP2 and SP3 are arranged in the X direction with the sub-pixel SP1. In addition, the sub-pixel SP2 and the sub-pixel SP3 are arranged in the Y direction.

[0054] When the sub-pixels SP1, SP2, and SP3 are arranged in this manner, columns in which the sub-pixels SP2 and SP3 are alternately arranged in the Y direction and columns in which a plurality of sub-pixels SP1 are repeatedly arranged in the Y direction are formed in the display area DA. These columns are alternately arranged in the X direction. It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 Example.

[0055] The rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 (first to third pixel openings) in the sub-pixels SP1, SP2, and SP3, respectively. Figure 2 In the example, the pixel opening AP1 is larger than the pixel opening AP2, and the pixel opening AP2 is larger than the pixel opening AP3. That is, among the sub-pixels SP1, SP2, and SP3, the sub-pixel SP1 has the largest opening ratio, and the sub-pixel SP3 has the smallest opening ratio. It should be noted that the sizes of the pixel openings AP1, AP2, and AP3 are not limited to this example. For example, the pixel openings AP2 and AP3 may also have the same size.

[0056] The sub-pixel SP1 includes a lower electrode LE1 (first lower electrode), an upper electrode UE1 (first upper electrode), and an organic layer OR1 (first organic layer) that overlap with the pixel opening AP1, respectively. The sub-pixel SP2 includes a lower electrode LE2 (second lower electrode), an upper electrode UE2 (second upper electrode), and an organic layer OR2 (second organic layer) that overlap with the pixel opening AP2, respectively. The sub-pixel SP3 includes a lower electrode LE3 (third lower electrode), an upper electrode UE3 (third upper electrode), and an organic layer OR3 (third organic layer) that overlap with the pixel opening AP3, respectively.

[0057] The lower electrode LE1, the upper electrode UE1, and the portion of the organic layer OR1 that overlaps with the pixel opening AP1 constitute the display element DE1 of the sub-pixel SP1. The lower electrode LE2, the upper electrode UE2, and the portion of the organic layer OR2 that overlaps with the pixel opening AP2 constitute the display element DE2 of the sub-pixel SP2. The lower electrode LE3, the upper electrode UE3, and the portion of the organic layer OR3 that overlaps with the pixel opening AP3 constitute the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cover layer described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0058] The partition wall 6A (first partition wall) is disposed in the display area DA. The partition wall 6A is located above the rib layer 5 and overlaps with the rib layer 5 as a whole. Figure 2 In the example of FIG. 1 , the partition wall 6A has the same planar shape as the rib layer 5. That is, the partition wall 6A has openings in the sub-pixels SP1, SP2, and SP3, respectively. From another point of view, the rib layer 5 and the partition wall 6A are lattice-shaped when viewed from above, and surround each of the display elements DE1, DE2, and DE3. The partition wall 6A has a function as a wiring for supplying a common voltage to the upper electrodes UE1, UE2, and UE3.

[0059] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP along line III-III in FIG. A circuit layer 11 is arranged on the substrate 10. The circuit layer 11 includes Figure 1 The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that planarizes the unevenness generated in the circuit layer 11.

[0060] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Figure 3 The cross section of FIG. 1 is not shown, but the lower electrodes LE1, LE2, and LE3 are connected to the pixel circuit 1 ( 10 ) of the circuit layer 11 through contact holes provided in the organic insulating layer 12. Figure 1 The drain electrode of the driving transistor 3 shown is connected.

[0061] The partition wall 6A includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. Thus, both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. Such a shape of the partition wall 6A is called a cantilever shape.

[0062] exist Figure 3 In the example of FIG. 5 , the lower portion 61 has a bottom layer 63 and a shaft layer 64. The bottom layer 63 is located between the shaft layer 64 and the rib layer 5 and is formed to be thinner than the shaft layer 64. Figure 3 In the example, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64 .

[0063] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and is opposite to the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and is opposite to the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and is opposite to the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surface of the lower portion 61 of the partition wall 6A.

[0064] The display element DE1 includes a cover layer CP1 covering the upper electrode UE1. The display element DE2 includes a cover layer CP2 covering the upper electrode UE2. The display element DE3 includes a cover layer CP3 covering the upper electrode UE3. The cover layers CP1, CP2, and CP3 respectively have the function of serving as optical adjustment layers to improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3.

[0065] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is referred to as the stacked film FL1 (the first stacked film), the multilayer body including the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is referred to as the stacked film FL2 (the second stacked film), and the multilayer body including the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is referred to as the stacked film FL3 (the third stacked film).

[0066] A portion of the laminate film FL1 is located above the upper portion 62. This portion is separated from the portion of the laminate film FL1 located around the partition wall 6A (the portion constituting the display element DE1). Similarly, a portion of the laminate film FL2 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL2 located around the partition wall 6A (the portion constituting the display element DE2). In addition, a portion of the laminate film FL3 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL3 located around the partition wall 6A (the portion constituting the display element DE3).

[0067] The sub-pixels SP1, SP2, and SP3 are provided with sealing layers SE11, SE12, and SE13 (first to third sealing layers) that cover the laminated films FL1, FL2, and FL3, respectively. Specifically, the sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6A around the sub-pixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6A around the sub-pixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6A around the sub-pixel SP3.

[0068] exist Figure 3 In the example, the laminated film FL1 and the sealing layer SE11 on the partition wall 6A between the sub-pixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE12 on the partition wall 6A. In addition, the laminated film FL1 and the sealing layer SE11 on the partition wall 6A between the sub-pixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition wall 6A.

[0069] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are continuously provided at least in the entire display area DA, and a part of them also reaches the peripheral area SA.

[0070] A cover member such as a polarizing plate, a protective film or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0071] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx) or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of resin materials (organic insulating materials) such as epoxy resin and acrylic resin.

[0072] The lower electrodes LE1, LE2, and LE3 have a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed of a metal material having excellent light reflectivity, such as silver. Each conductive oxide layer can be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0073] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), etc. For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0074] Figure 4 : is a diagram showing an example of a layer structure that can be applied to the organic layers OR1, OR2, and OR3. The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including a light-emitting layer EML. In the present embodiment, it is assumed that the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL are sequentially stacked in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures such as a so-called series structure including a plurality of light-emitting layers EML.

[0075] The cover layers CP1, CP2, and CP3, for example, have a stacked structure formed by overlapping multiple transparent layers. These transparent layers may include layers formed by inorganic materials and layers formed by organic materials. In addition, these transparent layers have different refractive indices from each other. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the refractive indices of the sealing layers SE11, SE12, and SE13. It should be noted that at least one of the cover layers CP1, CP2, and CP3 may also be omitted.

[0076] The bottom layer 63 and the shaft layer 64 of the next wall 6A are formed of, for example, a metal material. As the metal material of the bottom layer 63, for example, molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW) or molybdenum-niobium alloy (MoNb) can be used. As the metal material of the shaft layer 64, for example, aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY) or aluminum-silicon alloy (AlSi) can be used. It should be noted that at least one of the bottom layer 63 and the shaft layer 64 can have a stacked structure of multiple layers. In addition, the shaft layer 64 can also include a layer formed by an insulating material.

[0077] For example, the upper portion 62 of the partition wall 6A has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. As the metal material forming the lower layer, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy can be used. As the conductive oxide forming the upper layer, for example, ITO or IZO can be used. It should be noted that the upper portion 62 may have a single-layer structure of a metal material. In addition, the upper portion 62 may include a layer formed of an insulating material.

[0078] The common voltage is supplied to the partition wall 6A. The common voltage is supplied to the upper electrodes UE1, UE2, UE3 in contact with the side surface of the lower portion 61. The lower electrodes LE1, LE2, LE3 are supplied with pixel voltages corresponding to the video signals of the signal lines SL through the pixel circuits 1 of the sub-pixels SP1, SP2, SP3, respectively.

[0079] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, if a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EML of the organic layer OR1 emits light in a blue wavelength region. If a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EML of the organic layer OR2 emits light in a green wavelength region. If a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EML of the organic layer OR3 emits light in a red wavelength region.

[0080] As another example, the light-emitting layers EML of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layer EML into light of a color corresponding to the sub-pixels SP1, SP2, and SP3. In addition, the display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layer EML to generate light of a color corresponding to the sub-pixels SP1, SP2, and SP3.

[0081] Figure 51 is a schematic plan view of the display device DSP. The display device DSP includes dam portions DM1, DM2, DM3, and DM4 arranged in the peripheral area SA. The dam portions DM1, DM2, DM3, and DM4 all surround the display area DA.

[0082] like Figure 5 As shown in the enlarged view in FIG. 1 , a partition wall 6B (second partition wall) is arranged in the peripheral area SA. For example, the partition wall 6B is lattice-shaped as shown in the figure, and is arranged in the area between the display area DA and the dam portion DM1. From another point of view, the partition wall 6B forms a plurality of closed areas CA. The closed area CA is, for example, a square or rectangular area, but may also have other shapes.

[0083] The shape of the partition walls 6B is not limited to the grid shape. As another example, a plurality of partition walls 6B separated from each other may be arranged in the surrounding area SA together with or instead of the grid-shaped partition walls 6B.

[0084] Figure 6 It is along Figure 5 A schematic cross-sectional view of the display device DSP taken along line VI-VI in FIG. The dam portions DM1 , DM2 , DM3 , and DM4 are formed of, for example, the organic insulating layer 12 , and have a convex shape facing the Z direction.

[0085] The rib layer 5, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 are also arranged in the peripheral area SA. Figure 6 In the example of FIG. 5 , the dam portions DM1 , DM2 , DM3 , and DM4 are covered with the rib layer 5 .

[0086] When manufacturing the display device DSP, the dams DM1, DM2, DM3, and DM4 play a role in intercepting the resin layers RS1 and RS2 before curing. Figure 6 In the example of , the end of the resin layer RS1 is located near the dam portion DM2, and the end of the resin layer RS2 is located near the dam portion DM4. However, the positions of the end portions of the resin layers RS1 and RS2 are not limited to this example.

[0087] exist Figure 6 In the example of FIG. 1 , the sealing layer SE2 protrudes from the end of the resin layer RS2 . The sealing layer SE2 is in contact with the rib layer 5 covering the dam portions DM2 , DM3 , and DM4 . As another example, the sealing layer SE2 may not protrude from the end of the resin layer RS2 .

[0088] It should be noted that the number of dam sections does not necessarily need to be Figure 5 and Figure 6 As shown, there are 4. That is, the display device DSP may include 3 or less or 5 or more dam portions.

[0089] Figure 7 It is along Figure 5 1 is a schematic cross-sectional view of the display device DSP taken along line VII-VII in FIG. The partition wall 6B has the same structure as the partition wall 6A. That is, the partition wall 6B includes a lower portion 61 and an upper portion 62. In addition, the lower portion 61 of the partition wall 6B includes a bottom layer 63 and an axis layer 64.

[0090] The partition wall 6B is arranged on the rib layer 5. Figure 7 In the cross section, no opening is provided in the rib layer 5 of the closed area CA. For example, the partition wall 6B is connected to the partition wall 6A. In addition, at any position of the peripheral area SA, the partition wall 6B is connected to the power supply line of the circuit layer 11 through the contact hole provided in the rib layer 5. Thus, a common voltage can be supplied to the partition wall 6A through the partition wall 6B. As another example, the partition wall 6B can also be floating.

[0091] In this embodiment, the stacked films FL1, FL2, FL3 and the sealing layers SE11, SE12, SE13 are not arranged in the peripheral area SA. Therefore, in the peripheral area SA, the resin layer RS1 directly covers the rib layer 5 and the partition 6B. In this way, the area where the resin layer RS1 directly covers the rib layer 5 and the partition 6B covers, for example, the entire area between the display area DA and the dam portion DM1, but is not limited to this example.

[0092] It should be noted that the laminated film FL1 and the sealing layer SE11, the laminated film FL2 and the sealing layer SE12, or the laminated film FL3 and the sealing layer SE13 may be arranged in a part of the peripheral area SA. In this case, in order to suppress the peeling of the laminated films FL1, FL2, FL3 described later, it is also preferred that the laminated films FL1, FL2, FL3 and the sealing layers SE11, SE12, SE13 are not arranged in most of the peripheral area SA.

[0093] Next, a method for manufacturing the display device DSP according to the present embodiment will be described.

[0094] FIG. 8A to FIG. 16A Each of them is a schematic cross-sectional view of a display area DA of the display device DSP manufactured by the manufacturing method of the present embodiment. FIG. 8B to FIG. 16B Each of them is a schematic cross-sectional view of the peripheral area SA of the display device DSP manufactured by the manufacturing method of this embodiment. FIG. 8A to FIG. 16A and FIG. 8B to FIG. 16B The substrate 10 and the circuit layer 11 are omitted.

[0095] In manufacturing the display device DSP, firstly, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10. Next, Fig. 8AAs shown, lower electrodes LE1, LE2, LE3 are formed on the organic insulating layer 12. In addition, a rib layer 5 covering the lower electrodes LE1, LE2, LE3, a first layer L1 covering the rib layer 5, a second layer L2 covering the first layer L1, and a third layer L3 covering the second layer L2 are sequentially formed.

[0096] The first layer L1, the second layer L2 and the third layer L3 are used to be processed into the bottom layer 63, the shaft layer 64 and the upper layer 62 respectively. Figure 8B As shown, the rib layer 5 , the first layer L1 , the second layer L2 , and the third layer L3 are also formed in the surrounding area SA.

[0097] Then, if Fig. 9A and Fig. 9B As shown, the first layer L1, the second layer L2, and the third layer L3 are patterned. The patterning includes etching to process the third layer L3 into the shape of the upper portion 62 of the partition walls 6A and 6B, etching to process the second layer L2 into the shape of the shaft layer 64 of the partition walls 6A and 6B, and etching to process the first layer L1 into the shape of the bottom layer 63 of the partition walls 6A and 6B. Through these etchings, the partition walls 6A are formed in the display area DA, and the partition walls 6B are formed in the peripheral area SA.

[0098] After forming the partition walls 6A and 6B, Fig. 9A As shown, pixel openings AP1, AP2, and AP3 are formed in the rib layer 5. As another example, the pixel openings AP1, AP2, and AP3 may be formed before forming the partition walls 6A and 6B.

[0099] Next, a process for forming display elements DE1, DE2, and DE3 is performed. In this embodiment, display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed. However, the order of forming display elements DE1, DE2, and DE3 is not limited to this example.

[0100] When forming the display element DE1, first, as Fig. 10A and Fig. 10B As shown in FIG. 1 , the laminate film FL1 and the sealing layer SE11 are formed in the entire display area DA and the peripheral area SA. Figure 3 As shown, the laminated film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cover layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cover layer CP1 are formed by evaporation. In addition, the sealing layer SE11 is formed by CVD (Chemical Vapor Deposition).

[0101] The laminated film FL1 is divided into a plurality of parts by cantilevered partition walls 6A and 6B. Fig. 10A As shown, the laminated film FL1 in the display area DA covers the lower electrodes LE1, LE2, LE3, the rib layer 5 and the partition 6A exposed through the pixel openings AP1, AP2, AP3. Fig. 10B As shown, the laminate film FL1 in the peripheral area SA covers the rib layer 5 and the partition walls 6B. The sealing layer SE11 continuously covers the divided portions of the laminate film FL1 and the partition walls 6A and 6B.

[0102] Next, the laminate film FL1 and the sealing layer SE11 are patterned. Fig. 10A As shown in FIG. 1 , a resist R1 is disposed on the sealing layer SE11 . The resist R1 covers the sub-pixel SP1 and a part of the partition wall 6A around it. The resist R1 is not disposed in the peripheral area SA.

[0103] Then, if Fig.11A and Fig. 11B As shown, by etching using the resist R1 as a mask, the portions of the laminated film FL1 and the sealing layer SE11 exposed from the resist R1 are removed. In other words, the portions of the laminated film FL1 and the sealing layer SE11 located above the lower electrode LE1 remain, and the other portions in the display area DA and the portions located in the peripheral area SA are removed. Thus, a display element DE1 is formed in the sub-pixel SP1. For example, the etching includes wet etching and dry etching sequentially performed on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After the etching, the resist R1 is removed.

[0104] The display element DE2 is formed in the same steps as the display element DE1. That is, when forming the display element DE2, first, Fig. 12A and Fig. 12B As shown in FIG. 1 , the stacked film FL2 and the sealing layer SE12 are formed in the entire display area DA and the peripheral area SA. Figure 3 As shown, the laminated film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2. The organic layer OR2, the upper electrode UE2, and the cap layer CP2 are formed by evaporation. In addition, the sealing layer SE12 is formed by CVD.

[0105] Next, the laminate film FL2 and the sealing layer SE12 are patterned. In this patterning, Fig. 12A As shown in FIG. 1 , a resist R2 is disposed on the sealing layer SE12. The resist R2 covers the sub-pixel SP2 and a part of the partition wall 6A around it. The resist R2 is not disposed in the peripheral area SA.

[0106] Then, by etching with the resist R2 as a mask, as Fig.13A and Fig. 13B As shown, the portions of the laminated film FL2 and the sealing layer SE12 exposed from the resist R2 are removed. In other words, the portions of the laminated film FL2 and the sealing layer SE12 located above the lower electrode LE2 remain, and the other portions in the display area DA and the portions located in the peripheral area SA are removed. Thus, a display element DE2 is formed in the sub-pixel SP2. For example, the etching includes wet etching and dry etching sequentially performed on the sealing layer SE12, the cover layer CP2, the upper electrode UE2, and the organic layer OR2. After the etching, the resist R2 is removed.

[0107] The display element DE3 is formed in the same steps as the display elements DE1 and DE2. That is, when forming the display element DE3, first, Fig.14A and Fig. 14B As shown in FIG. 1 , the stacked film FL3 and the sealing layer SE13 are formed in the entire display area DA and the peripheral area SA. Figure 3 As shown, the laminated film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3. The organic layer OR3, the upper electrode UE3 and the cap layer CP3 are formed by evaporation. In addition, the sealing layer SE13 is formed by CVD.

[0108] Next, the laminate film FL3 and the sealing layer SE13 are patterned. In this patterning, Fig.14A As shown in FIG. 1 , a resist R3 is disposed on the sealing layer SE13 . The resist R3 covers the sub-pixel SP3 and a part of the partition wall 6A around it. The resist R3 is not disposed in the peripheral area SA.

[0109] Then, by etching with the resist R3 as a mask, as Fig.15A and Fig. 15B As shown, the portions of the laminated film FL3 and the sealing layer SE13 exposed from the resist R3 are removed. In other words, the portions of the laminated film FL3 and the sealing layer SE13 located above the lower electrode LE3 remain, and the other portions in the display area DA and the portions located in the peripheral area SA are removed. Thus, a display element DE3 is formed in the sub-pixel SP3. For example, the etching includes wet etching and dry etching sequentially performed on the sealing layer SE13, the cover layer CP3, the upper electrode UE3 and the organic layer OR3. After the etching, the resist R3 is removed.

[0110] After forming the display elements DE1, DE2, DE3, as shown in FIG. Fig.16A and Fig. 16BAs shown, the resin layer RS1, the sealing layer SE2 and the resin layer RS2 are sequentially formed. The resin layer RS1 directly covers the sealing layers SE11, SE12 and SE13 in the display area DA. In addition, the resin layer RS1 directly covers the rib layer 5 and the partition 6B in the peripheral area SA.

[0111] The resin layers RS1 and RS2 can be formed by, for example, an inkjet method. The sealing layer SE2 can be formed by CVD. The resin layers RS1 and RS2 before curing are blocked by the dams DM1, DM2, DM3, and DM4 as described above.

[0112] The laminated films FL1, FL2, FL3 formed by evaporation have weak adhesion to the substrate, so they may be peeled off from the substrate during the manufacturing process of the display device DSP. If such peeling is extended, the laminated films FL1, FL2, FL3 and the sealing layers SE11, SE12, SE13 thereon may peel off, which may cause contamination of the chamber of the production line.

[0113] In this regard, in the present embodiment, the laminated films FL1, FL2, and FL3 are separated by cantilevered partition walls 6A and 6B. Therefore, even if peeling occurs in the laminated films FL1, FL2, and FL3, the range thereof is not easy to expand. In addition, the laminated films FL1, FL2, and FL3 separated by the partition walls 6A and 6B are suppressed by the sealing layers SE11, SE12, and SE13 formed in a manner sunken below the upper portions 62 of the partition walls 6A and 6B, and are therefore not easy to peel off.

[0114] However, assuming that in the peripheral area SA, the laminated film FL2 and the sealing layer SE12 are formed without removing the laminated film FL1 and the sealing layer SE11, the peeling suppression effect brought by the partition wall 6B may not be obtained. That is, the partition wall 6B is covered by the relatively thick sealing layer SE11, and the laminated film FL2 formed subsequently is not easily separated by the partition wall 6B. As a result, if the laminated film FL2 peels off, its range will expand and easily cause the laminated film FL2 and the sealing layer SE12 to peel off. The same is true when the laminated film FL3 and the sealing layer SE13 are formed without removing the laminated film FL2 and the sealing layer SE12.

[0115] In contrast, in the present embodiment, the laminated film FL1 and the sealing layer SE11 are removed in the peripheral area SA before the laminated film FL2 and the sealing layer SE12 are formed. In addition, the laminated film FL2 and the sealing layer SE12 are removed in the peripheral area SA before the laminated film FL3 and the sealing layer SE13 are formed. Therefore, the laminated films FL2 and FL3 are well separated by the partition wall 6B, and peeling of the laminated films FL2, FL3 and the sealing layers SE12 and SE13 can be suppressed.

[0116] Thus, according to the display device DSP and the manufacturing method thereof of the present embodiment, the yield rate when manufacturing the display device DSP can be improved. In addition, according to the present embodiment, various appropriate effects can be obtained.

[0117] [Second embodiment]

[0118] The second embodiment will be described. The configuration and manufacturing process of the display device DSP not mentioned in the following description are the same as those of the first embodiment.

[0119] Fig.17 It is a schematic cross-sectional view of the peripheral area SA of the display device DSP according to the second embodiment. In the present embodiment, the laminated film FL3 and the sealing layer SE13 are arranged in the peripheral area SA.

[0120] The laminated film FL3 disposed in the peripheral area SA is partitioned into a plurality of parts by the partition walls 6B. These parts are continuously covered with the sealing layer SE13. The sealing layer SE13 is covered with the resin layer RS1.

[0121] The laminated film FL3 and the sealing layer SE13 may be arranged in the entire peripheral area SA or in a part of the peripheral area SA. Figure 5 The area between the display area DA and the dam portion DM1 is shown. However, the stacked film FL3 and the sealing layer SE13 may cover at least a portion of the dam portions DM1, DM2, DM3, and DM4.

[0122] Next, a method for manufacturing the display device DSP of the present embodiment will be described. The steps of forming the partition walls 6A and 6B and the steps of forming the display elements DE1 and DE2 are the same as those in the first embodiment. FIG. 8A to FIG. 13A and FIG. 8B to FIG. 13B As described.

[0123] Figures 18 to 20 1 is a schematic cross-sectional view showing the manufacturing process of the display device DSP of this embodiment. When forming the display element DE3, similarly to the first embodiment, the laminated film FL3 and the sealing layer SE13 are formed in the entire display area DA and the peripheral area SA. In addition, the laminated film FL3 and the sealing layer SE13 are patterned using the resist R3 as a mask. The structure of the display area DA at this time is as follows: Fig.14A and Fig.15A shown.

[0124] On the other hand, in the surrounding area SA, as Fig.18 As shown in FIG. 1 , the resist R3 is disposed in the region where the stacked film FL3 and the sealing layer SE13 need to remain. If etching is performed in this state, Fig.19As shown, the stacked film FL3 and the sealing layer SE13 remain in the peripheral area SA. That is, in this etching, the stacked film FL3 and the sealing layer SE13, the portion located above the lower electrode LE3 and the portion located in the peripheral area SA remain, and the other portions in the display area DA are removed.

[0125] Then, if Fig. 20 As shown, the resin layer RS1, the sealing layer SE2 and the resin layer RS2 are formed in sequence. Fig.17 The structure of the surrounding area SA is shown.

[0126] In this embodiment, the laminated film FL1 and the sealing layer SE11 are removed in the peripheral area SA before the laminated film FL2 and the sealing layer SE12 are formed. In addition, the laminated film FL2 and the sealing layer SE12 are removed in the peripheral area SA before the laminated film FL3 and the sealing layer SE13 are formed. Therefore, similarly to the first embodiment, peeling of the laminated films FL2, FL3 and the sealing layers SE12, SE13 can be suppressed.

[0127] In the display device DSP of the present embodiment, the sealing layer SE13 is disposed above the organic insulating layer 12 in the peripheral area SA. This improves the effect of suppressing the intrusion of moisture into the organic insulating layer 12 compared to the configuration of the first embodiment.

[0128] It should be noted that for Figure 4 As for the luminescent performance of the organic layers OR1, OR2, and OR3 having the structure shown, the shorter the wavelength of light emitted, the more easily it is affected by the surface properties of the lower electrodes LE1, LE2, and LE3 serving as the base. The surface properties of the lower electrodes LE1, LE2, and LE3 may be deteriorated due to exposure to etching of the stacked films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13. Therefore, the organic layers OR1, OR2, and OR3 are preferably formed of organic layers that emit short wavelength light as described above.

[0129] As described above, the organic layer OR1 emits blue light, the organic layer OR2 emits green light, and the organic layer OR3 emits red light. The wavelength of blue light is shorter than that of green light, and the wavelength of green light is shorter than that of red light. Therefore, as in the first embodiment and the second embodiment, when the display element DE1 is formed first, the display element DE2 is formed second, and the display element DE3 is formed last, a display device DSP having stable display quality and excellent reliability can be obtained.

[0130] In the display device DSP of this embodiment, the organic layer OR3 that emits light having a longer wavelength than the organic layers OR1 and OR2 is disposed in at least a portion of the peripheral area SA. Figure 2 In the case of the illustrated layout, the organic layer OR3 arranged in the pixel opening AP3 smaller than the pixel openings AP1 and AP2 is arranged in at least a part of the peripheral area SA.

[0131] [Third Embodiment]

[0132] In the first and second embodiments, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 are stacked in the display area DA and the peripheral area SA. In this embodiment, the resin layer RS1 is not configured in at least the peripheral area SA. The structure and manufacturing process of the display device DSP not mentioned in the following description are the same as those in the first or second embodiment.

[0133] Fig.21 and Fig. 22 1 is a schematic cross-sectional view showing an example of the peripheral area SA of the display device DSP according to the third embodiment. Fig.21 Equivalent to Figure 6 Likewise along Figure 5 The cross section of the VI-VI line in Fig. 22 Equivalent to Figure 7 Likewise along Figure 5 The cross section along line VII-VII in FIG.

[0134] exist Fig.21 and Fig. 22 In the embodiment, similarly to the first embodiment, the laminated films FL1, FL2, FL3 and the sealing layers SE11, SE12, SE13 are not arranged in the peripheral area SA. In addition, as described above, the resin layer RS1 is not arranged in the peripheral area SA. Fig.21 In the example of FIG. 5 , the sealing layer SE2 is in contact with the entire rib layer 5 covering the dam portions DM1 , DM2 , DM3 , and DM4 .

[0135] In addition, Fig. 22 In the example of FIG. 5 , the sealing layer SE2 continuously covers the partition wall 6B and the rib layer 5. Specifically, the sealing layer SE2 is in contact with the bottom layer 63, the shaft layer 64, and the upper portion 62 of the partition wall 6B, and is in contact with the rib layer 5 in the closed area CA.

[0136] Fig.23 FIG. 2 is a schematic cross-sectional view showing another example of the peripheral area SA of the display device DSP according to the third embodiment. Fig.23 In the second embodiment ( Fig.17) Similarly, the stacked film FL3 and the sealing layer SE13 are arranged in the peripheral area SA. In addition, the sealing layer SE2 is in contact with the sealing layer SE13.

[0137] Even when the resin layer RS1 is not disposed in the peripheral area SA as in the present embodiment, the same effects as those of the above-described embodiments can be obtained.

[0138] As long as the gist of the present invention is included, all display devices and methods of manufacturing the same that can be implemented by a person skilled in the art by appropriately changing the design based on the display device and method of manufacturing the same disclosed in the above embodiments also fall within the scope of the present invention.

[0139] Within the scope of the concept of the present invention, those skilled in the art can think of various variations, and these variations should also be understood to belong to the scope of the present invention. For example, the scheme obtained by adding, deleting or designing the above-mentioned embodiments appropriately by those skilled in the art, or the scheme obtained by adding, omitting or changing the conditions of the processes, as long as they have the gist of the present invention, is also included in the scope of the present invention.

[0140] In addition, regarding other effects brought about by the scheme described in the above-mentioned embodiment, the effects that can be clearly understood from the description of this specification or the technical effects that can be appropriately thought of by those skilled in the art should of course be understood as the effects brought about by the present invention.

Claims

1. A display device comprising: An organic insulating layer, which is arranged in a display area for displaying an image and a peripheral area around the display area; A lower electrode, which is arranged above the organic insulating layer in the display area; a rib layer, which is disposed in the display area and the peripheral area and has a pixel opening overlapping with the lower electrode; a first partition wall disposed above the rib layer in the display region; a second partition wall disposed above the rib layer in the peripheral region; an organic layer that contacts the lower electrode through the pixel opening and emits light in response to application of a voltage; an upper electrode covering the organic layer and contacting the first partition wall; a sealing layer covering the stacked film including the organic layer and the upper electrode; and a resin layer, which is arranged in the display area and the peripheral area and covers the sealing layer, Each of the first partition wall and the second partition wall includes a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion. The resin layer directly covers the rib layer and the second partition wall in at least a portion of the peripheral region.

2. The display device according to claim 1, further comprising a dam portion, the dam portion being formed by the organic insulating layer located in the peripheral region and surrounding the display region, The resin layer directly covers the rib layer and the second barrier rib in a region between the display region and the dam portion.

3. The display device according to claim 1, wherein: At least a portion of the second partition walls is in a lattice shape.

4. The display device according to claim 1, wherein: The lower portion of each of the first partition wall and the second partition wall includes a shaft layer and a bottom layer located between the shaft layer and the rib layer. Ends of the bottom layer protrude from sides of the shaft layer.

5. The display device according to claim 1, wherein: The stacked film further includes an optical adjustment layer covering the upper electrode.

6. A display device comprising: An organic insulating layer, which is arranged in a display area for displaying an image and a peripheral area around the display area; A first lower electrode, a second lower electrode and a third lower electrode arranged above the organic insulating layer in the display area; a rib layer, which is arranged in the display area and the peripheral area, and has a first pixel opening, a second pixel opening and a third pixel opening respectively overlapping with the first lower electrode, the second lower electrode and the third lower electrode; a first partition wall disposed above the rib layer in the display region; a second partition wall disposed above the rib layer in the peripheral region; a first organic layer, a second organic layer, and a third organic layer, wherein the first organic layer, the second organic layer, and the third organic layer are respectively in contact with the first lower electrode, the second lower electrode, and the third lower electrode through the first pixel opening, the second pixel opening, and the third pixel opening, and emit light in response to application of a voltage; a first upper electrode, a second upper electrode and a third upper electrode, wherein the first upper electrode, the second upper electrode and the third upper electrode respectively cover the first organic layer, the second organic layer and the third organic layer and are in contact with the first partition wall; a first sealing layer covering a first stacked film including the first organic layer and the first upper electrode; a second sealing layer covering a second stacked film including the second organic layer and the second upper electrode; and a third sealing layer covering a third laminated film including the third organic layer and the third upper electrode, Each of the first partition wall and the second partition wall includes a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion. The wavelength of light emitted by the third organic layer is longer than the wavelength of light emitted by the first organic layer and the second organic layer, respectively. The third laminated film and the third sealing layer are also arranged in at least a portion of the peripheral region.

7. The display device according to claim 6, wherein: The third pixel opening is smaller than at least one of the first pixel opening and the second pixel opening.

8. The display device according to claim 6, wherein: The first organic layer emits blue light, The second organic layer emits green light, The third organic layer emits red light. 9 . The display device according to claim 6 , further comprising a resin layer covering the first sealing layer, the second sealing layer, and the third sealing layer in the display region and covering the third sealing layer in the peripheral region.

10. The display device according to claim 6, wherein: At least a portion of the second partition walls is in a lattice shape.

11. The display device according to claim 6, wherein: The third stacked film located in the peripheral region is partitioned by the second partition walls.

12. The display device according to claim 11, wherein: The third sealing layer located in the peripheral region continuously covers the third laminated film partitioned by the second partition walls.

13. The display device according to claim 6, wherein: The lower portion of each of the first partition wall and the second partition wall includes a shaft layer and a bottom layer located between the shaft layer and the rib layer. Ends of the bottom layer protrude from sides of the shaft layer.

14. A method for manufacturing a display device, comprising: An organic insulating layer is formed in a display area for displaying an image and in a peripheral area around the display area. forming a first lower electrode, a second lower electrode and a third lower electrode above the organic insulating layer in the display area, forming a rib layer covering the first lower electrode, the second lower electrode and the third lower electrode in the display area and the peripheral area, forming a first partition wall in the display region, the first partition wall including a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion, forming a second partition wall including the lower portion and the upper portion in the peripheral region, Before or after the formation of the first partition wall and the second partition wall, a first pixel opening, a second pixel opening, and a third pixel opening respectively overlapping with the first lower electrode, the second lower electrode, and the third lower electrode are formed in the rib layer, A first stacked film is formed in the display region and the peripheral region, the first stacked film including a first organic layer that emits light in response to application of a voltage and a first upper electrode in contact with the lower portion, forming a first sealing layer covering the first laminate film, The first stacked film and the first sealing layer are left with portions located above the first lower electrode, and the other portions in the display region and the portion located in the peripheral region are removed. forming a second stacked film in the display region and the peripheral region, the second stacked film including a second organic layer that emits light in response to application of a voltage and a second upper electrode in contact with the lower portion, forming a second sealing layer covering the second laminate film, The second stacked film and the second sealing layer are left with portions located above the second lower electrode, and the other portions in the display region and the portion located in the peripheral region are removed. A third stacked film is formed in the display region and the peripheral region, the third stacked film including a third organic layer that emits light in response to application of a voltage and a third upper electrode in contact with the lower portion, A third sealing layer is formed to cover the third laminated film.

15. The method for manufacturing a display device according to claim 14, further comprising: The portions of the third stacked film and the third sealing layer located above the third lower electrode are left, and the other portions in the display region and the portion located in the peripheral region are removed.

16. The method for manufacturing a display device according to claim 15, further comprising: A resin layer is formed, the resin layer covering the first sealing layer, the second sealing layer, and the third sealing layer in the display region and directly covering the rib layer and the second barrier rib in at least a portion of the peripheral region.

17. The method for manufacturing a display device according to claim 14, further comprising: The third stacked film and the third sealing layer are left with portions located above the third lower electrode and portions located in the peripheral region, and the other portions in the display region are removed.

18. The method for manufacturing a display device according to claim 17, wherein: The wavelength of light emitted by the third organic layer is longer than the wavelengths of light emitted by the first organic layer and the second organic layer.

19. The method for manufacturing a display device according to claim 17, wherein: The third pixel opening is smaller than at least one of the first pixel opening and the second pixel opening.

20. The method for manufacturing a display device according to claim 17, wherein: The first organic layer emits blue light, The second organic layer emits green light, The third organic layer emits red light.

Images