Member for semiconductor manufacturing apparatus

Abstract

A wafer mounting table (10) is an example of a member for a semiconductor manufacturing apparatus, and is provided with a ceramic plate (20), a ceramic plate through-hole (24), a substrate (30), a substrate through-hole (34), an insulating sleeve (50), and a sleeve through-hole (54). The sleeve through-hole 54 passes through the insulating sleeve 50 in the vertical direction and communicates with the ceramic plate through-hole 24. The insulating sleeve (50) is inserted into the substrate through-hole (34), and the outer peripheral surface (50c) is adhered to the inner peripheral surface of the substrate through-hole (34) via an adhesive layer (60). The insulating sleeve (50) has at least one annular outer peripheral groove (52) on the outer peripheral surface (50c) of the insulating sleeve (50) excluding the upper end portion (56) of the insulating sleeve (50).

Description

Technical Field The present invention relates to a component for semiconductor manufacturing equipment. Background Art In the past, there is a known component for semiconductor manufacturing equipment, which includes: a ceramic plate with built-in electrodes, and a conductive substrate arranged on the lower surface side of the ceramic plate. For example, Patent Document 1 discloses: Based on the above-mentioned component for semiconductor manufacturing equipment, it includes: a ceramic plate through-hole that penetrates the ceramic plate along the thickness direction; a substrate through-hole that penetrates the substrate along the thickness direction; and an insulating sleeve that is inserted into the substrate through-hole, and the outer peripheral surface is bonded to the inner peripheral surface of the substrate through-hole by means of an adhesive layer. The insulating sleeve has a thick diameter portion on the side opposite to the ceramic plate and a thin diameter portion on the ceramic plate side, and the gap between the thin diameter portion and the substrate through-hole is filled with an adhesive. It is explained that the insulating sleeve can be firmly fixed and bonded to the substrate through-hole. Prior art literature Patent Literature Patent Document 1: Utility Model Grant No. 3182120 Summary of the invention However, when the insulating sleeve is inserted into the substrate through hole with the adhesive applied around the thin-diameter portion, the central axis of the thin-diameter portion is likely to be greatly inclined relative to the central axis of the substrate through hole, so there is a problem that the adhesive around the thin-diameter portion is easily scraped off by the substrate through hole. Therefore, sometimes the adhesive cannot fully fill the gap between the insulating sleeve and the substrate through hole, and cannot be firmly bonded. The present invention has been made to solve the above-mentioned problems, and a main object of the present invention is to enable the gap between the insulating sleeve and the substrate through-hole to be filled with an adhesive at a high filling rate.

[0001] The semiconductor manufacturing device component of the present invention comprises: A ceramic plate having a wafer placement surface on an upper surface and having electrodes built therein; A ceramic plate through hole, the ceramic plate through hole penetrating the ceramic plate in an up-down direction; A conductive substrate disposed on the lower surface of the ceramic plate; A substrate through hole, the substrate through hole passes through the substrate in a vertical direction; an insulating sleeve, the insulating sleeve being inserted into the substrate through hole, the outer peripheral surface of the insulating sleeve being bonded to the inner peripheral surface of the substrate through hole by means of an adhesive layer; and a sleeve through hole, the sleeve through hole penetrating the insulating sleeve in the up-down direction and communicating with the ceramic plate through hole, The semiconductor manufacturing device component is characterized in that: The insulating sleeve has at least one annular or spiral outer peripheral groove on the outer peripheral surface of the insulating sleeve except for the upper end portion of the insulating sleeve. In the semiconductor manufacturing device component, the insulating sleeve has at least one annular or spiral peripheral groove on the outer peripheral surface except the upper end. When the insulating sleeve is inserted into the substrate through hole for bonding, an adhesive is applied to the outer peripheral surface of the insulating sleeve, and the insulating sleeve is inserted into the substrate through hole in this state, and then the adhesive is cured to form an adhesive layer. Although the insulating sleeve is inserted into the substrate through hole from the upper end, since the peripheral groove is not provided at the upper end, the outer diameter of the upper end does not become thinner. Therefore, when the upper end of the insulating sleeve is initially inserted into the substrate through hole, the central axis of the insulating sleeve will not be greatly tilted relative to the central axis of the substrate through hole, and the adhesive applied on the outer peripheral surface of the insulating sleeve is not easily scraped off by the substrate through hole. In addition, since the scraped adhesive can remain in the peripheral groove, the gap between the insulating sleeve and the substrate through hole is filled with adhesive at a high filling rate. As a result, the insulating sleeve can be firmly bonded to the substrate through hole.

[0002] In the semiconductor manufacturing device component of the present invention (the semiconductor manufacturing device component described in [1] above), the outer peripheral groove may be an annular groove, and a plurality of them may be provided on the outer peripheral surface of the insulating sleeve. When a plurality of annular outer peripheral grooves are provided, the filling rate of the adhesive filled in the gap between the insulating sleeve and the substrate through hole is likely to be increased compared to the case where only one such outer peripheral groove is provided.

[0003] In the semiconductor manufacturing device component of the present invention (the semiconductor manufacturing device component described in [2] above), the number of the peripheral grooves may be greater than 2 and less than 4. Accordingly, since the number of peripheral grooves is appropriate, the insulating sleeve can be manufactured more easily than in the case where the number of peripheral grooves is too large.

[0004] In the semiconductor manufacturing device component of the present invention (the semiconductor manufacturing device component described in any one of [1] to [3] above), the peripheral groove may not be provided at the lower end of the insulating sleeve. Even if the peripheral groove does not exist at the lower end of the insulating sleeve, it is easy to fill the adhesive between the insulating sleeve and the substrate through hole. Therefore, even if the peripheral groove is omitted at the lower end, the adhesion between the insulating sleeve and the substrate through hole can be maintained.

[0005] In the semiconductor manufacturing device component of the present invention (the semiconductor manufacturing device component described in [4] above), the lower end portion of the insulating sleeve can be the area from the lower end surface of the insulating sleeve to a specified height, and the specified height can be greater than 1 / 3 and less than 1 / 2 of the height of the insulating sleeve.

[0006] In the component for semiconductor manufacturing equipment of the present invention (the component for semiconductor manufacturing equipment described in any one of [1] to [5] above), the upper end portion of the insulating sleeve can be an area from the upper end surface of the insulating sleeve to a specified length, and the specified length can be greater than 1 mm and less than 3 mm. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 It is a top view of the wafer stage 10 . Figure 2 yes Figure 1 A-A cross-section diagram. Figure 3 yes Figure 2 A partial enlarged view of . Figure 4 It is a perspective view of the insulating sleeve 50 . Figure 5 It is a manufacturing process diagram of the wafer placement table 10. Figure 6 It is a partially enlarged view of a longitudinal cross-section of another example of the wafer placing table 10 . Figure 7 It is a partially enlarged view of a longitudinal cross-section of another example of the wafer placing table 10 . Figure 8 It is a partially enlarged view of a longitudinal cross-section of another example of the wafer placing table 10 . DETAILED DESCRIPTION Next, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Figure 1 is a top view of the wafer stage 10, Figure 2 yes Figure 1 A-A cross-section diagram, Figure 3 yes Figure 2 The enlarged view of the part (the enlarged view in the single-point dashed line frame), Figure 4 1 is a perspective view of the insulating sleeve 50. It should be noted that in this specification, "up" and "down" indicate relative positional relationships, not absolute positional relationships. Therefore, depending on the orientation of the wafer stage 10, "up" and "down" become "down", "up", or become "left", "right", or become "front", "rear". The wafer stage 10 is an example of a component for a semiconductor manufacturing apparatus of the present invention. Figure 2 As shown, it comprises: a ceramic plate 20 , a substrate 30 , a bonding layer 40 , an insulating sleeve 50 , and a gas hole 70 . The ceramic plate 20 is a circular plate (e.g., 300 mm in diameter and 5 mm in thickness) made of ceramic such as alumina sintered body or aluminum nitride sintered body. The upper surface of the ceramic plate 20 is a wafer placement surface 21 for placing the wafer W. The ceramic plate 20 has an electrostatic electrode 22 and a heater electrode 23 built therein in the order close to the wafer placement surface 21. Figure 1As shown, a ring-shaped sealing band 21a is formed along the outer edge of the wafer placing surface 21 of the ceramic plate 20, and a plurality of circular small protrusions 21b are formed on the entire inner surface of the sealing band 21a. The sealing band 21a and the circular small protrusions 21b are of the same height, and their heights are, for example, several μm to several tens of μm. The portion of the wafer placing surface 21 where the sealing band 21a and the circular small protrusions 21b are not provided is called a reference surface 21c. The electrostatic electrode 22 is a planar mesh electrode, which is connected to an external DC power source by means of a power supply component (not shown). The power supply component is electrically insulated from the substrate 30. When a DC voltage is applied to the electrostatic electrode 22, the wafer W is adsorbed and fixed to the wafer loading surface 21 (specifically, the upper surface of the sealing tape 21a and the upper surface of the circular small protrusion 21b) by electrostatic adsorption force; when the application of the DC voltage is released, the adsorption and fixation of the wafer W on the wafer loading surface 21 is released. The heater electrode 23 is a resistance heating element that is wired in a straight line from one end to the other end of the entire ceramic plate 20 when viewed from above. A heater power source is connected to one end and the other end of the heater electrode 23 by means of a power supply component (not shown). The power supply component is electrically insulated from the substrate 30. When the heater electrode 23 is energized, it generates heat to heat the wafer placement surface 21 and the wafer W. The substrate 30 is a circular plate with good electrical conductivity and thermal conductivity (for example, a circular plate with a diameter equal to or greater than that of the ceramic plate 20 and a thickness of 25 mm). A refrigerant flow path 32 for refrigerant circulation is formed inside the substrate 30. The refrigerant flowing in the refrigerant flow path 32 is preferably a liquid, and preferably electrically insulating. As electrically insulating liquids, for example, fluorine-based inactive liquids can be cited. The refrigerant flow path 32 is formed in a single stroke from one end (inlet) to the other end (outlet) of the substrate 30 as a whole when viewed from above. At one end and the other end of the refrigerant flow path 32 are respectively connected: a supply port and a recovery port of an external refrigerant device not shown in the figure. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 passes through the refrigerant flow path 32, and then returns to the recovery port of the external refrigerant device from the other end of the refrigerant flow path 32. After the temperature is adjusted, it is supplied again from the supply port to one end of the refrigerant flow path 32. The substrate 30 is connected to a high frequency (RF) power source and also serves as an RF electrode. The material of the substrate 30 may include, for example, a metal material, or a composite material of metal and ceramic. Examples of the metal material include: Al, Ti, Mo or alloys thereof. Examples of the composite material of metal and ceramic include: metal matrix composite material (MMC), ceramic matrix composite material (CMC), etc. Specific examples of the above composite materials include: a material containing Si, SiC and Ti (also referred to as SiSiCTi), a material obtained by impregnating Al and / or Si into a SiC porous body, a composite material of Al2O3 and TiC, etc. As the material of the substrate 30, a material having a thermal expansion coefficient close to that of the material of the ceramic plate 20 is preferred. Here, the bonding layer 40 is a resin bonding layer that bonds the lower surface of the ceramic plate 20 and the upper surface of the substrate 30. Examples of the material of the resin bonding layer include insulating resins such as epoxy resins, acrylic resins, and silicone resins. The insulating sleeve 50 is received in the substrate through hole 34. The substrate through hole 34 is a hole that penetrates the substrate 30 in the vertical direction and is arranged not to penetrate the refrigerant flow path 32. The insulating sleeve 50 is a substantially cylindrical component made of an electrically insulating material (for example, the same material as the ceramic plate 20), and has a sleeve through hole 54 that penetrates the insulating sleeve 50 in the vertical direction along the central axis of the insulating sleeve 50. The outer peripheral surface 50c of the insulating sleeve 50 is bonded to the inner peripheral surface of the substrate through hole 34 by means of an adhesive layer 60. As the material of the adhesive layer 60, for example, insulating resins such as epoxy resin, acrylic resin, and silicone resin can be cited. Figure 2 and Figure 3 , the adhesive layer 60 is shown to be filled without gaps between the outer peripheral surface 50c of the insulating sleeve 50 and the inner peripheral surface of the substrate through hole 34, but some gaps can be generated. A plurality of (here 2) annular peripheral grooves 52 are provided on the outer peripheral surface 50c of the insulating sleeve 50. Each peripheral groove 52 is provided on the outer peripheral surface 50c of the insulating sleeve 50 except the upper end portion (the end portion on the ceramic plate side) 56 of the insulating sleeve 50. The upper end portion 56 is an area from the upper end surface (the end surface on the ceramic plate side) 60a of the insulating sleeve 50 to a specified length. The specified length is preferably greater than 1 mm and less than 3 mm, and more preferably greater than 1.5 mm and less than 2.5 mm. The peripheral groove 52 is not provided at the lower end portion 58 of the insulating sleeve 50. The lower end portion 58 is an area from the lower end surface (the end surface on the opposite side of the ceramic plate 20) 50b of the insulating sleeve 50 to a specified height. The predetermined height is preferably not less than 1 / 3 and not more than 1 / 2 of the height of the insulating sleeve 50 . The interval d between adjacent outer peripheral grooves 52, 52 (see Figure 3) is preferably shorter, for example, preferably less than 3 mm, more preferably less than 2.5 mm, and further preferably less than 2 mm. The depth of the peripheral groove 52 is preferably deeper, for example, preferably more than 0.25 mm, more preferably more than 0.5 mm, and further preferably more than 0.7 mm. Among them, if the number of peripheral grooves 52 provided on the outer peripheral surface 50c of the insulating sleeve 50 is large, the depth of the peripheral groove 52 can be shallower. The number of peripheral grooves 52 is preferably large, but if there are too many, it is difficult to manufacture the insulating sleeve 50. From this aspect, it is preferably more than 2 and less than 4. The gas hole 70 is composed of a ceramic plate through hole 24, a bonding layer through hole 44 and a sleeve through hole 54. The ceramic plate through hole 24 penetrates the ceramic plate 20 in the up-down direction (thickness direction). The ceramic plate through hole 24 is open at the reference surface 21c of the wafer loading surface 21. The electrostatic electrode 22 and the heater electrode 23 are not exposed on the inner peripheral surface of the ceramic plate through hole 24. That is, the inner peripheral surface of the ceramic plate through hole 24 is covered with ceramic. The bonding layer through hole 44 penetrates the bonding layer 40 in the up-down direction (thickness direction) and is connected to the ceramic plate through hole 24. The inner diameter of the bonding layer through hole 44 is larger than the inner diameter of the ceramic plate through hole 24. The edge of the bonding layer through hole 44 is located at the upper end surface 50a of the insulating sleeve 50. The sleeve through hole 54 is connected to the ceramic plate through hole 24 and the bonding layer through hole 44. The inner diameter of the sleeve through hole 54 is larger than the inner diameter of the ceramic plate through hole 24 and smaller than the inner diameter of the bonding layer through hole 44. The gas hole 70 is used to supply the heat transfer gas to the wafer placement surface 21. Next, based on Figure 5 , an example of a method for manufacturing the wafer stage 10 is described. Figure 5 It is a manufacturing process diagram of the wafer placement table 10. First, the substrate 30 and the insulating sleeve 50 are prepared. Then, a high-viscosity adhesive 65 is applied to the outer peripheral surface 50c of the insulating sleeve 50, and the insulating sleeve 50 is inserted into the substrate through hole 34 ( Figure 5 (A)). The outer diameter of the upper end portion 56 of the insulating sleeve 50 is larger than the outer diameter of the portion where the outer peripheral groove 52 is formed. Therefore, when the upper end portion 56 of the insulating sleeve 50 is initially inserted into the substrate through-hole 34, the center axis of the upper end portion 56 will not be greatly tilted relative to the center axis of the substrate through-hole 34. In addition, as the insulating sleeve 50 is inserted into the substrate through-hole 34, a portion of the adhesive 65 is scraped off by the substrate through-hole 34, but the scraped off adhesive 65 enters the outer peripheral groove 52 and remains therein. Therefore, when the upper end surface 50a of the insulating sleeve 50 reaches a position consistent with the upper surface of the substrate 30, the gap between the outer peripheral surface 50c of the insulating sleeve 50 and the inner peripheral surface of the substrate through-hole 34 is filled with the adhesive 65 at a high filling rate. If the adhesive 65 is cured, it becomes an adhesive layer 60 ( Figure 5(B)). It should be noted that Figure 5 (A) shows the situation where the insulating sleeve 50 is inserted from below the substrate 30. However, Figure 5 (A) is turned upside down, and the insulating sleeve 50 is inserted from above the substrate 30. Next, the ceramic plate 20 and the bonding sheet 80 ( Figure 5 (B)). The bonding sheet 80 has a layer of adhesive (for example, a thermosetting resin adhesive) on both the upper and lower surfaces. The bonding sheet 80 is pre-set with a sheet through hole 84 that will eventually become the bonding layer through hole 44. Then, the ceramic plate 20 is stacked on the upper surface of the substrate 30 via the bonding sheet 80. At this time, the sleeve through hole 54, the sheet through hole 84 and the ceramic plate through hole 24 are arranged in a manner that is connected. Next, the stack is pressurized in a heated state and then cooled. Accordingly, the ceramic plate 20 and the substrate 30 are bonded through the bonding layer 40. In addition, the gas hole 70 is formed by connecting the ceramic plate through hole 24, the bonding layer through hole 44 and the sleeve through hole 54. As a result, the chip carrier 10 ( Figure 5 (C)). Next, an example of using the wafer carrier 10 constructed as above is described. First, in a state where the wafer carrier 10 is set in a chamber not shown in the figure, a wafer W is placed on the wafer placement surface 21. Then, the pressure in the chamber is reduced by a vacuum pump and adjusted to a specified vacuum degree, and a DC voltage is applied to the electrostatic electrode 22 of the ceramic plate 20 to generate an electrostatic adsorption force, so that the wafer W is adsorbed and fixed to the wafer placement surface 21 (specifically, the upper surface of the sealing tape 21a and the upper surface of the circular small protrusion 21b). In addition, the heater electrode 23 is energized to generate heat to heat the ceramic plate 20 and heat the wafer W to a specified temperature. In addition, a back side gas is introduced from a gas cylinder not shown in the figure into the sleeve through hole 54 constituting the gas hole 70. As the back side gas, a heat conductive gas (such as He gas, etc.) is used. The back side gas introduced into the gas hole 70 fills and seals the space between the back side of the chip W and the reference surface 21c of the chip placement surface 21 (the space surrounded by the back side of the chip W, the sealing tape 21a of the chip placement surface 21, the small circular protrusion 21b and the reference surface 21c). Due to the presence of this back side gas, heat conduction between the chip W and the ceramic plate 20 is efficiently performed. Next, the chamber is set to a reaction gas atmosphere of a specified pressure (for example, tens to hundreds of Pa). In this state, an RF voltage is applied between an upper electrode (not shown) provided at the top part of the chamber and the substrate 30 of the chip placement table 10 to generate plasma. The surface of the chip W is processed by the generated plasma. The coolant circulates in the coolant flow path 32 of the substrate 30 in a timely manner. In the wafer placement table 10 described in detail above, the insulating sleeve 50 has an annular outer peripheral groove 52 on the outer peripheral surface 50c except the upper end portion 56. When the insulating sleeve 50 is inserted into the substrate through hole 34 for bonding, an adhesive is applied to the outer peripheral surface 50c of the insulating sleeve 50, and the insulating sleeve 50 is inserted into the substrate through hole 34 in this state, and then the adhesive is cured to form the bonding layer 40. Although the insulating sleeve 50 is inserted into the substrate through hole 34 from the upper end portion 56, since the outer peripheral groove 52 is not provided at the upper end portion 56, the outer diameter of the upper end portion 56 does not become thinner. Therefore, when the upper end portion 56 of the insulating sleeve 50 is initially inserted into the substrate through hole 34, the central axis of the insulating sleeve 50 does not tilt significantly relative to the central axis of the substrate through hole 34, and the adhesive on the outer peripheral surface 50c is not easily scraped off by the substrate through hole 34. In addition, since the scraped adhesive can remain in the outer peripheral groove 52, the gap between the insulating sleeve 50 and the substrate through-hole 34 is filled with the adhesive at a high filling rate. As a result, the insulating sleeve 50 can be firmly bonded to the substrate through-hole 34. It should be noted that the length in the vertical direction of the adhesive filled in the gap between the insulating sleeve 50 and the substrate through-hole 34 (filling length) may be used as an indicator instead of the filling rate of the adhesive filled in the gap. Furthermore, since two outer peripheral grooves 52 are provided on the outer peripheral surface 50 c of the insulating sleeve 50 , the filling rate of the adhesive in the gap between the insulating sleeve 50 and the substrate through hole 34 is easily increased compared to the case where only one outer peripheral groove 52 is provided. Furthermore, since the number of the outer peripheral grooves 52 is two, the insulating sleeve 50 can be manufactured relatively easily compared to a case where the number of the outer peripheral grooves 52 is too large. In addition, the outer peripheral groove 52 is not provided at the lower end portion 58 of the insulating sleeve 50. Even if the lower end portion 58 of the insulating sleeve 50 does not have the outer peripheral groove 52, it is easy to fill the adhesive between the lower end portion 58 and the substrate through hole 34. Therefore, even if the outer peripheral groove 52 is omitted from the lower end portion 58, the adhesion between the insulating sleeve 50 and the substrate through hole 34 can be maintained. It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented in various forms as long as they fall within the technical scope of the present invention. In the above-mentioned embodiment, the insulating sleeve 50 having two outer peripheral grooves 52 is exemplified, but the present invention is not particularly limited to this. Figure 6 As shown in the figure, the outer peripheral surface 50c is provided with an annular outer peripheral groove 52, which can also be Figure 7 As shown in the figure, the outer peripheral surface 50c has three annular outer peripheral grooves 52, and can also be as follows Figure 8 As shown, four annular outer peripheral grooves 52 are provided on the outer peripheral surface 50c. Figure 6 to Figure 8In the embodiment, the same symbols are used for the same components as those in the above embodiment. Even so, the same effects as those in the above embodiment are obtained. It should be noted that there is a tendency that the greater the number of peripheral grooves 52, the higher the filling rate of the adhesive filled in the gap between the insulating sleeve 50 and the substrate through hole 34. In addition, there is a tendency that, when the number of peripheral grooves 52 is the same, the deeper the depth of the peripheral grooves 52, the higher the filling rate of the adhesive filled in the gap between the insulating sleeve 50 and the substrate through hole 34. In the above-mentioned embodiment, the outer peripheral groove 52 of an annular shape is provided on the outer peripheral surface 50c of the insulating sleeve 50, but a spiral outer peripheral groove may be provided. The spiral outer peripheral groove may be provided in the area other than the upper end 56 and the lower end 58 of the outer peripheral surface 50c of the insulating sleeve 50. Even so, the effect substantially the same as that of the above-mentioned embodiment is obtained. In the above-mentioned embodiment, as a method for manufacturing the wafer stage 10, the insulating sleeve 50 is bonded to the substrate through hole 34 of the substrate 30, and then the substrate 30 is bonded to the ceramic plate 20, but the present invention is not particularly limited thereto. For example, the insulating sleeve 50 may be bonded to the substrate through hole 34 of the substrate 30 after the substrate 30 is bonded to the ceramic plate 20. In the above-mentioned embodiment, a resin adhesive layer is exemplified as the bonding layer 40, but the present invention is not particularly limited thereto. For example, a metal bonding layer may be used as the bonding layer 40. The metal bonding layer may be formed using a metal bonding material (e.g., an Al-Mg bonding material, an Al-Si-Mg bonding material) using the well-known TCB (Thermal compression bonding). In the above-mentioned embodiment, the electrostatic electrode 22 and the heater electrode 23 are built into the ceramic plate 20, but the present invention is not particularly limited thereto. For example, only one of the electrostatic electrode 22 and the heater electrode 23 may be built into the ceramic plate 20. Alternatively, the heater electrode 23 may be built into the ceramic plate 20 in two or more layers in the thickness direction. In the above-mentioned embodiment, the ceramic plate through hole 24, the bonding layer through hole 44 and the sleeve through hole 54 are used as the gas hole 70, but it is not particularly limited to this. For example, the ceramic plate through hole 24, the bonding layer through hole 44 and the sleeve through hole 54 can be used as lift pin holes. The lift pin hole is a hole for inserting a lift pin that moves the wafer W up and down relative to the wafer placement surface 21. When the wafer W is supported by, for example, three lift pins, the lift pin holes are provided at three locations. Industrial Applicability The semiconductor manufacturing apparatus component of the present invention can be used in the field of processing a wafer using plasma or the like, for example. Explanation of symbols 10 wafer placing table, 20 ceramic plate, 21 wafer placing surface, 21a sealing tape, 21b small circular protrusion, 21c reference surface, 22 electrostatic electrode, 23 heater electrode, 24 ceramic plate through hole, 30 substrate, 32 refrigerant flow path, 34 substrate through hole, 40 bonding layer, 44 bonding layer through hole, 50 insulating sleeve, 50a upper end surface, 50b lower end surface, 50c outer peripheral surface, 52 outer peripheral groove, 54 sleeve through hole, 56 upper end portion, 58 lower end portion, 60 adhesive layer, 65 adhesive, 70 gas hole, 80 bonding sheet, 84 sheet through hole.

Claims

1. A component for a semiconductor manufacturing device, comprising: A ceramic plate having a wafer placement surface on an upper surface and having electrodes built therein; A ceramic plate through hole, the ceramic plate through hole penetrating the ceramic plate in an up-down direction; A conductive substrate disposed on the lower surface of the ceramic plate; A substrate through hole, the substrate through hole passes through the substrate in a vertical direction; an insulating sleeve, the insulating sleeve being inserted into the substrate through hole, the outer peripheral surface of the insulating sleeve being bonded to the inner peripheral surface of the substrate through hole by means of an adhesive layer; and a sleeve through hole, the sleeve through hole penetrating the insulating sleeve in the up-down direction and communicating with the ceramic plate through hole, The semiconductor manufacturing device component is characterized in that: The insulating sleeve has at least one annular or spiral outer peripheral groove on the outer peripheral surface of the insulating sleeve except for the upper end portion of the insulating sleeve.

2. The semiconductor manufacturing device component according to claim 1, wherein: The outer peripheral groove is an annular groove, and a plurality of the outer peripheral grooves are provided on the outer peripheral surface of the insulating sleeve.

3. The semiconductor manufacturing device component according to claim 2, wherein: The number of the outer peripheral grooves is 2 or more and 4 or less.

4. The semiconductor manufacturing equipment component according to any one of claims 1 to 3, wherein: The outer peripheral groove is not provided at the lower end portion of the insulating sleeve.

5. The semiconductor manufacturing device component according to claim 4, wherein: The lower end portion of the insulating sleeve is a region from the lower end surface of the insulating sleeve to a predetermined height, and the predetermined height is greater than or equal to 1 / 3 and less than or equal to 1 / 2 of the height of the insulating sleeve.

6. The semiconductor manufacturing equipment component according to any one of claims 1 to 3, characterized in that: The upper end portion of the insulating sleeve is a region from the upper end surface of the insulating sleeve to a predetermined length, and the predetermined length is greater than or equal to 1 mm and less than or equal to 3 mm.

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