Light detection device

Abstract

A light detection device includes: a substrate including a light detection element; the chip is arranged on the substrate; the embedded layer is arranged to cover the chip; a seam part which appears in the embedded layer and extends to the front surface of the embedded layer; and a sealing layer provided so as to cover the embedded layer and the seam portion.

Description

Technical Field

[0001] The present disclosure relates to a light detection device. Background Art

[0002] As is known to all, due to the step on the substrate, a seam may appear in a layer provided to cover the substrate. For example, Patent Document 1 discloses a technique for preventing the seam from being connected to the outside by forming the seam between two stacked layers in a discontinuous manner. Citation list Patent Literature

[0003] Patent Document 1: International Publication WO 2017 / 183390 Summary of the invention Technical Problems to be Solved by the Invention

[0004] There is a light detection device having the following structure: wherein a layer is provided on a substrate including a light detection element so as to cover a chip provided on the substrate. A step formed by the chip causes a seam portion to appear. There is still room for research on a method for suppressing the seam portion from being connected to the outside.

[0005] One aspect of the present disclosure is to suppress communication of a seam portion with the outside. Technical solutions to technical problems

[0006] According to one aspect of the present disclosure, a light detecting device includes: a substrate, which includes a light detecting element; a chip, which is arranged on the substrate; a buried layer, which is arranged to cover the chip; a seam portion, which appears in the buried layer and extends to the front side of the buried layer; and a sealing layer, which is arranged to cover the buried layer and the seam portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram showing an example of a schematic configuration of a light detecting device according to the first embodiment. Figure 2 is a diagram showing an example of a schematic configuration of a light detecting device according to the second embodiment. Figure 3 is a diagram showing an example of a schematic configuration of a light detecting device according to a fourth embodiment. Figure 4 is a diagram showing an example of a schematic configuration of a light detecting device according to a fifth embodiment. Figure 5 is a diagram showing an example of a schematic configuration of a photodetecting device according to a sixth embodiment. Figure 6is a diagram showing an example of a schematic configuration of a photodetecting device according to a sixth embodiment. Figure 7 is a diagram showing an example of a schematic configuration of a light detecting device according to a seventh embodiment. Figure 8 is a diagram showing an example of a schematic configuration of a light detecting device according to an eighth embodiment. Fig. 9 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.10 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.11 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.12 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.13 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.14 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.15 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.16 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.17 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.18 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.19 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig. 20 1 is a diagram showing an example of a schematic configuration of a photodetection device according to an application example. Fig.21 1 is a diagram showing an example of a schematic configuration of a photodetection device according to an application example. Fig. 22 1 is a diagram showing an example of a schematic configuration of a photodetection device according to an application example. Fig.23 1 is a diagram showing an example of a schematic configuration of a photodetection device according to an application example. Fig.24 is a block diagram illustrating an example of a schematic configuration of a vehicle control system. Fig.25 It is a diagram for auxiliary explanation of an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. Fig.26 is a diagram showing an example of a schematic configuration of a photodetecting device according to a ninth embodiment. Fig. 27 is a diagram showing an example of a schematic configuration of a photodetecting device according to a ninth embodiment. Fig.28 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.29 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.30 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.31 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.32 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.33 It is a diagram showing a modified example. Fig.34 It is a diagram showing a modified example. Fig.35 is a diagram showing an example of a schematic configuration of a photodetecting device according to a tenth embodiment. Fig.36 is a diagram showing an example of a schematic configuration of a photodetecting device according to a tenth embodiment. Fig.37 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.38 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.39 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.40 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.41 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.42 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.43 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.44 It is a diagram showing a modified example. Fig.45 is a diagram showing an example of a schematic configuration of a light detecting device according to an eleventh embodiment. Fig.46 is a diagram showing an example of a schematic configuration of a light detecting device according to an eleventh embodiment. Fig.47 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.481 is a diagram showing an example of a method for manufacturing a light detection device. Fig.49 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.50 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.51 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.52 It is a diagram showing an example of a schematic structure of a sealing layer. Fig.53 is a diagram showing an example of a schematic configuration of a light detecting device according to a thirteenth embodiment. Fig.54 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.55 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.56 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.57 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.58 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.59 is a diagram showing an example of a schematic configuration of a light detecting device according to a fourteenth embodiment. Fig.60 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.61 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.62 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.63 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.64 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.65 is a diagram showing an example of a schematic configuration of a light detecting device according to a fifteenth embodiment. Fig.66 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.67 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.68 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.69 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.70 is a diagram showing a first arrangement example of dummy chips. Fig.71 is a diagram showing a first arrangement example of dummy chips. Fig.72 This is a diagram showing the effect of a dummy chip. Fig.73 2 is a diagram showing an example of a schematic structure of a wafer. Fig.74 is a diagram showing a second arrangement example of dummy chips. Fig.75 This is a diagram showing the effect of a dummy chip. Fig.76 2 is a diagram showing an example of a schematic structure of a wafer. Fig.77 is a diagram showing a third arrangement example of dummy chips. Fig.78 This is a diagram showing the effect of a dummy chip. Fig.79 2 is a diagram showing an example of a schematic structure of a wafer. Fig.80 is a diagram showing a fourth arrangement example of dummy chips. Fig.81 This is a diagram showing the effect of a dummy chip. Fig.82 2 is a diagram showing an example of a schematic structure of a wafer. Fig.83 is a diagram showing a fifth arrangement example of dummy chips. Fig.84 This is a diagram showing the effect of the dummy chip 2D. Fig.85 2 is a diagram showing an example of a schematic structure of a wafer. Fig.86 2 is a diagram showing an example of a schematic structure of a wafer. Fig.87 This is a diagram showing the effect of a dummy chip. Fig.88 2 is a diagram showing an example of a schematic structure of a wafer. Fig.89 is a diagram showing a seventh arrangement example of the dummy chips. Fig.90 This is a diagram showing the effect of a dummy chip. Fig.91 2 is a diagram showing an example of a schematic structure of a wafer. Fig.92 It is a diagram showing a modified example. Fig.93 It is a diagram showing a modified example. Fig.94 is a diagram showing an example of a schematic configuration of a photodetecting device according to a sixteenth embodiment. Fig.95 is a diagram showing an example of a schematic configuration of a light detecting device according to a seventeenth embodiment. Fig.96 is a diagram showing an example of a schematic configuration of a light detecting device according to an eighteenth embodiment. Fig.97 is a diagram showing an example of a schematic configuration of a light detecting device according to a nineteenth embodiment. Fig.98 is a diagram showing an example of a schematic configuration of a light detecting device according to a twentieth embodiment. Fig.99 is a diagram showing an example of a schematic configuration of a light detecting device according to a twenty-first embodiment. Fig.100 is a diagram showing an example of a schematic configuration of a light detecting device according to a twenty-second embodiment. Fig.101 is a diagram showing an example of a schematic configuration of a light detecting device according to the twenty-third embodiment. Fig.102 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.103 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.104 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.105 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.106 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.107 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.108 is a diagram showing an example of a schematic configuration of a light detecting device according to a twenty-fourth embodiment. Fig.109 is a diagram showing an example of a schematic configuration of a light detecting device according to a twenty-fourth embodiment. Fig.110 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.111 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.112 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.113 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.114 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.115 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.116 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.117 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.118 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.119 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.120 is a diagram showing an example of CMP. Fig.121 is a diagram showing an example of CMP. Fig.122 is a diagram showing an example of a schematic configuration of a light detecting device according to the twenty-fifth embodiment. Fig.123 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.124 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.125 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.126 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.127 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.128 1 is a diagram showing an example of a method for manufacturing a light detection device. DETAILED DESCRIPTION

[0008] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In addition, unless otherwise specified, in the following embodiments, the same constituent elements are represented by the same reference numerals, and their repeated description will be omitted.

[0009] The present disclosure will be described in the following order. 1. First Implementation Method 2. Second Implementation Method 3. Third Implementation Method 4. Fourth Implementation Method 5. Fifth Implementation Method 6. Sixth Implementation Method 7. Seventh Implementation Plan 8. Eighth Implementation Plan 9. Examples of manufacturing methods 10. Application examples of imaging devices 11. Examples of effects 12. Application examples for mobile objects 13. Ninth Implementation Plan 14. Tenth Implementation Plan 15. Eleventh Implementation Plan 16. Twelfth Implementation Plan 17. Thirteenth Implementation Plan 18. Fourteenth Implementation Plan 19. Fifteenth Implementation Plan 20. Example of dummy chip layout 21. Sixteenth Implementation Plan 22. Seventeenth Implementation Plan 23. Eighteenth Implementation Plan 24. Nineteenth Implementation Plan 25. Twentieth Implementation Plan 26. Twenty-first Implementation Plan 27. Implementation Plan 22 28. Twenty-third Implementation Plan 29. Application examples of camera devices 30. Example of manufacturing method 31. Twenty-fourth Implementation Plan 32. Twenty-fifth Implementation Plan

[0010] 1. First Implementation Method Figure 1 1 is a diagram showing an example of a schematic configuration of a light detecting device according to the first embodiment. The figure schematically shows a cross section of a light detecting device 100. The light detecting device 100 includes a substrate 1, a chip 2, a buried layer 3, a joint portion 4, a sealing layer 5, an auxiliary layer 6, and a supporting substrate 7. Note that, within the scope of no contradiction, "layer" can be appropriately replaced with terms such as "film", "component", etc. In addition, "setting" can be appropriately understood as "forming", "arranging", etc.

[0011] In the accompanying drawings, an XYZ coordinate system is also shown. The Z-axis direction is equivalent to the thickness direction of the substrate or layer. The X-axis direction and the Y-axis direction (XY plane direction) are equivalent to the plane direction of the substrate or layer. The substrate 1 and the supporting substrate 7 face each other. In this example, of the substrate 1 and the supporting substrate 7, the substrate 1 is located on the negative direction side of the Z axis, and the supporting substrate 7 is located on the positive direction side of the Z axis. The chip 2, the embedded layer 3, the seam portion 4, the sealing layer 5 and the auxiliary layer 6 are located between the substrate 1 and the supporting substrate 7.

[0012] The light detection device 100 includes a wiring layer. In the drawings, the wirings provided in the wiring layer are all illustrated as wirings L. Examples of the material of the wirings L are copper (Cu) and the like. Some vias (VIAs (vertical interconnects)) for connecting the wirings L of different wiring layers to each other are also shown with the same hatching as the wirings L.

[0013] For example, the substrate 1 is a semiconductor substrate such as a silicon (Si) semiconductor substrate, and includes a light detecting element 1p. An example of a light detecting element is a photoelectric conversion element such as a photodiode (PD: photo diode). For example, a plurality of photoelectric conversion elements arranged in an array in the XY plane direction may be equivalent to the light detecting element 1p. Although not shown in the figure, the substrate 1 also includes circuit elements such as transistors for driving each photoelectric conversion element and taking out an electrical signal corresponding to the amount of light received by each photoelectric conversion element. A circuit including such a circuit element is also referred to as a pixel circuit.

[0014] Among the surfaces of the substrate 1, the surface on the positive Z-axis side is referred to as the front surface 1a and is shown in the figure. The surface on the negative Z-axis side is referred to as the back surface 1b and is shown in the figure. The illustrated light detection device 100 is a back-illuminated light detection device that detects light incident on the back surface 1b of the substrate 1.

[0015] The substrate 1 has a wiring layer on the front surface 1a side. The wiring L of the wiring layer of the substrate 1 can constitute a part of the pixel circuit. The wiring layer of the illustrated substrate 1 is a multilayer wiring layer, and some of the wiring L is exposed on the front surface 1a.

[0016] The chip 2 is disposed on the substrate 1. The meaning of "disposed on the substrate 1" can be understood to include not only being disposed directly on the substrate 1, but also being disposed via another component (for example, the chip 2 described later). Fig.21 The additional substrate 12 is arranged on the substrate 1. Figure 1 In the example shown, the chip 2 is directly arranged on the substrate 1, more specifically, on the front surface 1a of the substrate 1. The mounting surface of the chip 2 is referred to and illustrated as the mounting surface 2b. The chip 2 has a wiring layer on the mounting surface 2b side. The wiring layer of the illustrated chip 2 is a multi-layer wiring layer, and some wiring L is exposed on the mounting surface 2b.

[0017] The chip 2 is arranged on the substrate 1 in such a manner that the mounting surface 2b of the chip 2 is in contact with the front surface 1a of the substrate 1. More specifically, the chip 2 is mounted on the substrate 1 in such a manner that the wiring L of the chip 2 and the wiring L of the substrate 1 are in contact with each other and electrically connected. When the material of the wiring L is Cu, this type of connection is also called Cu-Cu bonding, etc. The mounting surface 2b of the chip 2 and the front surface 1a of the substrate 1 define the bonding surface (chip bonding surface) between the chip 2 and the substrate 1.

[0018] The chip 2 may be any chip (such as an IC (integrated circuit) or the like) that can be applied to the light detection device 100. For example, one example of the chip 2 is a logic chip that drives the transistors of the pixel circuit or processes the electrical signals taken out of the pixel circuit. For example, another example of the chip 2 is a memory chip that stores data to be used in the processing of the logic chip and data obtained by the processing. Yet another example of the chip 2 is an AI (artificial intelligence) chip that is dedicated to performing high-speed computing processing by using a training model (e.g., a training DNN (deep neural network)).

[0019] from Figure 1 It can be understood that the chip 2 disposed on the substrate 1 provides a step. In this example, the chip 2 is a step portion having a convex shape protruding toward the positive direction of the Z axis with the front surface 1a of the substrate 1 as a reference. Note that the number of chips 2 included in the light detection device 100 is not limited to Figure 1 The light detection device 100 may include one or more chips 2 of any desired number.

[0020] The buried layer 3 is configured to cover the chip 2, and more specifically, in this example, is configured to cover the substrate 1 and the chip 2. The buried layer 3 can function as a protective layer for protecting the chip 2. For example, the layer can inhibit the intrusion of moisture, chemicals, undesirable gases, etc. into the chip 2. Examples of materials for the buried layer 3 include SiN, SiO2, etc. Among the surfaces of the buried layer 3, the surface on the positive direction side of the Z axis is referred to as and illustrated as the front side 3a. The surface on the negative direction side of the Z axis is referred to as and illustrated as the back side 3b.

[0021] Because of the step provided by the chip 2, a joint portion 4 appears in the buried layer 3. For example, the joint portion 4 extends to the front surface 3a of the buried layer 3 starting from the rising portion of the step or the peripheral portion of the step.

[0022] At least a portion of the joint portion 4 may be a gap. The gap in the joint portion 4 is referred to and illustrated as a gap 4a. Figure 1 In the example shown, the entire joint portion 4 is formed as a gap 4a. In the front surface 3a of the embedding layer 3, the portion where the joint portion 4 is located is open.

[0023] The sealing layer 5 is provided to cover the embedded layer 3 and the joint portion 4. The opening formed by the joint portion 4 on the front surface 3a of the embedded layer 3 is also blocked by the sealing layer 5. The sealing layer 5 suppresses the connection between the joint portion 4 and the outside. The material of the sealing layer 5 may be the same as or different from that of the embedded layer 3. Some examples of the material of the sealing layer 5 will be described later.

[0024] The auxiliary layer 6 is provided to cover the sealing layer 5. For example, the auxiliary layer 6 includes a material suitable for bonding with the supporting substrate 7. Examples of the material of the auxiliary layer 6 are mainly SiOx (including SiNx, SiON, SiCN and SiOC). Among the surfaces of the auxiliary layer 6, the surface on the positive direction side of the Z axis is referred to and illustrated as the front side 6a.

[0025] The support substrate 7 is located on the side opposite to the substrate 1 via the sealing layer 5, and directly or indirectly supports the sealing layer 5. For example, the support substrate 7 may be a silicon (Si) semiconductor substrate or the like. Figure 1 In the example shown, the supporting substrate 7 is located on the side opposite to the substrate 1 via the sealing layer 5 and the auxiliary layer 6, and is bonded to the auxiliary layer 6, thereby supporting the sealing layer 5 via the auxiliary layer 6 (i.e., indirectly supporting the sealing layer 5). Among the surfaces of the supporting substrate 7, the surface on the positive direction side of the Z axis is referred to as and illustrated as the front side 7a. The surface on the negative direction side of the Z axis is referred to as and illustrated as the back side 7b. The back side 7b of the supporting substrate 7 and the front side 6a of the auxiliary layer 6 define the bonding surface (support substrate bonding surface) between the supporting substrate 7 and the auxiliary layer 6. Incidentally, the light detecting device 100 may also not include the auxiliary layer 6. In this case, the supporting substrate 7 is bonded to the sealing layer 5, thereby directly supporting the sealing layer 5.

[0026] According to the above-mentioned light detection device 100, since the sealing layer 5 covering the embedding layer 3 and the joint portion 4 is provided, the connection between the joint portion 4 and the outside can be suppressed. Figure 1 In the example shown, the joint portion 4 can be prevented from reaching the front surface 6a of the auxiliary layer 6, which is the bonding surface of the auxiliary layer 6 and the support substrate 7. If the joint portion 4 reaches the front surface 6a of the auxiliary layer 6, an opening will be formed in the bonding surface of the auxiliary layer 6 and the support substrate 7, and there is a possibility that the bonding quality will be reduced due to the occurrence of vacancies, etc. The light detection device 100 suppresses such a reduction in bonding quality.

[0027] Some other embodiments based on the above technology will be described below. Within the scope of no contradiction, the technical features of each embodiment can be appropriately combined.

[0028] 2. Second Implementation Method Figure 21 is a diagram showing an example of a schematic configuration of a light detecting device according to the second embodiment. The sealing layer 5 includes an extending portion 5a extending into the joint portion 4. The extending portion 5a extends to fill at least a portion of the joint portion 4. Figure 2 In the example shown, the extension portion 5a extends to fill the entire joint portion 4. The joint portion 4 does not have a gap 4a ( Figure 1 ). The material of the sealing layer 5 (the material of the extension 5a) includes a low-permeability material. Examples of low-permeability materials include SiN-based materials. Examples of SiN-based materials include SiNx, SiCN, SiON, etc. For example, since the extension 5a of the sealing layer 5 described above fills the joint 4, the effect of suppressing the intrusion of moisture, etc. into the chip 2 is enhanced. This also leads to an improvement in reliability, etc.

[0029] 3. Third Implementation Method In one embodiment, the material of the sealing layer 5 includes a low Young's modulus material. Examples of low Young's modulus materials include low-k (low dielectric constant) materials, organic materials, etc. Examples of low-k materials include porous SiO2, etc. Examples of organic materials include silicone, siloxane, polyimide, etc. For example, by filling the seam portion 4 with the extension portion 5a of the sealing layer 5 described above, the stress between the chips can be relieved.

[0030] 4. Fourth Implementation Method Figure 3 4 is a diagram showing an example of a schematic configuration of a light detecting device according to a fourth embodiment. The extending portion 5a of the sealing layer 5 extends to fill only a portion of the joint portion 4. The remaining portion of the joint portion 4 is a gap 4a. By leaving the gap 4a, stress between the chips can also be relieved.

[0031] Hereinafter, unless otherwise specified, description will be given of a case where the extended portion 5 a of the sealing layer 5 extends to fill the entire joint portion 4 .

[0032] 5. Fifth Implementation Method Figure 4 1 is a diagram showing an example of a schematic configuration of a light detecting device according to the fifth embodiment. The light detecting device 100 also includes a side wall portion 8. The side wall portion 8 is configured to cover the side (side wall) of the chip 2. The buried layer 3 is configured to cover the substrate 1, the chip 2 and the side wall portion 8. Examples of the material of the side wall portion 8 are inorganic materials and the like. Examples of inorganic materials are mainly SiNx (including SiOx, SiON, SiCN and SiOC). Due to the presence of the side wall portion 8, the protectability of the chip 2 can be further improved.

[0033] 6. Sixth Implementation Method Figure 5 and Figure 6 1 is a diagram showing an example of a schematic configuration of a light detecting device according to the sixth embodiment. Seams 4 that appear due to two different chips 2 are connected to each other. Among the two chips 2, the first chip is referred to and illustrated as chip 2-1. The second chip is referred to and illustrated as chip 2-2.

[0034] The seam 4 includes a seam 4-1 and a seam 4-2. The seam 4-1 is a first seam that occurs due to the chip 2-1. The seam 4-2 is a second seam that occurs due to the chip 2-2. Figure 5 In the example shown, the joint portion 4-1 and the joint portion 4-2 are connected to each other on the way to the front surface 3a of the buried layer 3, and extend to the front surface 3a of the buried layer 3. Figure 6 In the example shown, the step provided by the seam portion 4-1 and the seam portion 4-2 are connected to each other from the beginning and extend together to the front surface 3a of the embedded layer 3. For example, even if there are the seam portion 4-1 and the seam portion 4-2 connected to each other in this way, the communication between the seam portion 4-1 and the seam portion 4-2 and the outside can be suppressed.

[0035] 7. Seventh Implementation Plan Figure 7 1 is a diagram showing an example of a schematic construction of an optical detection device according to the seventh embodiment. The optical detection device 100 also includes an additional layer 9. The additional layer 9 is arranged between the substrate 1 and the chip 2 and the buried layer 3. In other words, the additional layer 9 is arranged to cover the substrate 1 and the chip 2, and the buried layer 3 is arranged to cover the additional layer 9. The material of the additional layer 9 may be the same as or different from the material of the buried layer 3. Examples of the material of the additional layer 9 are mainly SiNx (including SiOx, SiON, SiCN and SiOC). The additional layer 9 may have a single-layer structure or a stacked structure. Due to the presence of the additional layer 9, the reliability can be further improved.

[0036] 8. Eighth Implementation Plan Figure 8 : is a diagram showing an example of a schematic structure of a light detection device according to the eighth embodiment. The auxiliary layer 6 has a stacked structure. In this example, the auxiliary layer 6 has a three-layer structure and includes layer 61, layer 62, and layer 63 in sequence in the positive direction of the Z axis. The materials of each of layer 61, layer 62, and layer 63 can be different materials from each other or the same material. Through various designs of the number of layers and materials, it is possible to perform warpage adjustment, expansion of bonding margin, etc.

[0037] 9. Examples of manufacturing methods Figures 9 to 19 1 is a diagram showing an example of a method for manufacturing a light detection device. Figures 9 to 14The light detection device 100 ( Figures 1 to 3 and Figures 5 to 8 ) is an example of a method for manufacturing the same.

[0038] like Fig. 9 As shown in FIG. 1 , a substrate 1 including a light detecting element 1p is prepared, and a chip 2 is provided on the substrate 1. Fig.10 As shown, the embedding layer 3 is provided to cover the substrate 1 and the chip 2. Due to the step formed by the chip 2, a joint portion 4 appears in the embedding layer 3. At this time, the entire joint portion 4 is a gap 4a.

[0039] As in the sixth embodiment ( Figure 5 and Figure 6 ), the joints 4 corresponding to the adjacent chips 2 can also be connected to each other. Figure 7 ), the additional layer 9 is provided to cover the substrate 1 and the chip 2 ( Figure 7 ), after which the buried layer 3 is arranged to cover the additional layer 9.

[0040] By grinding and cleaning the top of the buried layer 3 (the portion on the positive direction side of the Z axis), Fig.11 As shown in FIG. 1 , a flat front surface 3a is obtained. The portion where the seam 4 reaches on the front surface 3a is open. In this state, as shown in FIG. Fig.12 As shown, the sealing layer 5 is provided to cover the embedding layer 3. The opening on the front surface 3a is closed by the sealing layer 5.

[0041] In the above first embodiment ( Figure 1 ), the entire joint portion 4 is maintained as a gap 4a. In the above-mentioned second embodiment and third embodiment ( Figure 2 ), the entire joint portion 4 is filled with the material of the sealing layer 5, and the filled portion becomes the extension 5a of the sealing layer 5. Figure 3 ), only a portion of the joint portion 4 is filled with the material of the sealing layer 5, and the filled portion becomes the extension 5a of the sealing layer 5. Figures 5 to 8 ), any mode can be used.

[0042] like Fig.13 As shown, the auxiliary layer 6 is provided to cover the sealing layer 5. Thereafter, the auxiliary layer 6 is ground and cleaned. Since the joint portion 4 is covered by the sealing layer 5, the joint portion 4 will not expand even if it is cleaned. Figure 8 ), the auxiliary layer 6 is provided with a plurality of layers (eg, layer 61, layer 62, and layer 63) so as to allow the auxiliary layer 6 to have a stacked structure. Fig.14As shown, the support substrate 7 is attached to the auxiliary layer 6 .

[0043] For example, using the above-described method, the light detecting device 100 according to the first to fourth embodiments and the sixth to eighth embodiments described above can be manufactured.

[0044] Figures 15 to 19 According to the fifth embodiment described above ( Figure 4 ) is an example of a manufacturing method of the present invention. The preparation of the substrate 1 and the placement of the chip 2 on the substrate 1 are similar to those described above. Fig. 9 The process is the same. Fig.15 As shown, the side wall portion 8 ( Figure 4 ) is provided to cover the substrate 1 and the chip 2.

[0045] like Fig.16 As shown in FIG. 1 , etching (eg, dry etching) is performed so that the above-mentioned material remains on the side surface of the chip 2. The material remaining on the side surface of the chip 2 forms the side wall portion 8. Fig.17 As shown, the buried layer 3 is provided to cover the substrate 1, the chip 2 and the side wall portion 8. Due to the step formed by the chip 2, a joint portion 4 appears in the buried layer 3. Fig.18 As shown, the auxiliary layer 6 is arranged to cover the sealing layer 5. Fig.19 As shown, the support substrate 7 is attached to the auxiliary layer 6 .

[0046] For example, using the above-described method, the light detecting device 100 according to the fifth embodiment described above can be manufactured.

[0047] 10. Application examples of imaging devices An example of application of the aforementioned light detection device 100 is an imaging device. Figure 20 to Figure 23 to explain.

[0048] Fig. 20 1 is a diagram showing an example of a schematic configuration of a light detection device according to an application example. Note that the direction of the Z axis is opposite to the direction of the Z axis in the previous figures. The illustrated light detection device 100 is an imaging device configured to include a plurality of pixels 101. Examples of the pixels 101 include a pixel G that receives green light, a pixel R that receives red light, and a pixel B that receives blue light. The substrate 1 is a substrate (image sensor substrate) configured to include photoelectric conversion elements corresponding to the respective pixels 101. The light detection device 100 includes a filter layer 10 and a lens layer 11.

[0049] The filter layer 10 is arranged on a side opposite to the chip 2 and the buried layer 3 across the substrate 1. In the present example, the filter layer 10 is arranged on the back side 1b of the substrate 1. The filter layer 10 includes a plurality of filters corresponding to the plurality of pixels 101, respectively. The filter arranged on the pixel G is referred to as and illustrated as filter 10G. The filter arranged on the pixel R is referred to as and illustrated as filter 10R. The filter arranged on the pixel B is referred to as and illustrated as filter 10B. Filter 10G allows green light to pass through. Filter 10R allows red light to pass through. Filter 10B allows blue light to pass through. The filter can use various known materials such as resin.

[0050] The lens layer 11 is provided on the side opposite to the substrate 1 via the filter layer 10. The lens layer 11 includes a plurality of lenses 11a corresponding to the plurality of pixels 101. The lens 11a is a condenser lens that can condense light so that the light is incident on the photoelectric conversion element of the substrate 1 via the filter layer 10. The lens can use various known materials such as resin.

[0051] For example, the light detection device 100 having the above-described configuration may be used as an imaging device. Other configurations may also be used for the light detection device, and reference will be made to the above configurations. Figure 21 to Figure 23 Let's illustrate with some examples.

[0052] Fig.21 1 is a diagram showing an example of a schematic structure of a light detecting device according to an application example. The light detecting device 100 also includes an additional substrate 12. The additional substrate 12 is arranged between the substrate 1 and the buried layer 3. The additional substrate 12 can also be considered as an intermediate substrate located between the substrate 1 and the supporting substrate 7. Among the surfaces of the additional substrate 12, the surface on the positive direction side of the Z axis is referred to as and illustrated as the front side 12a. The surface on the negative direction side of the Z axis is referred to as and illustrated as the back side 12b. The front side 12a of the additional substrate 12 is in contact with the back side 3b of the buried layer 3, and the back side 12b of the additional substrate 12 is in contact with the front side 1a of the substrate 1.

[0053] The additional substrate 12 has wiring layers on the front surface 12a side and the back surface 12b side, respectively. The wiring layers of the additional substrate 12 illustrated are each a multi-layer wiring layer, and some wirings L are exposed on the front surface 12a or the back surface 12b.

[0054] The chip 2 is provided on the additional substrate 12, and the mounting surface 2b of the chip 2 is in contact with the front surface 12a of the additional substrate 12. More specifically, the chip 2 is mounted on the additional substrate 12 in such a manner that the wiring L of the chip 2 and the wiring L of the additional substrate 12 are in contact with each other and electrically connected. The mounting surface 2b of the chip 2 and the front surface 12a of the additional substrate 12 define a bonding surface (chip bonding surface) between the chip 2 and the additional substrate 12.

[0055] The additional substrate 12 is attached to the substrate 1 in such a manner that the wiring L of the additional substrate 12 and the wiring L of the substrate 1 are in contact with each other and electrically connected. The front surface 1a of the substrate 1 and the back surface 12b of the additional substrate 12 define the bonding surface (F2F (face-to-face) bonding surface) between the substrate 1 and the additional substrate 12.

[0056] The additional substrate 12 includes a penetrating via 12v. The penetrating via 12v penetrates a portion (base portion) between a wiring layer on the front side 12a of the additional substrate 12 and a wiring layer on the back side 12b of the additional substrate 12 so as to connect the two wiring layers. Since the wiring layer of the additional substrate 12 is also utilized, more wiring and circuit elements can be formed. This can further lead to an enhanced function of the light detection device 100. Note that the number of additional substrates 12 to be provided may also be two or more.

[0057] Fig. 22 and Fig.23 FIG. 1 is a diagram showing an example of a schematic structure of a light detection device according to an application example. Fig. 22 As shown, wiring L and a structure are provided between the chips 2 arranged adjacent to each other with a space therebetween. An example of the structure is a through via V.

[0058] Specifically, Fig. 22 As shown, the buried layer 3 and the auxiliary layer 6 also include wiring L. Some wiring L is provided between adjacent chips 2. By also providing wiring L in the buried layer 3 and the auxiliary layer 6, the function of the light detection device 100 can be further enhanced. The wiring L can also be provided on the seam portion 4, thereby correspondingly improving the degree of freedom of layout.

[0059] The through-via V can penetrate the buried layer 3, the sealing layer 5, the auxiliary layer 6 and the supporting substrate 7. The through-via V can be used to provide electrical access from the front side 7a of the supporting substrate 7 to the wiring layer on the front side 12a of the additional substrate 12. The through-via V can also be called a contact via. In the buried layer 3, at least some of the through-vias V are located between the chips 2 adjacent to each other. In addition, the through-via V can also penetrate the seam 4. Specifically, Fig.23 In the plan view (when viewed along the Z-axis direction), some of the plurality of through vias V arranged around the chip 2 overlap with the seam portion 4. The through vias V can be provided at various positions, thereby increasing the degree of freedom of layout accordingly.

[0060] 11. Examples of effects For example, the above-described technology is specifically described as follows. One of the disclosed technologies is a light detection device 100. Figure 1 As described in the figures, the light detection device 100 includes: a substrate 1, which includes a light detection element 1p; a chip 2, which is arranged on the substrate 1; a buried layer 3, which is arranged to cover the chip 2; a joint portion 4, which appears in the buried layer 3 and extends to the front side 3a of the buried layer 3; and a sealing layer 5, which is arranged to cover the buried layer 3 and the joint portion 4.

[0061] According to the above-described light detection device 100 , since the sealing layer 5 is provided so as to cover the embedding layer 3 and the joint portion 4 , communication between the joint portion 4 and the outside can be suppressed.

[0062] As reference Figure 1 As described in the above, the light detection device 100 may include a support substrate 7, which is located on the side opposite to the substrate 1 via the sealing layer 5 and directly or indirectly supports the sealing layer 5. Since the joint portion 4 covered by the sealing layer 5 does not reach the bonding surface between the sealing layer and the support substrate 7, it is possible to suppress the reduction in bonding quality due to the occurrence of voids and the like.

[0063] As reference Figure 1 and Figure 3 As described in the above, at least a part of the joint 4 may be a gap 4a. For example, this can relieve stress between chips.

[0064] As reference Figure 2 and Figure 3 As described in the figures, the sealing layer 5 may include an extension 5a extending into the seam 4 to fill at least a portion of the seam 4. The material of the sealing layer 5 may include a low permeability material. This enhances the effect of suppressing the intrusion of moisture, etc. into the chip 2. The material of the sealing layer 5 may include a low Young's modulus material. For example, this can relieve stress between chips.

[0065] As reference Figure 4 As described in the above, the light detecting device 100 may include the side wall portion 8 provided so as to cover the side surface of the chip 2. This can further improve the protectability of the chip 2.

[0066] As reference Figure 5 and Figure 6 As described in the above, the chip 2 may include a chip 2-1 (first chip) and a chip 2-2 (second chip) which are arranged separately from each other, the seam portion 4 may include a seam portion 4-1 (first seam portion) which appears due to the chip 2-1 and a crack portion 4-2 (second seam portion) which appears due to the chip 2-2, and the seam portion 4-1 and the seam portion 4-2 may be connected to each other. For example, even if there are seams 4-1 and 4-2 which are connected to each other in this way, the connection between the seams 4-1 and 4-2 and the outside can be suppressed.

[0067] As reference Figure 7 As described in , the light detection device 100 may include an additional layer 9 arranged between the chip 2 and the buried layer 3. This can further improve the reliability.

[0068] As reference Figure 1 and Figure 8 As described in the above, the light detection device 100 may include an auxiliary layer 6 provided in a manner covering the sealing layer 5. This makes it easy to achieve bonding with the support substrate 7. The auxiliary layer 6 may have a stacked structure. By designing the number of layers and materials, warpage adjustment and bonding margin expansion can be performed.

[0069] As reference Figure 1 As described in , etc., the chip 2 may include at least one of a logic chip, a memory chip, and an AI (artificial intelligence) chip. For example, a light detection device having various chips 2 and having enhanced functions may be provided.

[0070] As reference Fig. 20 As described in the above, the light detection device 100 may be an imaging device configured to include a plurality of pixels 101. The light detection device 100 may include: a filter layer 10, which is disposed on a side opposite to the chip 2 and the embedding layer 3 via the substrate 1; and a lens layer 11, which is disposed on a side opposite to the substrate 1 via the filter layer 10. The light detection device 100 may be applied to an imaging device.

[0071] As reference Fig.21 As described in FIG. 1 and FIG. 2 , the light detecting device 100 may include an additional substrate 12 disposed between the substrate 1 and the buried layer 3. This leads to an enhancement in the functionality of the light detecting device 100.

[0072] As reference Fig. 22 As described in the above, the chip 2 may include two chips 2 arranged in a spaced-apart manner adjacent to each other, and the buried layer 3 may include a wiring L provided between the two chips 2. This can further achieve functional enhancement of the light detection device 100. The light detection device 100 may include a through-path V penetrating the buried layer 3, the sealing layer 5, and the support substrate 7. This can achieve access to the wiring layer on the front surface 12a side of the additional substrate 12 from the front surface 7a of the support substrate 7.

[0073] Note that the effects described in the present disclosure are only examples and are not limited to the disclosed contents. In addition, the present technology may have other effects.

[0074] 12. Application examples for mobile objects The technology described so far can be applied to various products. For example, the light detection device 100 described so far can be implemented as a device mounted on any type of mobile body such as a car, an electric car, a hybrid car, a two-wheeled motor vehicle, a bicycle, a personal mobility vehicle, an airplane, an unmanned aerial vehicle, a ship, and a robot.

[0075] Fig.24 : is a block diagram illustrating an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to the present disclosure is applicable.

[0076] The vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. Fig.24 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F: interface) 12053 are shown.

[0077] The drive system control unit 12010 controls the operation of the devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for various devices such as the following: a drive force generating device such as an internal combustion engine, a drive motor, etc. for generating a drive force for the vehicle; a drive force transmitting mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating a braking force for the vehicle.

[0078] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for various devices such as: a keyless entry system; a smart key system; a power window device; or various lights such as a headlight, a taillight, a brake light, a turn signal, a fog light, etc. In this case, a radio wave emitted from a portable device that replaces a key or a signal from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0079] The vehicle exterior information detection unit 12030 detects information on the exterior of the vehicle equipped with the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform processing for detecting objects such as people, vehicles, obstacles, signs, text on the road surface, etc. or processing for detecting the distance to the object.

[0080] The imaging unit 12031 is an optical sensor that can receive light and output an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as distance measurement information. In addition, the light received by the imaging unit 12031 can be visible light, or can be non-visible light such as infrared rays.

[0081] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's state. For example, the driver state detection unit 12041 includes a camera for photographing the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0082] Based on the information outside or inside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism or the braking device, and output the control instruction to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control for realizing the functions of ADAS (Advanced Driver Assistance System), the functions of which include collision avoidance or impact mitigation of the vehicle, following driving based on the vehicle-to-vehicle distance, vehicle constant speed driving, vehicle collision warning, vehicle lane departure warning, etc.

[0083] In addition, based on the information outside or inside the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control such as automatic driving, which enables the vehicle to drive autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc.

[0084] In addition, based on the information outside the vehicle obtained by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control instruction to the body system control unit 12020. For example, based on the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, the microcomputer 12051 can perform coordinated control such as switching the headlights from high beam to low beam to achieve anti-glare purposes.

[0085] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Fig.24 In the example shown, as output devices, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. For example, the display portion 12062 may include at least one of an onboard display and a head-up display.

[0086] Fig.25 12031 is a diagram showing an example of the installation position of the camera unit 12031.

[0087] exist Fig.25 In the figure, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0088] For example, the camera units 12101, 12102, 12103, 12104 and 12105 are respectively arranged at the positions of the front nose, side mirrors, rear bumper and trunk door of the vehicle 12100 and the upper position of the windshield in the vehicle compartment. The camera unit 12101 arranged at the front nose and the camera unit 12105 arranged at the upper part of the windshield in the vehicle compartment mainly obtain images in front of the vehicle 12100. The camera units 12102 and 12103 arranged at the side mirrors mainly obtain images on the sides of the vehicle 12100. The camera unit 12104 arranged at the rear bumper or the trunk door mainly obtains images behind the vehicle 12100. The camera unit 12105 arranged at the upper part of the windshield in the vehicle compartment is mainly used to detect vehicles in front, pedestrians, obstacles, signal lights, traffic signs, lanes, etc.

[0089] By the way, Fig.25An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the trunk door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, it is possible to obtain a bird's-eye view image of the vehicle 12100 viewed from above.

[0090] At least one of the imaging units 12101 to 12104 may have a function capable of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0091] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can obtain the distance to each solid object within the camera ranges 12111 to 12114 and the change in the distance over time (relative speed relative to the vehicle 12100), thereby extracting the following solid object as the leading vehicle: the solid object is particularly the closest solid object existing on the driving path of the vehicle 12100 and is a solid object that travels at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100. In addition, the microcomputer 12051 can set the inter-vehicle distance that should be ensured in advance with respect to the leading vehicle, and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Therefore, it is possible to perform coordinated control such as automatic driving that enables the vehicle to travel autonomously without relying on the driver's operation.

[0092] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into three-dimensional object data of two-wheeled vehicles, ordinary cars, large vehicles, pedestrians, telephone poles and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually perceive and obstacles that the driver of the vehicle 12100 is difficult to visually perceive. Then, the microcomputer 12051 determines the collision risk used to represent the degree of danger of collision with each obstacle. In the case where the collision risk is equal to or greater than the set value and there is a possibility of collision, the microcomputer 12051 issues a warning to the driver via the audio speaker 12061 or the display unit 12062, or performs forced deceleration or evasive steering via the drive system control unit 12010. Therefore, the microcomputer 12051 can provide driving assistance for avoiding collisions.

[0093] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the image captured by the camera units 12101 to 12104. For example, such identification of a pedestrian is performed by: a process of extracting feature points from the image captured by the camera units 12101 to 12104 as infrared cameras; and a process of performing pattern matching processing on a series of feature points representing the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that there is a pedestrian in the image captured by the camera units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 may control the display unit 12062 to display a square outline for emphasis in a superimposed manner on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 to display an icon or the like representing a pedestrian at a desired position.

[0094] For example, the light detection device 100 described above can be applied to the imaging unit 12031 in the above-described structure. This can further improve the reliability of a product including the light detection device 100.

[0095] Other embodiments of the light detection device 100 will be described below. Note that the disclosed techniques including the technical details described so far can be appropriately combined within the scope of no contradiction. For example, the sealing layer 5 can but does not necessarily extend into the joint portion 4. The material of the sealing layer 5 can be a low permeability material or can be a low Young's modulus material (for example, resin). The light detection device 100 can be a camera device.

[0096] 13. Ninth Implementation Plan Fig.26 and Fig. 27 1 is a diagram showing an example of a schematic configuration of a light detecting device according to a ninth embodiment. The chip 2 includes a plurality of chips 2. As the plurality of chips 2, Fig.26 Two chips 2 are illustrated in FIG. Fig. 27 Three chips 2 are illustrated in FIG. 1 . The first chip is referred to and illustrated as chip 2-1. The second chip is referred to and illustrated as chip 2-2. The third chip is referred to and illustrated as chip 2-3. Note that the chips 2-1 and 2-2 here can be the same as those in the sixth embodiment ( Figure 5 and Figure 6 )'s chip 2-1 and chip 2-2 are understood differently.

[0097] exist Fig.26 In the example shown, the chip 2-1 and the chip 2-2 have different thicknesses (heights) from each other. The thickness of the chip 2-2 is greater than the thickness of the chip 2-1. In other words, the thickness of the chip 2-1 is less than the thickness of the chip 2-2. The seam portion 4 includes a seam portion 4-1 and a seam portion 4-2. The seam portion 4-1 is a first seam portion extending from the chip 2-1 toward the front surface 3a of the buried layer 3. The seam portion 4-2 is a second seam portion extending from the chip 2-2 toward the front surface 3a of the buried layer 3.

[0098] Since the thickness of the chip 2-1 is smaller than that of the chip 2-2, the length of the joint 4-1 can be shorter than that of the joint 4-2 in their thickness directions. The joint 4-2 can extend closer to the front surface 3a of the buried layer 3 than the joint 4-1. Fig.26 In the example shown, the seam portion 4-2 reaches the front surface 3a of the buried layer 3, while the seam portion 4-1 does not reach the front surface 3a of the buried layer 3. The extension portion 5a of the sealing layer 5 may extend into the seam portion 4-2 to fill at least a portion of the seam portion 4-2. On the contrary, the seam portion 4-1 may become a gap 4a.

[0099] exist Fig. 27 In the example shown, chip 2-3 is also arranged on chip 2-2. Chip 2-2 and chip 2-3 are multiple chips 2 stacked in sequence (stacked chips). Chip 2-3 is electrically connected to chip 2-2 through wiring. The wiring also includes a through-path 2v that runs through chip 2. The overall thickness of chip 2-2 and chip 2-3 is greater than the thickness of chip 2-1. As long as this condition is met, the thickness of chip 2-2 can be the same as or different from the thickness of chip 2-1. The same applies to chip 2-3. Note that the number of chips 2 to be stacked can be three or more.

[0100] The seam 4 is similar to the one described above. Fig.26 The seam portion 4 in the embodiment of the present invention can be formed by the following steps. The seam portion 4-2 can extend closer to the front surface 3a of the buried layer 3 than the seam portion 4-1. Fig. 27 In the example shown, the seam portion 4 - 2 reaches the front surface 3 a of the buried layer 3 , whereas the seam portion 4 - 1 does not reach the front surface 3 a of the buried layer 3 .

[0101] <Example of Manufacturing Method> Figure 28 to Figure 32 1 and 2 are diagrams each showing an example of a method for manufacturing a light detecting device. Note that descriptions overlapping with the above descriptions on the manufacturing method will be appropriately omitted.

[0102] like Fig.28 As shown, the chip 2-1 and the chip 2-2 are arranged on the substrate 1. Fig.29 As shown, the embedding layer 3 is provided to cover the substrate 1, the chip 2-1 and the chip 2-2. The joint portion 4-1 and the joint portion 4-2 appear. At this time, the joint portion 4-1 and the joint portion 4-2 are both gaps.

[0103] like Fig.30 As shown, the buried layer 3 is flattened. Of the joint portion 4-1 and the joint portion 4-2, the upper portion of the joint portion 4-2 is open. Fig.31 As shown in FIG. 1 , the sealing layer 5 is provided to cover the embedded layer 3 and the joint portion 4-2. The sealing layer 5 extends into the joint portion 4-2, and the extended portion becomes the extended portion 5a of the sealing layer 5. Fig.32 As shown, the auxiliary layer 6 is arranged to cover the sealing layer 5. Thereafter, the supporting substrate 7 is attached to the auxiliary layer 6, thereby obtaining the aforementioned Fig.26 structure.

[0104] By replacing the chip 2-2 in the above manufacturing process with a stacked structure of chips 2-2 and 2-3, the aforementioned Fig. 27 structure.

[0105] <Modification> Fig.33 and Fig.34 It is a diagram showing a modified example. Fig.33 and Fig.34 The light detection device 100 shown is similar to the previously described Fig.26 and Fig. 27 The light detecting device 100 in FIG. 1 is different from that in which the joint portion 4 - 1 reaches the front surface 3 a of the embedding layer 3 , and the extending portion 5 a of the sealing layer 5 extends into the joint portion 4 - 1 .

[0106] 14. Tenth Implementation Plan Fig.35 and Fig.3610 is a diagram showing an example of a schematic configuration of a light detecting device according to the tenth embodiment. The layer structure in the light detecting device 100 described above is configured to be multi-layered. The chip 2 includes two chips 2 aligned in the height direction (Z-axis direction).

[0107] Reference Fig.35 , as two chips 2 aligned in the height direction, chip 2-2 and chip 2-3 are exemplified. Chip 2-2 is a lower chip located below chip 2-3 (on the negative Z-axis side). Chip 2-3 is an upper chip located above chip 2-2 (on the positive Z-axis side). Note that chip 2-2 is located at the same height as chip 2-1.

[0108] The light detection device 100 also includes a bonding layer 13. The bonding layer 13 is arranged between the chip 2-2 and the chip 2-3. The bonding layer 13 is configured to include wiring so as to provide an electrical connection between the chip 2-2 and the chip 2-3. The portion other than the wiring in the bonding layer 13 can be an insulating material, and in this sense, the bonding layer 13 can be restated as an insulating layer. The chip 2-2 and the chip 2-3 are arranged at two sides opposite to each other across the bonding layer 13, and are electrically connected to each other via the bonding layer 13.

[0109] The buried layer 3 includes a buried layer 3-1 and a buried layer 3-2. The buried layer 3-1 is a lower buried layer, which is provided to cover the substrate 1 and to cover the side surface of the chip 2-1 and the side surface of the chip 2-2. The buried layer 3-2 is an upper buried layer, which is provided to cover the bonding layer 13 and the chip 2-3.

[0110] The seam portion 4 includes a seam portion 4-1, a seam portion 4-2 and a seam portion 4-3. The seam portion 4-1 extends from the chip 2-1 toward the front surface 3a of the buried layer 3-1. The seam portion 4-2 extends from the chip 2-1 toward the front surface 3a of the buried layer 3-1. The seam portion 4-3 extends from the chip 2-3 toward the front surface 3a of the buried layer 3-2.

[0111] The joints 4-1 and 4-2 are lower joints that appear in the buried layer 3-1 and extend to the front surface 3a of the buried layer 3-1. The joint 4-3 is an upper joint that appears in the buried layer 3-2 and extends to the front surface 3a of the buried layer 3-2.

[0112] The sealing layer 5 is provided to cover the buried layer 3-2 and the joint portion 4-3. The bonding layer 13 is provided to cover the buried layer 3-1, the joint portion 4-1 and the joint portion 4-2. The bonding layer 13 can play a role similar to that of the sealing layer 5 with respect to the buried layer 3-1, the joint portion 4-1 and the joint portion 4-2.

[0113] exist Fig.36In the example shown, the chip 2 also includes a dummy chip 2D. The dummy chip 2D is located in the buried layer 3-2 above the chip 2-1. The dummy chip 2D creates a state as if a chip 2 having the same volume as the volume of the dummy chip 2D exists in the buried layer 3-2. The material of the dummy chip 2D can be the same as or different from the material of the chip 2. The dummy chip 2D does not have to have the function of the chip 2.

[0114] The chip 2-1 and the dummy chip 2D are disposed at opposite sides of each other via the bonding layer 13. Note that the chip 2-1 and the dummy chip 2D may be but need not be electrically connected to each other. For example, the thickness of the dummy chip 2D is the same as that of the chip 2-3.

[0115] The buried layer 3-2 is provided to cover the bonding layer 13, the dummy chip 2D and the chip 2-3. The joint portion 4 also includes a joint portion 4-D extending from the dummy chip 2D toward the front surface 3a of the buried layer 3-2. The sealing layer 5 is provided to cover the buried layer 3-2, the joint portion 4-D and the joint portion 4-3.

[0116] In the case where the dummy chip 2D is not provided, the entire portion needs to be buried with the buried layer 3, and for example, the height of the buried layer 3 at the portion is insufficient, making it difficult to flatten the buried layer 3. This problem can be solved by the presence of the dummy chip 2D. That is, compared with the case where the dummy chip 2D is not provided, the presence of the dummy chip 2D makes it easier to flatten the buried layer 3-2.

[0117] <Example of Manufacturing Method> Figures 37 to 43 are diagrams showing examples of methods for manufacturing a light detection device. As a premise, it is assumed that the above-described Fig.28 and Fig.29 The buried layer 3-1 corresponds to Fig.28 and Fig.29 The buried layer 3 in the chip 2-2 has a thickness different from that of the chip 2-2. Fig.28 and Fig.29 The thickness of chip 2-2.

[0118] like Fig.37 As shown, the upper part of the buried layer 3-1 is ground and cleaned, and then the sealing layer 5 is set to cover the buried layer 3-1, the joint part 4-1 and the joint part 4-2. The sealing layer 5 extends into the joint part 4-1 and the joint part 4-2, and the extended part becomes the extended part 5a of the sealing layer 5. Fig.38As shown, the sealing layer 5 is removed by grinding. The extension portion 5a remains in the joint portion 4-1 and the joint portion 4-2. The front surface 2a of the chip 2-1 and the front surface 2a of the chip 2-2 are both exposed. The front surface 2a is the surface on the positive direction side of the Z axis of the chip 2-1 and the chip 2-2.

[0119] like Fig.39 As shown, a through via 2v is provided to penetrate the chip 2-2. In addition, the bonding layer 13 is provided to cover the embedded layer 3-1, the chip 2-1, the joint portion 4-1, the chip 2-2 and the joint portion 4-2. Fig.40 As shown, the chip 2-3 is disposed on the bonding layer 13, and is located on the side opposite to the chip 2-2 across the bonding layer 13. Fig.41 As shown, the embedding layer 3-2 is provided to cover the bonding layer 13 and the chip 2-2. A joint portion 4-3 appears. At this time, the joint portion 4-3 is a gap.

[0120] like Fig.42 As shown in FIG. 1 , the sealing layer 5 is provided to cover the buried layer 3-2, the chip 2-3 and the joint portion 4-3. The sealing layer 5 extends into the joint portion 4-3, and the extended portion becomes the extended portion 5a of the sealing layer 5. Fig.43 As shown, the auxiliary layer 6 is arranged to cover the sealing layer 5. Thereafter, by attaching the supporting substrate 7 to the auxiliary layer 6, the aforementioned Fig.35 structure.

[0121] In the above manufacturing process, by setting a dummy chip 2D when setting the chip 2-3, the above-mentioned Fig.36 structure.

[0122] <Modification> Fig.44 2 is a diagram showing a modified example. Two substrates 1 are prepared, a chip 2 and a buried layer 3 are provided on each substrate, and then the two substrates are bonded to each other via a bonding layer 13. The first substrate of the two substrates 1 is referred to and illustrated as substrate 1-1. The second substrate of the two substrates 1 is referred to and illustrated as substrate 1-2.

[0123] The substrate 1-1 is subjected to the same Fig.39The manufacturing process is the same as the manufacturing process up to the manufacturing process of the present invention. Chip 2-1 and chip 2-2 are arranged on substrate 1-1, and then a through-via 2v is arranged. The buried layer 3-1 is arranged to cover substrate 1-1, chip 2-1 and chip 2-2. Seam 4-1 and seam 4-2 will appear in the buried layer 3-1. The sealing layer 5 is arranged to cover the buried layer 3-1, seam 4-1 and seam 4-2. The sealing layer 5 extends into the seam 4-1 and seam 4-2, and the extended portion becomes the extended portion 5a of the sealing layer 5. The sealing layer 5 is removed by grinding. The extended portion 5a remains in the seam 4-1 and seam 4-2. The bonding layer 13 is arranged to cover the buried layer 3-1, seam 4-1 and seam 4-2.

[0124] A chip 2-3 and a dummy chip 2D are arranged on a substrate 1-2, and then a through-path 3v is arranged to penetrate the chip 2-3. The buried layer 3-2 is arranged to cover the substrate 1-2, the chip 2-2 and the dummy chip 2D. A seam 4-3 and a seam 4-D appear in the buried layer 3-2. The sealing layer 5 is arranged to cover the buried layer 3-2, the seam 4-3 and the seam 4-D. The sealing layer 5 extends into the seam 4-3 and the seam 4-D, and the extended portion becomes an extension 5a of the sealing layer 5. The sealing layer 5 is removed by grinding. The extension 5a remains in the seam 4-3 and the seam 4-D.

[0125] By bonding the embedding layer 3-2 on the substrate 1-2 side obtained as described above to the bonding layer 13 on the substrate 1-1 side, a Fig.44 The bonding can be performed by bonding a wafer (e.g., a semiconductor wafer) including the substrate 1-1 and a wafer including the substrate 1-2. The inside of the joint 4 is filled with the extension 5a, and the opening of the joint 4 is covered with the bonding layer 13. It can also be considered that the bonding layer 13 acts as a sealing layer 5 covering the joint 4.

[0126] <Conclusion> For example, the light detecting device 100 according to the ninth embodiment and the tenth embodiment described above is defined as follows. Fig.26 and Fig.33 As described in, etc., the chip 2 may include a chip 2-1 (first chip) and a chip 2-2 (second chip) having a thickness greater than that of the chip 2-1; the seam 4 may include a seam 4-1 (first seam) extending from the chip 2-1 toward the front surface 3a of the buried layer 3 and a seam 4-2 (second seam) extending from the chip 2-2 toward the front surface 3a of the buried layer 3; and the seam 4-2 may extend to a position closer to the front surface 3a of the buried layer 3 than the seam 4-1. Alternatively, as described in reference Fig. 27 and Fig.34As described in the above, the chip 2 may include a chip 2-1 (first chip), and a chip 2-2 (second chip) and a chip 2-3 (third chip) stacked in sequence; the overall thickness of the chip 2-2 and the chip 2-3 may be greater than the thickness of the chip 2-1; the seam portion 4 may include a seam portion 4-1 (first seam portion) extending from the chip 2-1 toward the front surface 3a of the buried layer 3 and a seam portion 4-2 (second seam portion) extending from the chip 2-2 toward the front surface 3a of the buried layer 3; and the seam portion 4-2 may extend to a position closer to the front surface 3a of the buried layer 3 than the seam portion 4-1. In this way, even in a structure including chip portions having mutually different thicknesses, the connection between the seam portion 4 and the outside can be suppressed.

[0127] As reference Fig.26 , Fig. 27 , Fig.33 and Fig.34 As described in the above, the sealing layer 5 may include an extension portion 5a extending into the joint portion 4-2 to fill at least a portion of the joint portion 4-2. In this way, the advantages of the extension portion 5a can also be obtained. For example, when the material of the sealing layer 5 includes a low permeability material, the effect of suppressing the intrusion of moisture and the like into the chip 2 is enhanced; in addition, when the material of the sealing layer 5 includes a low Young's modulus material, the stress between the chips can be relieved.

[0128] As reference Fig.26 and Fig. 27 As described in the above, the seam portion 4-1 may be in a state where it does not reach the front surface 3a of the buried layer 3, and the seam portion 4-2 may be in a state where it reaches the front surface 3a of the buried layer 3. In this way, even when the seam portion 4-2 that reaches the front surface 3a of the buried layer 3 and the seam portion 4-1 that does not reach the front surface 3a coexist, the connection between the seam portion 4 and the outside can be suppressed.

[0129] As reference Fig.35 and Fig.36As described in the above, the chip 2 may include a chip 2-2 (lower chip) and a chip 2-3 (upper chip) aligned in the height direction; the light detection device 100 may also include a bonding layer 13 arranged between the chip 2-2 and the chip 2-3; the buried layer 3 may include a buried layer 3-1 (lower buried layer) arranged in a manner to cover the side of the chip 2-2 and a buried layer 3-2 (upper buried layer) arranged in a manner to cover the chip 2-3 and the bonding layer 13; the joint 4 may include a joint 4-2 (lower joint) appearing in the buried layer 3-1 and extending to the front side 3a of the buried layer 3-1 and a joint 4-3 (upper joint) appearing in the buried layer 3-2 and extending to the front side 3a of the buried layer 3-2; the bonding layer 13 may be arranged to cover the buried layer 3-1 and the joint 4-2; and the sealing layer 5 may be arranged to cover the buried layer 3-2 and the joint 4-3. Even with such a structure, it is possible to suppress the joint portion 4 from communicating with the outside.

[0130] As reference Fig.36 As described in the above, the chip 2 may further include a chip 2-1 (lower chip) and a dummy chip 2D disposed at two sides opposite to each other across the bonding layer 13, and the buried layer 3-2 may be disposed to cover the chip 2-3, the dummy chip 2D, and the bonding layer 13. This configuration makes it easier to flatten the buried layer 3-2 than when the dummy chip 2D is not disposed.

[0131] 15. Eleventh Implementation Plan Fig.45 and Fig.46 11 is a diagram showing an example of a schematic configuration of a light detecting device according to the eleventh embodiment. The sealing layer 5 includes a first portion 51 and a second portion 52 .

[0132] The first portion 51 is a portion of the sealing layer 5 and covers the seam portion 4. At least a portion of the first portion 51 is located between the chips 2 adjacent to each other. The second portion 52 is a portion of the sealing layer 5 and does not cover the seam portion 4. At least a portion of the second portion 52 is located above the corresponding chip 2. The second portion 52 may be a portion of the sealing layer 5 other than the first portion 51.

[0133] The surface of the first portion 51 on the positive Z-axis direction side is referred to as and is shown as the front side 51a. The surface of the first portion 51 on the negative Z-axis direction side is referred to as and is shown as the back side 51b. The surface of the second portion 52 on the positive Z-axis direction side is referred to as and is shown as the front side 52a. The surface of the second portion 52 on the negative Z-axis direction side is referred to as and is shown as the back side 52b. The back side 51b of the first portion 51 is located at a lower position (on the negative Z-axis direction side) than the back side 52b of the second portion 52.

[0134] exist Fig.45 In the example shown, the front surface 51a of the first portion 51 and the front surface 52a of the second portion 52 are located at the same height. The entire front surface of the sealing layer 5 is a flattened surface.

[0135] exist Fig.46 In the example shown, the front face 51a of the first part 51 and the front face 52a of the second part 52 are located at different heights from each other. In this example, the front face 52a of the second part 52 is located at a position higher (Z-axis positive direction side) than the front face 51a of the first part 51. The entire front face of the sealing layer 5 is a non-planarized face. However, the auxiliary layer 6 (e.g., SiO2) provided on the sealing layer 5 has a front face 6a as a planarized face, thereby ensuring flatness. Depending on the material of the sealing layer 5, it is sometimes difficult to planarize the sealing layer 5 by grinding or the like. In this case, the sealing layer 5 is not planarized, but the manufacturing process is facilitated by using an auxiliary layer 6 that can be more easily planarized. The auxiliary layer 6 may also be referred to as a planarization-facilitating layer.

[0136] according to Fig.45 and Fig.46 The structure of the present invention can increase the thickness of the sealing layer 5 on the joint portion 4 compared to the above structure. Therefore, the function of the sealing layer 5 for suppressing the connection between the joint portion 4 and the outside can be enhanced. In addition, since it is not necessary to flatten the buried layer 3, it is possible to prevent the intrusion of chemical liquid into the joint portion 4, which may occur when grinding or cleaning the buried layer 3.

[0137] <Example of Manufacturing Method> Figures 47 to 51 1 is a diagram showing an example of a method for manufacturing a light detection device. Figure 47 to Figure 49 The method for obtaining the aforementioned Fig.45 As a premise, it is assumed that the above-mentioned Fig. 9 and Fig.10 The manufacturing process is the same manufacturing process as in the manufacturing process.

[0138] like Fig.47 As shown in FIG. 1 , the sealing layer 5 is disposed on the embedding layer 3 without grinding the embedding layer 3. The sealing layer 5 extends into the joint portion 4, and the extended portion becomes the extended portion 5a of the sealing layer 5. Fig.48 As shown, by grinding and cleaning the top of the sealing layer 5, the above-mentioned Fig.45 The sealing layer 5 includes a first portion 51 and a second portion 52. The front surface 51a of the first portion 51 and the front surface 52a of the second portion 52 are located at the same height, so that the front surface of the entire sealing layer 5 becomes a flat surface. Fig.49As shown, the auxiliary layer 6 is arranged to cover the sealing layer 5. Thereafter, by attaching the supporting substrate 7 to the auxiliary layer 6, the aforementioned Fig.45 structure.

[0139] Fig.50 and Fig.51 The method for obtaining the aforementioned Fig.46 As a premise, it is assumed that the above-mentioned Fig.47 manufacturing process.

[0140] like Fig.50 As shown, the above-mentioned Fig.49 The sealing layer 5 includes the first portion 51 and the second portion 52, and the auxiliary layer 6 is arranged to cover the sealing layer 5 without grinding the sealing layer 5. Fig.51 As shown, the top of the auxiliary layer 6 is ground and cleaned, thereby obtaining the auxiliary layer 6 having a flat front surface 6a. Thereafter, by attaching the support substrate 7 to the auxiliary layer 6, the aforementioned Fig.46 structure.

[0141] 16. Twelfth Implementation Plan In one embodiment, the sealing layer 5 may have a laminated structure. This will be referred to Fig.52 to explain.

[0142] Fig.52 It is a diagram showing an example of a schematic structure of a sealing layer. Fig.52 (A) schematically shows a cross section of the sealing layer 5 and its surroundings. Fig.52 (B) in FIG. 5 schematically shows a cross section obtained by enlarging a part of the sealing layer 5 .

[0143] The sealing layer 5 has a stacked structure including a stack of multiple layers. For example, the multiple layers may include two types of layers. One of the two types of layers may be an inorganic layer, and the other may be an organic layer. The inorganic layer is referred to and illustrated as an inorganic layer 53. The organic layer is referred to and illustrated as an organic layer 54.

[0144] The material of the inorganic layer 53 may be various known inorganic materials, and examples of the inorganic material include Al2O3, SiN, SiON, SiCN, and the like.

[0145] The material of the organic layer 54 can be various known organic materials. Examples of the material include polymers, hybrid polymers, etc. Examples of the polymer include PEN, PET, PEG, etc. For example, the hybrid polymer is a material comprising a polymer and a metal material. When the metal material is aluminum, an example of the hybrid polymer is Alcone. For example, the organic layer 54 can be formed by using a spin coating method, an inkjet method, an MLD (molecular layer deposition) method, etc. The sealing layer 5 including the extension 5a extending to the inside of the seam portion 4 can be preferably formed using the MLD method.

[0146] exist Fig.52 In the example shown, the sealing layer 5 has a six-layer structure including three inorganic layers 53 and three organic layers 54. The inorganic layers 53 and the organic layers 54 are alternately stacked. However, the number of the inorganic layers 53 and the number of the organic layers 54 may be less than or greater than Fig.52 Quantity shown.

[0147] Since the sealing layer 5 has a laminated structure, it is possible to enhance the function of the sealing layer 5. For example, the gas (water vapor, etc.) barrier property can be improved or the robustness against deformation can be improved.

[0148] <Conclusion> For example, the light detecting device 100 according to the aforementioned eleventh embodiment and the twelfth embodiment is defined as follows. Fig.45 , Fig.46 As described in the examples above, the sealing layer 5 may include a first portion 51 covering the seam portion 4 and a second portion 52 not covering the seam portion 4, and the back surface 51b of the first portion 51 may be located further downward (on the negative side of the Z axis) than the back surface 52b of the second portion 52. Fig.45 As described in the examples above, the front face 51a of the first portion 51 may be located at the same height as the front face 52a of the second portion 52. Fig.46 As described in the above, the light detection device 100 may include an auxiliary layer 6 configured to cover the sealing layer 5, the front surface 52a of the second part 52 may be located higher (on the positive side of the Z axis) than the front surface 51a of the first part 51, and the front surface 6a of the auxiliary layer 6 may be a flattened surface. For example, using this structure, the thickness of the sealing layer 5 on the joint portion 4 can be increased. Therefore, the function of the sealing layer 5 for suppressing the connection between the joint portion 4 and the outside can be enhanced. In addition, there is no need to flatten the buried layer 3, for example, it is possible to prevent the intrusion of chemical liquid into the joint portion 4 that may occur when grinding or cleaning the buried layer 3.

[0149] As reference Fig.52As described in the foregoing, the sealing layer 5 may have a laminated structure including a laminate of a plurality of layers. The plurality of layers of the sealing layer 5 may include an inorganic layer 53 and an organic layer 54. With this configuration, the function of the sealing layer 5 can be enhanced. For example, the gas (water vapor, etc.) barrier property can be improved or the robustness against deformation can be improved.

[0150] 17. Thirteenth Implementation Plan Fig.53 1 is a diagram showing an example of a schematic configuration of a light detecting device according to the thirteenth embodiment. The light detecting device 100 includes a dummy chip 2D. Note that the dummy chip 2D here may be the same as that of the tenth embodiment ( Fig.36 )'s virtual chip 2D is understood differently.

[0151] The dummy chip 2D is used to reduce the peripheral spacing of the chip 2. The dummy chip 2D is arranged to be spaced apart from the chip 2. In this example, the chip 2 includes two chips 2 arranged separately from each other. The dummy chip 2D is arranged between the two chips 2.

[0152] The buried layer 3 is arranged to cover the substrate 1, the chip 2 and the dummy chip 2D. In the portion between the chip 2 and the dummy chip 2D, the seam portion 4 extends to the front side 3a of the buried layer 3. The aspect ratio of the portion of the buried layer 3 where the seam portion 4 appears increases accordingly according to the area of ​​the dummy chip 2D. The aspect ratio here is equivalent to the ratio of the length in the Z-axis direction to the length in the XY plane direction. With the increase of the aspect ratio, the extension direction of the seam portion 4 is restricted. Thus, the extension direction of the seam portion 4 can be made close to the height direction (positive direction of the Z-axis) of the chip 2 and the dummy chip 2D. The aspect ratio can be designed so that such a seam portion 4 can be easily obtained. For example, the aspect ratio can be designed in the range of 1 to 3.

[0153] The seam portion 4 extends along the height direction (positive direction of the Z axis) of the chip 2 and the dummy chip 2D. Extending along the height direction may include not only extending in the same direction as the height direction, but also extending at a specific angle relative to the height direction. Examples of upper limits of such angles include less than 30 degrees, less than 25 degrees, less than 20 degrees, less than 15 degrees, less than 10 degrees, less than 5 degrees, etc. The lower limit of the angle may be 0 degrees. Note that, hereinafter, extending along the height direction of the chip 2 and the dummy chip 2D is also referred to as extending in the vertical direction.

[0154] Since the joint portion 4 extends in the vertical direction, when the sealing layer 5 is provided to cover the embedding layer 3 and the joint portion 4, the sealing layer 5 easily extends into the joint portion 4. Thereby, the advantages of the extended portion 5a of the sealing layer 5 described so far are very easily obtained.

[0155] <Example of Manufacturing Method> Figure 54 to Figure 58 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.54 As shown, the chip 2 and the dummy chip 2D are arranged on the substrate 1. Fig.55 As shown, the buried layer 3 is set (for example, film-formed) to cover the substrate 1, the chip 2 and the dummy chip 2D. The seam portion 4 appears due to the overhang during the film formation. That is, the top of the chip 2 achieves film formation earlier than the film formation speed at the bottom of the portion between the chip 2 and the dummy chip 2D. The above-mentioned overhang blocks the material of the buried layer 3 during the film formation, resulting in the interruption of the film formation between the chip 2 and the dummy chip 2D, thereby forming the seam portion 4. However, since the peripheral spacing of the chip 2 is correspondingly narrowed according to the area of ​​the dummy chip 2D, the extension direction of the seam portion 4 is close to the height direction of the chip 2 and the dummy chip 2D (the positive direction of the Z axis). At this time, the seam portion 4 is a gap.

[0156] like Fig.56 As shown in FIG. 1 , the top of the buried layer 3 is ground and cleaned. Thus, the top of the joint portion 4 is open. Fig.57 As shown, the sealing layer 5 is provided to cover the embedding layer 3 and the joint portion 4. Since the joint portion 4 extends in the vertical direction, the sealing layer 5 easily extends into the joint portion 4, and the extended portion becomes the extended portion 5a of the sealing layer 5. Fig.58 As shown, the auxiliary layer 6 is arranged to cover the sealing layer 5. Thereafter, by attaching the supporting substrate 7 to the auxiliary layer 6, the aforementioned Fig.53 structure.

[0157] 18. Fourteenth Implementation Plan Fig.59 14 is a diagram showing an example of a schematic configuration of a light detecting device according to the fourteenth embodiment. The chip 2 has a shape in which the width (length in the XY plane direction) decreases as it approaches the front surface 2a.

[0158] The portion located in the center of the chip 2 in the XY plane direction is referred to as and illustrated as a central portion 21. In the chip 2, the portion located outside the central portion 21 and including the edge of the chip 2 is referred to as and illustrated as an edge portion 22. The edge portion 22 of the chip 2 has a rounded shape at the front surface 2a of the chip 2. The edge portion 22 may have a shape other than the rounded shape. Another example of the shape is a tapered shape.

[0159] The buried layer 3 is provided to cover the chip 2. The seam portion 4 extends from the chip 2 to the front surface 3a of the buried layer 3. Since the width of the front surface 2a side of the chip 2 is narrowed, the seam portion 4 extends in the height direction of the chip 2, that is, in the vertical direction. This is because: the embedding property of the buried layer 3 is improved at the periphery of the chip 2, more specifically, in the present example, in the bottom of the portion between the chips 2 adjacent to each other. The advantages of extending the seam portion 4 in the vertical direction are as described above.

[0160] <Example of Manufacturing Method> Figure 60 to Figure 64 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.60 As shown in FIG. 1 , a chip 2 having a narrow front surface 2a side width is provided on a substrate 1. For example, the chip 2 is processed so that the angle of the corner of the edge portion 22 of the chip 2 is less than 90 degrees. An example of this processing is chamfering performed on the front surface 2a of the chip 2. Examples of this chamfering include C chamfering, R chamfering, etc. performed by plasma etching, etc. Fig.61 As shown, the embedding layer 3 is provided to cover the substrate 1 and the chip 2. With the degree of processing of the chip 2 as described above, the embedding property of the embedding layer 3 at the bottom of the portion between the chips 2 is improved. The extending direction of the already formed joint portion 4 is close to the height direction (Z-axis positive direction) of the chip 2. At this time, the joint portion 4 is a gap.

[0161] like Fig.62 As shown in FIG. 1 , the top of the buried layer 3 is ground and cleaned. Thus, the top of the joint portion 4 is open. Fig.63 As shown, the sealing layer 5 is provided to cover the embedding layer 3 and the joint portion 4. Since the joint portion 4 extends in the vertical direction, the sealing layer 5 easily extends into the joint portion 4, and the extended portion becomes the extended portion 5a of the sealing layer 5. Fig.64 As shown, the auxiliary layer 6 is provided to cover the sealing layer 5. Even when the auxiliary layer 6 is ground and cleaned, the joint portion 4 is covered by the sealing layer 5, thereby preventing the joint portion 4 from expanding. Thereafter, the supporting substrate 7 is attached to the auxiliary layer 6, thereby obtaining the aforementioned Fig.59 structure.

[0162] 19. Fifteenth Implementation Plan Fig.65 1 is a diagram showing an example of a schematic configuration of a light detection device according to the fifteenth embodiment. The seam portion 4 has a shape in which its width (length in the XY plane direction) changes as the seam portion advances in the extension direction. The shape of the seam portion 4 may be a shape having a partial expansion.

[0163] The seam portion 4 includes an end portion 41, a central portion 42, and an end portion 43. The central portion 42 is a portion located at the center of the seam portion 4 in the extending direction of the seam portion 4. The end portions 41 and the end portions 43 are portions located at both ends of the seam portion 4 in the extending direction of the seam portion 4. The end portions 41 and the end portions 43 are located at opposite sides of the central portion 42. In this example, the end portions 41, the central portion 42, and the end portions 43 are arranged in sequence in the positive direction of the Z axis.

[0164] The width of the central portion 42 is greater than the width of at least one of the end portions 41 and 43. In this example, the width of the central portion 42 is greater than the width of the end portions 41 and greater than the width of the end portions 43. The seam portion 4 has a shape that allows the central portion 42 to expand in the extending direction of the seam portion 4.

[0165] exist Fig.65 In the example shown, a dummy chip 2D is provided on the substrate 1. However, even in the case where the dummy chip 2D is not provided, the joint portion 4 having a partially expanded shape can also appear. When the dummy chip 2D is provided, the extending direction of the joint portion 4 can be made close to the height direction (Z-axis positive direction) of the chip 2 and the dummy chip 2D. In addition, by using the aforementioned Fig.59 The same effect can be obtained even if the chip 2 having a narrow front surface 2 a side width is provided instead of the dummy chip 2D.

[0166] <Example of Manufacturing Method> Figure 66 to Figure 69 is a diagram showing an example of a method for manufacturing a light detection device. As a premise, it is assumed that the above-described Fig.54 The same manufacturing process as in Fig.66 As shown, the buried layer 3 is set (for example, film-formed) to cover the substrate 1, the chip 2 and the dummy chip 2D. Due to the overhang during film formation, a joint portion 4 appears. Relative to the film forming speed at the bottom of the portion between the chip 2 and the dummy chip 2D, the top of the chip 2 achieves film formation earlier. The above-mentioned overhang blocks the material of the buried layer 3 during film formation, resulting in the interruption of film formation between the chip 2 and the dummy chip 2D and the appearance of a local gap. This gap will become the joint portion 4. Since the peripheral spacing of the chip 2 is correspondingly narrowed according to the area of ​​the dummy chip 2D, the extension direction of the joint portion 4 is close to the height direction of the chip 2 and the dummy chip 2D (the positive direction of the Z axis).

[0167] like Fig.67 As shown in FIG. 1 , the top of the buried layer 3 is ground and cleaned. Thus, the top of the joint portion 4 is open. Fig.68As shown, the sealing layer 5 is provided to cover the embedding layer 3 and the joint portion 4. Since the joint portion 4 extends in the vertical direction, the sealing layer 5 easily extends into the joint portion 4, and the extended portion becomes the extended portion 5a of the sealing layer 5. Fig.69 As shown, the auxiliary layer 6 is arranged to cover the sealing layer 5. Thereafter, the supporting substrate 7 is attached to the auxiliary layer 6, thereby obtaining the aforementioned Fig.65 structure.

[0168] <Conclusion> For example, the light detecting device 100 according to the thirteenth to fifteenth embodiments described above is defined as follows. Fig.53 As described in the above, the light detection device 100 may include a dummy chip 2D arranged in a manner adjacent to the chip 2 with a gap, the buried layer 3 may be arranged to cover the chip 2 and the dummy chip 2D, and the seam portion 4 may extend to the front side 3a of the buried layer 3 in the portion between the chip 2 and the analog chip 2D. The seam portion 4 may extend in the height direction (positive direction of the Z axis) of the chip 2 and the dummy chip 2D. The chip 2 may include two chips 2 arranged separately from each other, and a dummy chip 2D may be arranged between the two chips 2. With this structure, when the sealing layer 5 is arranged to cover the buried layer 3 and the seam portion 4, the sealing layer 5 easily extends into the seam portion 4. Therefore, it is very easy to obtain the advantages of the extended portion 5a of the sealing layer 5.

[0169] As reference Fig.59 As described in the above, the chip 2 may have a shape in which the width decreases as it goes toward the front side 2a of the chip 2 (as it goes toward the positive direction of the Z axis). The edge portion 22 of the chip 2 may have a tapered shape or a rounded shape at the front side 2a of the chip 2. The seam portion 4 may extend in the height direction (Z axis direction) of the chip 2. Even with this configuration, when the sealing layer 5 is set to cover the buried layer 3 and the seam portion 4, the sealing layer 5 easily extends into the seam portion 4.

[0170] As reference Fig.65 As described in, etc., the seam portion 4 may have a shape in which its width changes as the seam portion moves forward in the extension direction. The seam portion 4 may include: a central portion 42 located at the center in the extension direction of the seam portion 4; and an end portion 41 (which may also be an end portion 43) located at the end in the extension direction of the seam portion 4. The width of the central portion 42 may be greater than the width of the end portion 41 (which may also be an end portion 43). Even in the case where such a shape of the seam portion 4 is adopted, the connection between the seam portion 4 and the outside can be suppressed. In addition, for example, by providing a dummy chip 2D or by using a chip 2 having a narrow front 2a side width, the extension direction of the seam portion 4 can be close to the height direction (Z-axis direction) of the chip 2.

[0171] 20. Example of dummy chip layout Some arrangement examples of the dummy chips 2D described in the thirteenth embodiment will be described below.

[0172] <First Arrangement Example> Fig.70 and Fig.71 is a diagram showing a first arrangement example of dummy chips. Fig.70 A cross section of the light detection device 100 is schematically shown. Fig.71 Schematically shows the Fig.70 The cross section (planar layout) of the light detection device 100 when viewed from line II in FIG. Fig.70 In the example shown, the seam 4 is filled with the extension 5a. Fig.71 In FIG. 1 , the joint portion 4 is simplified and drawn without having a width.

[0173] The chip 2 has a side surface 2c, a side surface 2d, a side surface 2e, and a side surface 2f. The side surface 2c and the side surface 2d are a pair of side surfaces opposite to each other. The side surface 2e and the side surface 2f are a pair of side surfaces opposite to each other and connecting the side surface 2c and the side surface 2d to each other. When there is no need to particularly distinguish the side surface 2c, the side surface 2d, the side surface 2e, and the side surface 2f of the chip 2, they are also referred to as the side surface of the chip 2.

[0174] like Fig.71 As shown, in a plan view, the dummy chip 2D extends in a manner facing the side surface of the chip 2. The dummy chip 2D may be a plurality of dummy chips 2D, and each of the dummy chips 2D faces different side surfaces of the chip 2.

[0175] The number of dummy chips 2D provided for one chip 2 may be two or more. The material of the dummy chip 2D may include the same material as that of the chip 2. In addition, the dummy chip 2D may have the same height as that of the chip 2. The chip 2 and the dummy chip 2D may be alternately arranged in the XY plane direction.

[0176] When a dummy chip 2D is provided around the chip 2, the stress acting on the material of the buried layer 3 from the chip 2 toward the periphery of the chip 2 when the buried layer 3 is formed (for example, when forming a film) can be suppressed compared to the case where the dummy chip 2D is not provided.

[0177] The dummy chip 2D may include two or more dummy chips 2D. Fig.71In the example shown, the dummy chip 2D includes four dummy chips 2D. The dummy chip 2D facing the side 2c of the chip 2 is referred to as and is illustrated as a dummy chip 2D-1. The dummy chip 2D facing the side 2d of the chip 2 is referred to as and is illustrated as a dummy chip 2D-2. The dummy chip 2D facing the side 2e of the chip 2 is referred to as and is illustrated as a dummy chip 2D-3. The dummy chip 2D facing the side 2f of the chip 2 is referred to as and is illustrated as a dummy chip 2D-4. Fig.71 In the example shown, the dummy chips 2D are arranged spaced apart from each other. Near the corners of the chip 2, the dummy chips 2D are separated from each other.

[0178] Fig.72 This is a diagram showing the effect of a dummy chip. Fig.72 (A) in FIG. 1 schematically shows the range of the joint portion 4E1 that can appear when only the chip 2 is provided. Fig.72 (B) in FIG. 1 schematically shows the range of the joint portion 4E2 that can appear when only the dummy chip 2D is provided. Fig.72 (C) in the figure schematically shows the range of the seam 4 that can appear when the chip 2 and the dummy chip 2D are provided. When the dummy chip 2D is provided, the range of the seam 4 is narrowed in the plan view. This means that the extension direction of the seam 4 can be made close to the height direction (Z-axis positive direction) of the chip 2 and the dummy chip 2D, that is, the seam 4 extending in the vertical direction can be obtained.

[0179] Back to Fig.71 , the length of the dummy chip 2D in the extension direction of the dummy chip 2D may be more than half the length of the side surface of the chip 2 facing the dummy chip 2D. For example, the length of the side surface 2c of the chip 2 is referred to and illustrated as length H. The length of the side surface 2e of the chip 2 is referred to and illustrated as length W. The length of the dummy chip 2D-1 in the extension direction facing the side surface 2c of the chip 2 is referred to and illustrated as length H. D The length of the dummy chip 2D- 3 facing the side surface 2 e of the chip 2 in the extending direction is referred to and illustrated as length W. D .

[0180] The length H of the dummy chip 2D-1 D It can be designed to satisfy the following formula (1). H D ≥H / 2 (1) The dummy chip 2D-2 can be designed in the same manner.

[0181] The dummy chip 2D- 3 may be designed to satisfy the following formula (2). W D ≥W / 2 (2) The dummy chip 2D-4 can be designed in the same manner.

[0182] As described above, by making the dummy chip 2D have a certain length, it is very easy to obtain the effect of the dummy chip 2D, that is, it is very easy to obtain the effect of making the extension direction of the joint portion 4 close to the height direction of the chip 2 and the dummy chip 2D (positive direction of the Z axis).

[0183] In addition, Fig.71 In the example shown, the dummy chip 2D is arranged to sandwich the chip 2. Specifically, the dummy chip 2D-1 and the dummy chip 2D-2 are arranged on both sides opposite to each other across the chip 2 in a manner of sandwiching the chip 2. In addition, the dummy chip 2D-3 and the dummy chip 2D-4 are arranged on both sides opposite to each other across the chip 2 in a manner of sandwiching the chip 2. For example, this can expand the area where the effect of the dummy chip 2D can be exerted, compared with the case where only the dummy chip 2D facing one side of the chip 2 is provided.

[0184] For example, components of the light detection device 100 such as the chip 2 and the dummy chip 2D may be arranged for each region divided by a scribe line on a wafer. The light detection device 100 is obtained by slicing (cutting) the wafer along the scribe line. This will be referred to as Fig.73 to explain.

[0185] Fig.73 2 is a diagram showing an example of a schematic structure of a wafer. The wafer is referred to as and shown as a wafer 200 . Fig.73 A portion of wafer 200 in a plan view (when viewed in the negative direction of the Z axis) is schematically shown. Wafer 200 has scribe lines SL-H and scribe lines SL-V formed to be orthogonal to each other. When these scribe lines are not particularly distinguished, they are simply referred to as scribe lines SL.

[0186] An area surrounded by the scribe line SL-H and the scribe line SL-V corresponds to one light detection device 100. In this example, the chip 2 and the dummy chip 2D of the light detection device 100 are located inside the scribe line SL (not on the scribe line SL). One slice (one grain) obtained by slicing the wafer 200 along the scribe line SL will become the light detection device 100.

[0187] Regarding the second to seventh arrangement examples described later, the differences from the first arrangement example will be mainly described. The description of the first arrangement example can be appropriately cited within the scope of no contradiction. For example, the material of the dummy chip 2D can include the same material as the material of the chip 2. The height of the dummy chip 2D can be the same as the height of the chip 2. In addition, the dummy chip 2D can be arranged to sandwich the chip 2.

[0188] <Second Arrangement Example> Fig.74 2 is a diagram showing a second arrangement example of dummy chips. Dummy chips 2D extend continuously in a manner surrounding chip 2. In this example, dummy chips 2D-1 to 2D-4 are connected to each other and arranged to surround chip 2. The entire periphery of chip 2 is surrounded by dummy chips 2D, so that the effect of dummy chips 2D can be maximized.

[0189] Fig.75 is a diagram showing the effect of a dummy chip. Fig.72 The instructions in are similar and therefore will be omitted.

[0190] Fig.76 2 is a diagram showing an example of a schematic structure of a wafer. The chip 2 and the dummy chip 2D of the light detection device 100 are located inside the scribe line SL. The light detection device 100 is obtained by dicing the wafer 200 along the scribe line SL.

[0191] <Third Arrangement Example> Fig.77 2D-1, 2D-2, 2D-3, and 2D-4, which are disposed separately from each other, are disposed to surround the chip 2.

[0192] Among the side surfaces of the dummy chip 2D-1, the side surfaces of the dummy chip 2D-2, the side surfaces of the dummy chip 2D-3, and the side surfaces of the dummy chip 2D-4, the side surfaces located at the side opposite to the chip 2 are respectively referred to and illustrated as the side surfaces 2D-1a, the side surfaces 2D-2a, the side surfaces 2D-3a, and the side surfaces 2D-4a. These side surfaces constitute a part of the side surfaces of the optical detection device 100. When the optical detection device 100 is observed from the side (when observed in the X-axis direction or the Y-axis direction), the side surfaces 2D-1a, the side surfaces 2D-2a, the side surfaces 2D-3a, and the side surfaces 2D-4a are exposed from the buried layer 3 (not covered by the buried layer 3). By arranging the dummy chip 2D at the outermost portion of the optical detection device 100, it is possible to easily ensure an area for setting the chip 2, for example.

[0193] Fig.78 is a diagram showing the effect of a dummy chip. Fig.72 The instructions in are similar and therefore will be omitted.

[0194] Fig.792 is a diagram showing an example of a schematic structure of a wafer. The chip 2 of the light detecting device 100 is located on the inner side of the scribe line SL. On the other hand, the dummy chips 2D of the light detecting devices 100 adjacent to each other are arranged to cross the scribe line SL and be connected to each other. In other words, these dummy chips 2D are arranged on the scribe line SL. The light detecting device 100 is obtained by slicing the wafer 200 and the dummy chips 2D along the scribe line SL. Since the dummy chips 2D of the light detecting devices 100 adjacent to each other can be arranged together, manufacturing becomes easy.

[0195] <Fourth Arrangement Example> Fig.80 is a diagram showing a fourth arrangement example of dummy chips. Chip 2 is arranged near a corner of the light detection device 100. In this example, chip 2 is arranged so that side 2c and side 2e of chip 2 are respectively located near two side surfaces of the light detection device 100. Two dummy chips 2D are arranged to face the other two side surfaces of chip 2, respectively. In this example, a dummy chip 2D-2 facing side 2d of chip 2 and a dummy chip 2D-4 facing side 2f of chip 2 are arranged.

[0196] Fig.81 is a diagram showing the effect of a dummy chip. Fig.72 The instructions in are similar and therefore will be omitted.

[0197] Fig.82 2 is a diagram showing an example of a schematic structure of a wafer. In this example, the chip 2 and the dummy chip 2D of the light detection device 100 are located inside the scribe line SL. The light detection device 100 is obtained by slicing the wafer 200 along the scribe line SL.

[0198] <Fifth Arrangement Example> Fig.83 2D-1, 2D-2, 2D-3 and 2D-4 are arranged to surround the chip 2. Fig.77 The difference is that when observing the light detection device 100 from the side, the side 2D-1a of the dummy chip 2D-1, the side 2D-2a of the dummy chip 2D-2, the side 2D-3a of the dummy chip 2D-3 and the side 2D-4a of the dummy chip 2D-4 are not exposed from the buried layer 3 (but are covered by the buried layer 3).

[0199] Fig.84 is a diagram showing the effect of the dummy chip 2D. Fig.72 The instructions in are similar and therefore will be omitted.

[0200] Fig.851 is a diagram showing an example of a schematic structure of a wafer. The chip 2 and the dummy chip 2D of the light detection device 100 are located inside the scribe line SL. Fig.79 The difference is that the dummy chips 2D of the adjacent light detecting devices 100 are separated from each other without crossing the scribe line SL. The light detecting devices 100 are obtained by slicing the wafer 200 along the scribe line SL.

[0201] <Sixth Arrangement Example> Fig.86 is a diagram showing an example of a schematic structure of a wafer. The chip 2 includes two or more chips 2, and Fig.86 There are shown two chips 2. A side surface 2e of one chip 2 and a side surface 2f of the other chip 2 face each other.

[0202] Two dummy chips 2D are arranged. One of the two dummy chips 2D is arranged between the two chips 2. The dummy chip 2D is referred to and illustrated as a dummy chip 2D-34. The other of the two dummy chips 2D is arranged as a dummy chip 2D-2 extending along the side 2d of the two chips 2.

[0203] Fig.87 is a diagram showing the effect of a dummy chip. Fig.72 The instructions in are similar and therefore will be omitted.

[0204] Fig.88 2 is a diagram showing an example of a schematic structure of a wafer. The chip 2 and the dummy chip 2D of the light detection device 100 are located inside the scribe line SL. The light detection device 100 is obtained by dicing the wafer 200 along the scribe line SL.

[0205] <Seventh Arrangement Example> Fig.89 7 is a diagram showing a seventh arrangement example of a dummy chip. Fig.74 ) and the third arrangement example ( Fig.77 ) are combined. The dummy chip 2D extends continuously in a manner surrounding the chip 2. In the present example, the dummy chips 2D-1 to 2D-4 are connected to each other and arranged to surround the chip 2. In addition, when the light detection device 100 is observed from the side (when observed in the X-axis direction or the Y-axis direction), the side 2D-1a of the dummy chip 2D-1, the side 2D-2a of the dummy chip 2D-2, the side 2D-3a of the dummy chip 2D-3, and the side 2D-4a of the dummy chip 2D-4 are exposed from the buried layer 3.

[0206] Fig.90 is a diagram showing the effect of a dummy chip. Fig.72 The instructions in are similar and therefore will be omitted.

[0207] Fig.91 2 is a diagram showing an example of a schematic structure of a wafer. The chip 2 of the light detection device 100 is located inside the scribe line SL. On the other hand, the dummy chips 2D of the light detection devices 100 adjacent to each other are arranged to cross the scribe line SL and connect to each other. The light detection device 100 is obtained by slicing the wafer 200 and the dummy chip 2D along the scribe line SL.

[0208] <Modification> Fig.92 and Fig.93 It is a diagram showing a modified example. Fig.92 A cross section of the light detection device 100 is schematically shown. Fig.93 Schematically shows the Fig.92 The layout of the dummy chip 2D is similar to the first arrangement example ( Fig.70 and Fig.71 ) is the same. However, in this example, the sealing layer 5 does not have the extension portion 5a, and the seam portion 4 is a gap. Even in this case, the effect of the dummy chip 2D can be obtained. Similarly, in the above-mentioned second arrangement example to the seventh arrangement example, the seam portion 4 can also be a gap.

[0209] <Conclusion> As described above, for example, the light detecting device 100 in which the dummy chip 2D is arranged is defined as follows. Fig.71 , Fig.74 , Fig.77 , Fig.80 , Fig.83 , Fig.86 , Fig.89 , Fig.93 As described in the above description, in a plan view (when viewed in the negative direction of the Z axis), the dummy chip 2D may extend in a manner facing the side surface of the chip 2, and may have the following length in the extending direction (length H D , length W D ): This length is at least half the length (length H, length W) of the side surface of the chip 2 facing the dummy chip 2D. D ≥H / 2, W D ≥W / 2). When the dummy chip 2D has a certain length in this way, it is very easy to obtain the effect of the dummy chip 2D, that is, it is very easy to obtain the effect of making the extension direction of the joint portion 4 close to the chip 2 and the height direction of the chip 2 (positive direction of the Z axis) of the dummy chip 2D.

[0210] As reference Fig.71 , Fig.74 , Fig.77 , Fig.83 , Fig.89 , Fig.93 As described in FIG. 1 and FIG. 2 , in a plan view, the dummy chip 2D may be arranged to sandwich the chip 2. The dummy chip 2D may include two or more dummy chips 2D. This can expand the area where the effect of the dummy chip 2D can be achieved, compared with, for example, a case where only one dummy chip 2D facing one side of the chip 2 is provided.

[0211] As reference Fig.70 and Fig.71 As described in the above, the material of the dummy chip 2D may include the same material as the material of the chip 2. In addition, the dummy chip 2D may have the same height (length in the Z-axis direction) as the height of the chip 2. For example, by using such a dummy chip 2D, the extending direction of the joint portion 4 can be made close to the height direction (Z-axis direction) of the chip 2 and the dummy chip 2D.

[0212] As reference Fig.86 As described in the above, the chip may include two or more chips. For example, even in such a multi-chip structure, the effect of the dummy chip 2D can be obtained.

[0213] As reference Fig.74 and Fig.89 As described in FIG. 1 and FIG. 2 , in a plan view, the dummy chip 2D may extend continuously so as to surround the chip 2. This structure can maximize the effect of the dummy chip 2D.

[0214] As reference Fig.77 and Fig.89 As described in the embodiments of the present invention, when the light detection device 100 is observed from the side (observed along the X-axis direction or the Y-axis direction), the dummy chip 2D (for example, the dummy chip 2D-1, the dummy chip 2D-2, the dummy chip 2D-3 and the dummy chip 2D-4) can have a side (for example, the side 2D-1a, the side 2D-2a, the side 2D-3a and the side 2D-4a) exposed from the buried layer 3. With this structure, the dummy chip 2D can be arranged at the outermost side of the light detection device 100. For example, this makes it easy to ensure an area for setting the chip 2. In addition, since the dummy chips 2D of the light detection devices 100 adjacent to each other can be concentrated on the wafer 200, manufacturing becomes easy.

[0215] 21. Sixteenth Implementation Plan Fig.94 16 is a diagram showing an example of a schematic configuration of a light detecting device according to the sixteenth embodiment. The light detecting device 100 includes a sealing layer 5-2 instead of the sealing layer 5. In this example, the light detecting device 100 does not include the auxiliary layer 6. The supporting substrate 7 is bonded (laminated) via the sealing layer 5-2.

[0216] The buried layer 3 is provided to cover the side surface of the chip 2. The front surface 2a of the chip 2 is exposed from the buried layer 3. At least a portion of the joint portion 4 is filled with a material different from that of the buried layer 3. In the present example, the extension portion 5a described so far extends into the joint portion 4 to fill at least a portion of the joint portion 4.

[0217] The sealing layer 5-2 is provided to cover the buried layer 3 and the joint portion 4 and to cover the front surface 2a of the chip 2. The sealing layer 5-2 is in contact with not only the front surface 3a of the buried layer 3 but also the front surface 2a of the chip 2.

[0218] The thermal conductivity of the sealing layer 5-2 is higher than that of silicon (Si). The portion to which the heat from the chip 2 is transferred is easily thermally connected to the outside through the sealing layer 5-2 (heat is easily exposed, thereby improving heat dissipation, etc.). For example, if a metal material is used in the buried layer 3 to improve the heat dissipation of the buried layer 3, leakage may occur between the metal material and the chip 2, thereby reducing the reliability of the device. On the contrary, by using the sealing layer 5-2 to improve heat dissipation, the reliability of the device can be improved while suppressing leakage.

[0219] 22. Seventeenth Implementation Plan Fig.95 1 is a diagram showing an example of a schematic configuration of a light detecting device according to the seventeenth embodiment. The light detecting device 100 includes the above-mentioned sealing layer 5-2 instead of the above-mentioned auxiliary layer 6. Two sealing layers, namely, the sealing layer 5 and the sealing layer 5-2 are provided. The sealing layer 5 is a first sealing layer provided to cover the buried layer 3 and the joint portion 4. The sealing layer 5-2 is a second sealing layer provided to cover the sealing layer 5. The supporting substrate 7 is bonded via the sealing layer 5-2. In this way, heat dissipation can also be improved by using the sealing layer 5-2.

[0220] 23. Eighteenth Implementation Plan Fig.96 1 is a diagram showing an example of a schematic configuration of a light detecting device according to the eighteenth embodiment. Fig.94 The configuration is different in that the light detecting device 100 does not include a sealing layer 5 - 2 but includes a sealing layer 5 - 3 .

[0221] The sealing layer 5-3 is a metal layer. Examples of the material of the metal layer include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), etc. The support substrate 7 is bonded via the sealing layer 5-3. In this way, heat dissipation can also be improved by using the sealing layer 5-3 as a metal layer.

[0222] 24. Nineteenth Implementation Plan Fig.97 19 is a diagram showing an example of a schematic configuration of a light detecting device according to the nineteenth embodiment. Fig.94 The configuration is different in that the light detecting device 100 does not include a sealing layer 5 - 2 but includes a sealing layer 5 - 4 .

[0223] The sealing layer 5-4 includes an insulating layer 50 and a sealing layer 5-2 that extend continuously along the plane direction (XY plane direction) of the sealing layer 5-4. The insulating layer 50 is the first part of the sealing layer 5-4, which covers the buried layer 3 of both the buried layer 3 and the chip 2. The sealing layer 5-2 is the second part, which is set to cover the buried layer 3 of both the buried layer 3 and the chip 2.

[0224] The insulating layer 50 has insulating properties as its name indicates. Examples of the material of the insulating layer 50 include SiOx, SiNx, SiON, SiOC, SiCN, SiC, etc. As described above, the thermal conductivity of the sealing layer 5-2 is higher than that of silicon. The sealing layer 5-2 can be arranged to contact the front side 2a of the chip 2. In this way, heat dissipation can also be improved by using the sealing layer 5-2.

[0225] 25. Twentieth Implementation Plan Fig.98 FIG. 2 is a diagram showing an example of a schematic configuration of a light detecting device according to a twentieth embodiment. Fig.94 The difference from the structure of the seventh embodiment is that the light detection device 100 does not include the sealing layer 5-2 but includes an additional layer 9. Note that the additional layer 9 here can be different from the seventh embodiment ( Figure 7 ) is to be understood differently.

[0226] The additional layer 9 is provided between the chip 2 and the buried layer 3. More specifically, the additional layer 9 is provided to cover the substrate 1 and the chip 2. The buried layer 3 is provided to cover the additional layer 9 except for the portion of the additional layer 9 located above the chip 2.

[0227] The additional layer 9 in this embodiment is a metal layer (also referred to as a barrier metal). Examples of the material of the metal layer include titanium (Ti), tantalum (Ta), and the like.

[0228] The inside of the joint portion 4 is filled with the extension portion 5a, and the joint portion 4 is covered with the additional layer 9. The support substrate 7 is joined by the buried layer 3 and the additional layer 9. The support substrate 7 and the additional layer 9 can function as a sealing layer covering the buried layer 3, the joint portion 4 and the chip 2. In this way, heat dissipation can also be improved by using the additional layer 9 as a metal layer. Since the auxiliary layer 6 is removed, the number of manufacturing processes can be reduced or the thickness of the device can be reduced (the height can be reduced).

[0229] 26. Twenty-first Implementation Plan Fig.99 21 is a diagram showing an example of a schematic configuration of a light detecting device according to the twenty-first embodiment. Fig.94 Compared with the structure of FIG. 5 , a part of the joint portion 4 is filled with the extension portion 5a, but the rest is a gap 4a. In this structure, heat dissipation can also be improved by using the sealing layer 5-2. The stress between the chips 2 can be relieved by the presence of the gap 4a. In addition, in the above-mentioned Figures 95 to 98 In the configuration of FIG. 4 , a portion of the joint portion 4 may also be filled with the extension portion 5 a , and the remaining portion may also be the gap 4 a .

[0230] 27. Implementation Plan 22 Fig.100 2 is a diagram showing an example of a schematic configuration of a light detecting device according to the twenty-second embodiment. Fig.94 The difference from the structure of FIG. 1 is that the light detection device 100 includes a compound layer 14 .

[0231] The compound layer 14 is disposed between the chip 2 and the sealing layer 5-2, and is also disposed in the sealing layer 5-2. For example, the compound layer 14 may be a silicide layer. Examples of the material of the compound layer 14 may include semiconductor materials such as silicon (Si) and metal materials.

[0232] Two compound layers 14 are provided. The first compound layer 14 is provided on the front surface 2a of the chip 2. The sealing layer 5-2 is provided to cover the buried layer 3, the joint portion 4 and the first compound layer 14. The second compound layer 14 is provided to cover the sealing layer 5-2. The support substrate 7 is bonded via the compound layer 14. In this way, heat dissipation can also be improved by using the compound layer 14 including a metal material.

[0233] 28. Twenty-third Implementation Plan Fig.101 23 is a diagram showing an example of a schematic configuration of a light detecting device according to the twenty-third embodiment. Fig.94 The structure is different in that the light detection device 100 does not include a sealing layer 5-2 but includes a sealing layer 5-5. The sealing layer 5-5 is a layer that has a metal structure such as wiring (including a passage) arranged in an insulator. While providing a heat dissipation path, the metal structure can also function as a wiring or a pad. An example of the metal structure is represented by the reference numeral as a passage 5-5v. In this way, heat dissipation can also be improved by using the sealing layer 5-5. In addition, wiring can be formed at the joint surface between the embedded layer 3 and the supporting substrate 7.

[0234] 29. Application examples of camera devices An example of application of the light detection device 100 according to the sixteenth to twenty-third embodiments described above is an image pickup device. Figure 20 to Figure 23 For example, in the case where the light detecting device 100 according to the sixteenth embodiment is used as an image pickup device, a configuration including the sealing layer 5-2 may be adopted instead of Figure 20 to Figure 22 The sealing layer 5 and the auxiliary layer 6 are provided.

[0235] 30. Example of manufacturing method Figure 102 to Figure 107 1 is a diagram showing an example of a method for manufacturing a light detection device. Figure 102 to Figure 105 The method for obtaining the aforementioned Fig.94 As a premise, it is assumed that the above-mentioned Figures 9 to 12 The manufacturing process is the same manufacturing process as in the manufacturing process.

[0236] like Fig.102 As shown in FIG. 1 , the sealing layer 5 and the buried layer 3 are ground and cleaned. Thus, the front side 2a of the chip 2 is exposed from the buried layer 3. Fig.103 As shown, the sealing layer 5-2 is provided to cover the buried layer 3, the joint portion 4 and the chip 2. Fig.104 As shown, the support substrate 7 is bonded via the sealing layer 5-2 to obtain the aforementioned Fig.94 structure.

[0237] In the aforementioned Fig.103 During the manufacturing process, when the interior of the joint portion 4 is not completely filled with the sealing layer 5 and the joint portion 4 has a gap 4a, the aforementioned Fig.99 In the above-mentioned Fig.102 In the manufacturing process of the present invention, the above-mentioned Fig.95 The structure of Fig.103 In the manufacturing process, when the sealing layer 5-3 (metal layer) is provided to replace the sealing layer 5-2, the aforementioned Fig.96 structure.

[0238] There may be some variation in the position of the bonding surface of the support substrate 7. Specifically, Fig.105 (A) in FIG. 5 shows three types of bonding surfaces, namely, bonding surface B, bonding surface C and bonding surface D. Bonding surface B is located between the support substrate 7 and the sealing layer 5-2. Bonding surface C is located inside the sealing layer 5-2. Bonding surface D is located between the sealing layer 5-2 and the embedding layer 3.

[0239] Fig.105(B), (C) and (D) in the figure schematically show the Z-axis exploded views of the support substrate 7, the sealing layer 5-2 and the buried layer 3 at the bonding surface B, the bonding surface C and the bonding surface D, respectively. A compound (silicide) is generated during the bonding process, and in this case, the aforementioned Fig.100 structure.

[0240] Fig.106 and Fig.107 The method for obtaining the aforementioned Fig.101 As a premise, it is assumed that the above-mentioned Fig.102 The manufacturing process so far.

[0241] like Fig.106 As shown, the sealing layer 5-5 is arranged to cover the buried layer 3, the joint portion 4 and the chip 2. Fig.107 As shown, the supporting substrate 7 is bonded via the sealing layer 5-5 to obtain the aforementioned Fig.101 structure.

[0242] <Conclusion> For example, the light detecting device 100 according to the sixteenth to twenty-third embodiments described above is defined as follows. Fig.94 , Fig.99 As described in the above, at least a part of the joint portion 4 is filled with a material different from that of the embedded layer 3 (e.g., the extension portion 5a), and the sealing layer 5-2 is a layer having a thermal conductivity higher than that of silicon (Si). Even with such a structure, the connection between the joint portion 4 and the outside can be suppressed. In addition, heat dissipation can also be improved.

[0243] As reference Fig.95 As described in the above, the light detection device 100 may include a sealing layer 5 (first sealing layer) provided in a manner covering the buried layer 3 and the joint portion 4 and a sealing layer 5-2 (second sealing layer) provided in a manner covering the sealing layer 5, and the thermal conductivity of the sealing layer 5-2 may be higher than the thermal conductivity of silicon (Si). With this structure, heat dissipation can also be improved.

[0244] As reference Fig.96 As described in the above, the sealing layer 5-3 may be a metal layer. With this structure, heat dissipation can also be improved.

[0245] Reference Fig.97As described in the embodiments of the present invention, the sealing layer 5-4 may include: an insulating layer 50 (a first part of the sealing layer) covering the buried layer 3 of the buried layer 3 and the chip 2; and a sealing layer 5-2 (a second part of the sealing layer) covering the chip 2 of the buried layer 3 and the chip 2. The insulating layer 50 may have insulating properties, and the sealing layer 5-2 may have a thermal conductivity higher than that of silicon (Si). With this structure, heat dissipation can also be improved.

[0246] As reference Fig.98 As described in FIG. 1 and FIG. 2 , the light detection device 100 may include an additional layer 9 disposed between the chip 2 and the buried layer 3 , and the additional layer 9 may be a metal layer. With this configuration, heat dissipation can also be improved.

[0247] As reference Fig.100 As described in the above, the light detection device 100 may include a compound layer 14 disposed between the chip 2 and the sealing layer 5 - 2 , and the compound layer 14 may be a silicide layer. With this configuration, heat dissipation can also be improved.

[0248] As reference Fig.101 As described in the above, the sealing layer 5-5 may be a layer obtained by providing a metal structure (e.g., a via 5-5v, etc.) in an insulator. This structure can also improve heat dissipation. When the support substrate 7 is bonded, wiring may also be formed on its bonding surface.

[0249] 31. Twenty-fourth Implementation Plan Fig.108 and Fig.109 1 is a diagram showing an example of a schematic configuration of a light detecting device according to the twenty-fourth embodiment. Note that the illustration of the supporting substrate 7 is omitted here, and the same applies to the subsequent drawings. The light detecting device 100 includes a sealing layer 5-6 instead of the sealing layer 5. The sealing layer 5-6 is a resin layer. Among the surfaces of the sealing layer 5-6, the surface on the positive direction side of the Z axis is referred to and illustrated as the front surface 5-6a.

[0250] Fig.109 An enlarged view of a portion including a chip 2 and a buried layer 3 and a sealing layer 5 located on the upper portion of the chip 2 is schematically shown. The buried layer 3 has a concave-convex shape at the front surface 3a. Specifically, the front surface 3a of the buried layer 3 has a concave portion 3c1 and a convex portion 3c2. The concave portion 3c1 has a concave shape that is concave downward (in the positive direction of the Z axis). The convex portion 3c2 has a convex shape that protrudes upward (in the positive direction of the Z axis).

[0251] The sealing layer 5-6 is a resin layer, which is arranged to fill the concave portion 3c1 and cover the concave portion 3c1 and the convex portion 3c2. The resin layer can be an oxide layer or an organic layer. For example, the oxide layer can be an oxide-based insulating film or an oxide-based bonding film. For example, the organic layer can have a heat resistance temperature of 400°C or more. Examples of materials of such an organic layer include polyimide, siloxane, silicone, etc. Even if exposed to heat of about 400°C in a subsequent step, the layer can be heat-resistant.

[0252] The sealing layer 5-6 can be applied to the embedding layer 3 in the form of a coating liquid during manufacturing. This makes it easy to fill the recess 3c1 with the sealing layer 5-6 and to extend the sealing layer 5-6 into the joint 4. Since this is not a conformal film forming method, the front surface after coating becomes a surface with a higher flatness than before coating. Fig.109 In the example shown, the front surface 5-6a of the sealing layer 5-6 is a flattened surface. That is, the shapes of the concave portions 3c1 and the convex portions 3c2 at the front surface 3a of the embedding layer 3 are flattened by the sealing layer 5-6, thereby obtaining the front surface 5-6a as a flattened surface.

[0253] <Example of Manufacturing Method> Figures 110 to 114 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.110 As shown in FIG. 1 , a chip 2 is disposed on a substrate 1, and a buried layer 3 is disposed to cover the chip 2. A joint portion 4 appears in the buried layer 3. Fig.111 As shown, the buried layer 3 on the chip 2 is removed by a photolithography process including dry etching, etc., in such a way that the buried layer 3 located at the upper part of the corner of the chip 2 is left. The buried layer 3 remaining at the upper part of the corner of the chip 2 is referred to as and is shown as a corner 3h. By leaving the corner 3h, the outer part of the chip 2 can be protected, and the buried layer 3 outside the chip 2 can be prevented from falling off.

[0254] like Fig.112 As shown, a buried layer 3 is further provided. In this example, a joint portion 4 also appears in the buried layer 3 located on the upper part of the chip 2. Fig.113 As shown, the corner 3h is removed by CMP (chemical mechanical polishing). The CMP here is different from ordinary CMP in terms of the composition of the slurry, etc., and the CMP here ends when the layer is flattened to a certain extent (self-stop CMP). Fig.114 As shown in FIG. 1 , the sealing layer 5-6 is provided to cover the embedded layer 3 and the joint portion 4. The sealing layer 5-6 is provided by coating with a material (resin material). At this time, the material of the sealing layer 5-6 extends into the joint portion 4, and the extended portion becomes the extended portion 5a of the sealing layer 5-6. Fig.109The recess 3c1 at the front surface 3a of the buried layer 3 is filled with the sealing layer 5-6. Thereafter, by providing the auxiliary layer 6 to cover the sealing layer 5, the aforementioned Fig.108 and Fig.109 structure.

[0255] In the above manufacturing method, photolithography and subsequent film formation of the buried layer 3 can be omitted ( Fig.111 and Fig.112 process).

[0256] <Example of Manufacturing Method> Figures 115 to 119 FIG. 1 is a diagram showing an example of a method for manufacturing a light detection device. Figures 110 to 114 Compared with the manufacturing method of the present invention, a CMP process is added before setting the sealing layer 5-6. As a premise, it is assumed that the above-mentioned Fig.111 manufacturing process.

[0257] like Fig.115 As shown, a buried layer 3 is further provided. The thickness (length in the Z-axis direction) of the buried layer 3 added here can be greater than the aforementioned Fig.112 The thickness of the buried layer 3 in Fig.116 As shown, the corner 3h is removed by self-stop CMP. Fig.117 As shown, the top of the buried layer 3 is ground and cleaned by CMP. In this CMP, the buried layer 3 in the portion corresponding to the corner of the chip 2 has roundness (is rounded).

[0258] like Fig.118 As shown, the sealing layer 5-6 is arranged to cover the embedded layer 3 and the joint portion 4. Fig.119 As shown, the auxiliary layer 6 is arranged to cover the sealing layer 5. In addition to the fact that the buried layer 3 at the portion corresponding to the corner of the chip 2 is rounded, the same as described above can be obtained. Fig.108 and Fig.109 The construction is the same as the construction of .

[0259] In the above-mentioned manufacturing method, the photolithography, the subsequent film formation of the buried layer 3, and the self-stop CMP process can also be omitted ( Fig.111 , Fig.115 and Fig.116 process).

[0260] When the top of the buried layer 3 is polished by CMP, the front surface 3a of the buried layer 3 may have a concave portion 3c1 and a convex portion 3c2. This will be referred to Fig.120 and Fig.121 to explain.

[0261] Fig.120 and Fig.1212 is a diagram showing an example of CMP. For easy understanding, the joint portion 4 is omitted from illustration.

[0262] Fig.120 The above-mentioned Fig.113 and Fig.116 In the present example, the upper portion of the buried layer 3 (e.g., an oxide film such as SiO2) is ground using a slurry containing cerium oxide abrasive grains Pa and an additive Ad to remove the corner 3h. Complete flattening may be difficult, and in the present example, the buried layer 3 has a concave portion 3c1 and a convex portion 3c2. For example, the remaining portion of the corner 3h that is not scraped and remains (corner residue), the slits generated between the corner residues, and the joint portion 4 may become the concave portion 3c1 and the convex portion 3c2.

[0263] Fig.121 The schematic diagram shows the Fig.117 The CMP executed in Fig.121 As shown in (A) in FIG. 1 , the top of the embedded layer 3 is polished using a polishing pad. The cerium oxide abrasive grains Pa are not adsorbed to the embedded layer 3 but exist in a free state. Fig.121 As shown in (B) in FIG. 1 , slurry is accumulated in the concave portion 3c1 and the convex portion 3c2 of the buried layer 3 located above the corner of the chip 2, which increases the local stress and allows grinding. The effect of the additive Ad hinders the grinding of the flat portion at the top of the convex portion 3c2 having a relatively wide width (length in the XY plane direction).

[0264] For example, due to the above reasons, during the manufacturing process, the buried layer 3 develops the concave portion 3c1 and the convex portion 3c2. By setting the sealing layer 5-6 (resin layer) to fill the concave portion 3c1 and cover the concave portion 3c1 and the convex portion 3c2, the concave portion 3c1 and the convex portion 3c2 are smoothed, thereby obtaining the front surface 5-6a as a flattened surface.

[0265] 32. Twenty-fifth Implementation Plan Fig.122 1 is a diagram showing an example of a schematic configuration of a light detecting device according to the twenty-fifth embodiment. The light detecting device 100 includes a resin layer 15 instead of the sealing layer 5. Like the above-mentioned sealing layers 5-6, the resin layer 15 is an oxide layer or an organic layer. The material of the resin layer 15 can be the same as that of the sealing layers 5-6.

[0266] The resin layer 15 is provided between the chip 2 and the embedding layer 3. In this example, the resin layer 15 is provided to cover the substrate 1 and to cover the side surfaces of the chip 2. However, the resin layer 15 may cover not only the side surfaces of the chip 2 but also the front surface 2a thereof.

[0267] By covering the chip 2 with the resin layer 15, the shape of the chip 2 portion (for example, the shape of the step portion formed by the chip 2 and the substrate 1) becomes gentle. Therefore, it is unlikely that the joint portion 4 will appear. Even if the joint portion 4 appears, the auxiliary layer 6 functions as a sealing layer covering the embedded layer 3 and the joint portion 4, so that the connection between the joint portion 4 and the outside can be suppressed as described above.

[0268] <Example of Manufacturing Method> Figures 123 to 128 1 is a diagram showing an example of a method for manufacturing a light detection device. Fig.123 As shown in FIG. 1 , the chip 2 is disposed on the substrate 1, and the resin layer 15 is disposed to cover the chip 2. Fig.124 As shown in FIG. 1 , the embedding layer 3 is provided to cover the resin layer 15 (in this example, also covering the front surface 2a of the chip 2). In this example, no joint portion 4 appears in the embedding layer 3. Fig.125 As shown, the buried layer 3 is removed by a photolithography process including dry etching, etc., in such a manner that the corner portion 3h remains.

[0269] like Fig.126 As shown, a buried layer 3 is further provided. Fig.127 As shown in FIG. 3 , the corner 3h is removed by CMP (self-stop CMP). Fig.128 As shown, the top of the buried layer 3 is ground and cleaned by CMP. Thereafter, by setting the auxiliary layer 6 to cover the buried layer 3, the aforementioned Fig.122 structure.

[0270] In the above-mentioned manufacturing method, the photolithography, the subsequent film formation of the buried layer 3, and the self-stop CMP process can also be omitted ( Figures 125 to 127 process).

[0271] <Conclusion> For example, the light detecting device 100 according to the twenty-fourth embodiment and the twenty-fifth embodiment described above is defined as follows. Fig.108 and Fig.109 As described in the above, the sealing layer 5-6 may be a resin layer (e.g., an oxide layer or an organic layer). The front surface 3a of the buried layer 3 may have a recessed portion 3c1, and the sealing layer 5-6 may be arranged to fill the recessed portion 3c1. The front surface 5-6a of the sealing layer 5-6 may be a flattened surface. Thus, the recessed portion 3c1 at the front surface 3a of the buried layer 3 can be flattened, thereby obtaining a flattened surface (front surface 5-6a).

[0272] The sealing layer 5-6 as an organic layer may have a heat resistance temperature of 400° C. or more. The material of the organic layer may include at least one of polyimide, siloxane, and silicone. For example, the layer can withstand heat even when exposed to heat of about 400° C. in a subsequent step.

[0273] As reference Fig.122 As described in the above description, the light detecting device 100 may include a resin layer 15 (for example, an oxide layer or an organic layer) provided between the chip 2 and the embedding layer 3. This can suppress the occurrence of the joint portion 4.

[0274] The resin layer 15 may have the same properties as those of the sealing layers 5-6 described above. For example, the resin layer 15 as an organic layer may have a heat resistance temperature of 400° C. or higher. The material of the organic layer may include at least one of polyimide, siloxane, and silicone. Thus, for example, even if the layer is exposed to heat of about 400° C. in a subsequent step, the layer can be heat-resistant.

[0275] The embodiments of the present disclosure have been described above. However, the technical scope of the present disclosure is not limited to the above embodiments, and various modifications can be made without departing from the scope of protection of the present disclosure. In addition, it is allowed to appropriately combine the constituent elements in different embodiments and modifications.

[0276] Note that this technology can also have the following technical solutions. (1) A light detection device comprising: a substrate including a light detecting element; A chip is disposed on the substrate; a buried layer arranged to cover the chip; a seam portion that appears in the embedded layer and extends to the front surface of the embedded layer; and A sealing layer is provided to cover the embedding layer and the joint portion. (2) The light detection device according to (1), further comprising: The supporting substrate is located on a side opposite to the substrate via the sealing layer, and the supporting substrate is configured to directly or indirectly support the sealing layer. (3) The light detection device according to (1) or (2), wherein: At least a portion of the seam portion is a gap. (4) The light detection device according to any one of (1) to (3), wherein: The sealing layer includes an extending portion extending into the seam portion in a manner filling at least a portion of the seam portion. (5) The light detection device according to any one of (1) to (4), wherein: The sealing layer is made of a material having low permeability. (6) The light detection device according to any one of (1) to (5), wherein: The material of the sealing layer includes a low Young's modulus material. (7) The light detection device according to any one of (1) to (6), further comprising: The side wall portion is configured to cover the side surface of the chip. (8) The light detection device according to any one of (1) to (7), wherein: The chip includes a first chip and a second chip which are arranged separately from each other. The seam portion includes a first seam portion that occurs due to the first chip and a second seam portion that occurs due to the second chip, and The first seam portion and the second seam portion are connected to each other. (9) The light detection device according to any one of (1) to (8), further comprising: An additional layer is disposed between the chip and the buried layer. (10) The light detection device according to any one of (1) to (9), further comprising: An auxiliary layer is arranged to cover the sealing layer. (11) The light detection device according to (10), wherein: The auxiliary layer has a stacked structure. (12) The light detection device according to any one of (1) to (11), wherein: The chip includes at least one of a logic chip, a memory chip, and an AI (artificial intelligence) chip. (13) The light detection device according to any one of (1) to (12), wherein: The light detection device is an image pickup device configured to include a plurality of pixels. (14) The light detection device according to (13), further comprising: a filter layer disposed on a side opposite to the chip and the embedded layer across the substrate; and The lens layer is provided on a side opposite to the substrate across the filter layer. (15) The light detection device according to any one of (1) to (14), further comprising: An additional substrate is disposed between the substrate and the buried layer. (16) The light detection device according to any one of (1) to (15), wherein: The chip includes two chips arranged adjacent to each other with a space therebetween, and The buried layer includes wiring disposed between the two chips. (17) The light detection device according to any one of (1) to (16), further comprising: a supporting substrate located on a side opposite to the substrate across the sealing layer, and the supporting substrate is configured to directly or indirectly support the sealing layer; and A through via is configured to penetrate the buried layer, the sealing layer, and the support substrate. (18) The light detection device according to any one of (1) to (17), wherein: The chip comprises: a first chip; and A second chip, wherein the thickness of the second chip is greater than the thickness of the first chip, and the seam portion comprises: A first seam portion extending from the first chip toward the front surface of the buried layer; and a second seam portion extending from the second chip toward the front surface of the buried layer, and The second seam portion extends closer to the front surface of the embedded layer than the first seam portion. (19) The light detection device according to any one of (1) to (18), wherein: The chip comprises: a first chip; and The second chip and the third chip are stacked in sequence, The overall thickness of the second chip and the third chip is greater than the thickness of the first chip. The seam portion comprises: A first seam portion extending from the first chip toward the front surface of the buried layer; and a second seam portion extending from the second chip toward the front surface of the buried layer, and The second seam portion extends closer to the front surface of the embedded layer than the first seam portion. (20) The light detection device according to (18) or (19), wherein: The sealing layer includes an extending portion extending into the second seam portion in a manner filling at least a portion of the second seam portion. (21) The light detection device according to any one of (18) to (20), wherein: The first seam portion does not reach the front surface of the embedded layer, and The second seam portion reaches the front surface of the embedding layer. (22) The light detection device according to any one of (1) to (21), wherein: The chip includes a lower chip and an upper chip aligned in a height direction, The light detection device further includes a bonding layer disposed between the lower chip and the upper chip, The buried layer comprises: a lower buried layer, which is arranged to cover the side surfaces of the lower chip; and an upper buried layer, which is arranged to cover the upper chip and the bonding layer, and the seam portion comprises: a lower seam portion which appears in the lower buried layer and extends to the front surface of the lower buried layer; and an upper seam portion which appears in the upper buried layer and extends to the front surface of the upper buried layer, The bonding layer is provided to cover the lower embedding layer and the lower seam portion, and The sealing layer is provided to cover the upper embedding layer and the upper seam portion. (23) The light detection device according to (22), wherein: The chip further includes: a lower chip and a dummy chip disposed at two sides opposite to each other across the bonding layer, and The upper buried layer is provided to cover the upper chip, the dummy chip, and the bonding layer. (24) The light detection device according to any one of (1) to (23), wherein: The sealing layer comprises: A first portion covering the seam portion; and a second portion which does not cover the seam portion, and The back surface of the first portion is located below the back surface of the second portion. (25) The light detection device according to (24), wherein: The front surface of the first part and the front surface of the second part are located at the same height. (26) The light detection device according to (24), further comprising: an auxiliary layer, which is arranged to cover the sealing layer, wherein the front face of the second portion is located above the front face of the first portion, and The front side of the auxiliary layer is a planarized side. (27) The light detection device according to any one of (1) to (26), wherein: The sealing layer has a laminated structure including a laminate of a plurality of layers. (28) The light detection device according to (27), wherein: The plurality of layers of the sealing layer include an inorganic layer and an organic layer. (29) The light detection device according to any one of (1) to (28), further comprising: a dummy chip disposed adjacent to the chip at a distance therefrom, The buried layer is configured to cover the chip and the dummy chip, and The joint portion extends to the front surface of the buried layer in a portion between the chip and the dummy chip. (30) The light detection device according to (29), wherein: The joint portion extends along a height direction of the chip and the dummy chip. (31) The light detection device according to (29) or (30), wherein: The chip includes two chips that are separated from each other, and The dummy chip is arranged between the two chips. (32) The light detection device according to any one of (1) to (31), wherein: The chip has a shape whose width decreases toward the front side of the chip. (33) The light detection device according to (32), wherein: The edge portion of the chip has a tapered shape or a rounded shape at the front surface of the chip. (34) The light detection device according to (32) or (33), wherein: The joint portion extends along a height direction of the chip. (35) The light detection device according to any one of (1) to (34), wherein: The seam portion has a shape in which a width thereof changes as the seam portion advances in the extending direction. (36) The light detection device according to (35), wherein: The seam portion comprises: a central portion located at the center in the extending direction of the seam portion; and an end portion which is located at a terminal end in the extending direction of the seam portion, and The width of the central portion is greater than the width of the end portions. (37) The light detection device according to any one of (29) to (36), wherein: The dummy chip extends to face a side surface of the chip in a plan view, and a length of the dummy chip in an extending direction of the dummy chip is more than half a length of the side surface of the chip facing the dummy chip. (38) The light detection device according to any one of (29) to (37), wherein: The dummy chips are arranged so as to sandwich the chip in a plan view. (39) The light detection device according to any one of (29) to (38), wherein: The dummy chip includes more than two dummy chips. (40) The light detection device according to any one of (29) to (39), wherein: The material of the dummy chip includes the same material as that of the chip. (41) The light detection device according to any one of (29) to (40), wherein: The height of the dummy chip is equal to the height of the chip. (42) The light detection device according to any one of (29) to (41), wherein: The chip includes more than two chips. (43) The light detection device according to any one of (29) to (42), wherein: The dummy chip continuously extends in a manner surrounding the chip in a plan view. (44) The light detection device according to any one of (29) to (43), wherein: When the light detecting device is viewed from the side, the dummy chip has a side surface exposed from the buried layer. (45) The light detection device according to any one of (1) to (44), wherein: At least a portion of the joint portion is filled with a material different from that of the embedding layer, and The sealing layer is a layer having a thermal conductivity higher than that of silicon. (46) The light detection device according to (45), further comprising: A first sealing layer, which is arranged to cover the embedded layer and the joint portion; and a second sealing layer, which is arranged to cover the first sealing layer, Wherein, the thermal conductivity of the second sealing layer is higher than the thermal conductivity of silicon. (47) The light detection device according to (45) or (46), wherein: The sealing layer is a metal layer. (48) The light detection device according to any one of (45) to (47), wherein: The sealing layer comprises: A first portion covering the buried layer among the buried layer and the chip; and a second portion covering the chip among the buried layer and the chip, The first portion has insulating properties, and The second portion has a thermal conductivity higher than a thermal conductivity of silicon. (49) The light detection device according to any one of (45) to (48), further comprising: an additional layer disposed between the chip and the buried layer, Wherein, the additional layer is a metal layer. (50) The light detection device according to any one of (45) to (49), further comprising: a compound layer disposed between the chip and the sealing layer, Wherein, the compound layer is a silicide layer. (51) The light detection device according to any one of (45) to (50), wherein the sealing layer is a layer having a metal structure disposed in an insulator. (52) The light detection device according to any one of (1) to (51), wherein the sealing layer is a resin layer. (53) The light detection device according to (52), wherein: The front surface of the buried layer has a recessed portion, and The sealing layer is configured to fill the recess. (54) The light detection device according to (52) or (53), wherein the front surface of the sealing layer is a flattened surface. (55) The light detection device according to any one of (52) to (54), wherein the resin layer is an oxide layer or an organic layer. (56) The light detection device according to (55), wherein: The organic layer has a heat resistance temperature of 400° C. or higher. (57) The light detection device according to (56), wherein: The material of the organic layer includes at least one of polyimide, siloxane, and silicone. (58) The light detection device according to any one of (1) to (57) further includes: a resin layer provided between the chip and the embedded layer. (59) The light detection device according to (58), wherein: The resin layer is an oxide layer or an organic layer. (60) The light detection device according to (59), wherein: The organic layer has a heat resistance temperature of 400° C. or higher. (61) The light detection device according to (60), wherein: The material of the organic layer includes at least one of polyimide, siloxane, and silicone. Description of Reference Numerals

[0277] 100: Light detection device 1: Substrate 1a: Front 1b: Back side 1p: Light detection element 2: Chip 2a: Front 2b: Mounting surface 2c: Side 2d: Side 2e: Side 2f: Side 2v: Through Passage 21: Central 22: Edge 2D: Virtual Chip 3: Buried layer 3a: Front 3b: Back side 3h: Corner 3v: Through Passage 3c1: concave part 3c2: convex part 4: Seam 41: end 42: Central Department 43: End 4a: Gap 5: Sealing layer 5a: Extension 51: Part 1 51a: Front 51b: Back 52: Part 2 52a: Front 52b: Back 53: Inorganic layer 54: Organic layer 5-2: Sealing layer 5-3: Sealing layer 5-4: Sealing layer 5-5: Sealing layer 5-5v: Passage 5-6: Sealing layer 6: Auxiliary layer 61: Layer 62: Layer 63: Layer 6a: Front 7: Support substrate 7a: Front 7b: Back 8: Side wall 9: Additional Layers L: Wiring 10: Filter layer 11: Lens layer 11a: Lens 12: Additional substrate 12a: Front 12b: Back 12v: Through-path V: Through passage 13: Bonding layer 14 Compound layer 15: Resin layer 200: Wafer Ad: Additive Pa: Cerium dioxide abrasive SL: Score

Claims

1. A light detection device, comprising: a substrate including a light detecting element; A chip is disposed on the substrate; a buried layer arranged to cover the chip; a seam portion, which appears in the embedded layer and extends to the front surface of the embedded layer; as well as A sealing layer is provided to cover the embedding layer and the joint portion.

2. The light detection device according to claim 1, further comprising: The supporting substrate is located on a side opposite to the substrate via the sealing layer, and the supporting substrate is configured to directly or indirectly support the sealing layer.

3. The light detection device according to claim 1, wherein: At least a portion of the seam portion is a gap.

4. The light detection device according to claim 1, wherein: The sealing layer includes an extending portion extending into the seam portion in a manner filling at least a portion of the seam portion.

5. The light detection device according to claim 1, wherein: The sealing layer is made of a material having low permeability.

6. The light detection device according to claim 1, wherein: The material of the sealing layer includes a low Young's modulus material.

7. The light detection device according to claim 1, further comprising: The side wall portion is configured to cover the side surface of the chip.

8. The light detection device according to claim 1, wherein The chip includes a first chip and a second chip which are arranged separately from each other. The seam portion includes a first seam portion that occurs due to the first chip and a second seam portion that occurs due to the second chip, and The first seam portion and the second seam portion are connected to each other.

9. The light detection device according to claim 1, further comprising: An additional layer is disposed between the chip and the buried layer.

10. The light detection device according to claim 1, further comprising: An auxiliary layer is arranged to cover the sealing layer.

11. The light detection device according to claim 10, wherein: The auxiliary layer has a stacked structure.

12. The light detection device according to claim 1, wherein The chip includes at least one of a logic chip, a memory chip, and an AI (artificial intelligence) chip.

13. The light detection device according to claim 1, wherein The light detection device is an image pickup device configured to include a plurality of pixels.

14. The light detection device according to claim 13, further comprising: A filter layer is arranged on a side opposite to the chip and the embedded layer across the substrate; and The lens layer is provided on a side opposite to the substrate across the filter layer.

15. The light detection device according to claim 1, further comprising: An additional substrate is disposed between the substrate and the buried layer.

16. The light detection device according to claim 1, wherein The chip includes two chips arranged adjacent to each other with a space therebetween, and The buried layer includes wiring disposed between the two chips.

17. The light detection device according to claim 1, further comprising: a supporting substrate located on a side opposite to the substrate across the sealing layer, and the supporting substrate is configured to directly or indirectly support the sealing layer; and A through via is configured to penetrate the buried layer, the sealing layer, and the support substrate.

18. The light detection device according to claim 1, wherein The chip comprises: a first chip; and A second chip, wherein the thickness of the second chip is greater than the thickness of the first chip, and the seam portion comprises: A first seam portion extending from the first chip toward the front surface of the buried layer; and a second seam portion extending from the second chip toward the front surface of the buried layer, and The second seam portion extends closer to the front surface of the embedded layer than the first seam portion.

19. The light detection device according to claim 1, wherein: The chip comprises: a first chip; and The second chip and the third chip are stacked in sequence, The overall thickness of the second chip and the third chip is greater than the thickness of the first chip. The seam portion comprises: A first seam portion extending from the first chip toward the front surface of the buried layer; and a second seam portion extending from the second chip toward the front surface of the buried layer, and The second seam portion extends closer to the front surface of the embedded layer than the first seam portion.

20. The light detection device according to claim 18, wherein The sealing layer includes an extending portion extending into the second seam portion in a manner filling at least a portion of the second seam portion.

21. The light detection device according to claim 18, wherein The first seam portion does not reach the front surface of the embedded layer, and The second seam portion reaches the front surface of the embedding layer.

22. The light detection device according to claim 1, wherein The chip includes a lower chip and an upper chip aligned in a height direction, The light detection device further includes a bonding layer disposed between the lower chip and the upper chip, The buried layer comprises: a lower buried layer, which is arranged to cover the side surfaces of the lower chip; and an upper buried layer, which is arranged to cover the upper chip and the bonding layer, and the seam portion comprises: a lower seam portion which appears in the lower buried layer and extends to the front surface of the lower buried layer; and an upper seam portion which appears in the upper buried layer and extends to the front surface of the upper buried layer, The bonding layer is provided to cover the lower embedding layer and the lower seam portion, and The sealing layer is provided to cover the upper embedding layer and the upper seam portion.

23. The light detection device according to claim 22, wherein: The chip further includes: a lower chip and a dummy chip disposed at two sides opposite to each other across the bonding layer, and The upper buried layer is provided to cover the upper chip, the dummy chip, and the bonding layer.

24. The light detection device according to claim 1, wherein The sealing layer comprises: A first portion covering the seam portion; and a second portion which does not cover the seam portion, and The back surface of the first portion is located below the back surface of the second portion.

25. The light detection device according to claim 24, wherein: The front surface of the first part and the front surface of the second part are located at the same height.

26. The light detection device according to claim 24, further comprising: an auxiliary layer, which is arranged to cover the sealing layer, wherein the front face of the second portion is located above the front face of the first portion, and The front side of the auxiliary layer is a planarized side.

27. The light detection device according to claim 1, wherein The sealing layer has a laminated structure including a laminate of a plurality of layers.

28. The light detection device according to claim 27, wherein The plurality of layers of the sealing layer include an inorganic layer and an organic layer.

29. The light detection device according to claim 1, further comprising: a dummy chip arranged adjacent to the chip at a distance therefrom, The buried layer is configured to cover the chip and the dummy chip, and The joint portion extends to the front surface of the buried layer in a portion between the chip and the dummy chip.

30. The light detection device according to claim 29, wherein The joint portion extends along a height direction of the chip and the dummy chip.

31. The light detection device according to claim 29, wherein The chip includes two chips that are separated from each other, and The dummy chip is arranged between the two chips.

32. The light detection device according to claim 1, wherein The chip has a shape whose width decreases toward the front side of the chip.

33. The light detection device according to claim 32, wherein: The edge portion of the chip has a tapered shape or a rounded shape at the front surface of the chip.

34. The light detection device according to claim 32, wherein: The joint portion extends along a height direction of the chip.

35. The light detection device according to claim 1, wherein The seam portion has a shape in which a width thereof changes as the seam portion advances in the extending direction.

36. The light detection device according to claim 35, wherein The seam portion comprises: a central portion located at the center in the extending direction of the seam portion; and An end portion is located at a terminal end in the extending direction of the seam portion, and a width of the central portion is greater than a width of the end portion.

37. The light detection device according to claim 29, wherein: The dummy chip extends to face a side surface of the chip in a plan view, and a length of the dummy chip in an extending direction of the dummy chip is more than half a length of the side surface of the chip facing the dummy chip.

38. The light detection device according to claim 29, wherein: The dummy chips are arranged so as to sandwich the chip in a plan view.

39. The light detection device according to claim 29, wherein: The dummy chip includes more than two dummy chips.

40. The light detection device according to claim 29, wherein The material of the dummy chip includes the same material as that of the chip.

41. The light detection device according to claim 29, wherein The height of the dummy chip is equal to the height of the chip.

42. The light detection device according to claim 29, wherein The chip includes more than two chips.

43. The light detection device according to claim 29, wherein The dummy chip continuously extends in a manner surrounding the chip in a plan view.

44. The light detection device according to claim 29, wherein When the light detecting device is viewed from the side, the dummy chip has a side surface exposed from the buried layer.

45. The light detection device according to claim 1, wherein At least a portion of the joint portion is filled with a material different from that of the embedding layer, and The sealing layer is a layer having a thermal conductivity higher than that of silicon.

46. ​​The light detection device according to claim 45, further comprising: a first sealing layer, which is arranged to cover the embedded layer and the seam portion; and a second sealing layer, which is arranged to cover the first sealing layer, The second sealing layer has a thermal conductivity higher than that of silicon.

47. The light detection device according to claim 45, wherein The sealing layer is a metal layer.

48. The light detection device according to claim 45, wherein The sealing layer comprises: A first portion covering the buried layer among the buried layer and the chip; and a second portion covering the chip among the buried layer and the chip, The first portion has insulating properties, and The second portion has a thermal conductivity higher than a thermal conductivity of silicon.

49. The light detection device according to claim 45, further comprising: an additional layer disposed between the chip and the buried layer, Wherein, the additional layer is a metal layer.

50. The light detection device according to claim 45, further comprising: a compound layer disposed between the chip and the sealing layer, Wherein, the compound layer is a silicide layer.

51. The light detection device according to claim 45, wherein The sealing layer is a layer having a metal structure provided in an insulator.

52. The light detection device according to claim 1, wherein The sealing layer is a resin layer.

53. The light detection device according to claim 52, wherein The front surface of the buried layer has a recessed portion, and The sealing layer is configured to fill the recess.

54. The light detection device according to claim 52, wherein The front side of the sealing layer is a planarized side.

55. The light detection device according to claim 52, wherein The resin layer is an oxide layer or an organic layer.

56. The light detection device according to claim 55, wherein The organic layer has a heat resistance temperature of 400° C. or higher.

57. The light detection device according to claim 56, wherein The material of the organic layer includes at least one of polyimide, siloxane, and silicone.

58. The light detection device according to claim 1, further comprising: A resin layer is provided between the chip and the embedding layer.

59. The light detection device according to claim 58, wherein The resin layer is an oxide layer or an organic layer.

60. The light detection device according to claim 59, wherein The organic layer has a heat resistance temperature of 400° C. or higher.

61. The light detection device according to claim 60, wherein The material of the organic layer includes at least one of polyimide, siloxane, and silicone.

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