Method of manufacturing plasma generating unit for plasma source

Abstract

A method of fabricating a dielectric barrier discharge (DBD) structure includes forming a patterned electrode layer around an outer periphery of a substrate composed of a dielectric material. The patterned electrode layer includes a plurality of electrodes surrounding an outer periphery of the substrate and gaps between adjacent electrodes. The method further includes depositing a dielectric layer on at least a first region of the patterned electrode layer to form a DBD region of the DBD structure.

Description

Technical Field

[0001] The present specification relates to methods of making components for controlling plasma processing. In particular, the present specification relates to methods of making electrode rods for use in a plasma source, such as a stackable plasma source for plasma processing. Background Art

[0002] Plasma processing is widely used in the semiconductor industry. Plasma can change the chemical properties of the process gas (e.g., produce ions, free radicals, etc.), produce new species without limitations related to process temperature, and produce ion-to-wafer fluxes with energies ranging from a fraction of an electron volt (eV) to thousands of eV. There are a variety of plasma sources (e.g., capacitively coupled plasma (CCP), inductively coupled plasma (ICP), microwave-generated plasma, electron cyclotron resonance (ECR), etc.), covering a wide range of operating processes from a few millitorr to several torr.

[0003] Common plasma process specifications today are for high uniformity of process results (e.g., uniformity from wafer to wafer edge). For example, process uniformity specifications in today's semiconductor manufacturing may include a target of approximately 1%-2% across the entire wafer, excluding 1-3 mm from the wafer edge. These tight constraints continue to become tighter as researchers seek new methods for controlling process uniformity and / or discover improvements to existing methods for controlling process uniformity. Different uniformity control methods may be effective for some processes and completely ineffective for others. Summary of the invention

[0004] The following is a simplified overview of the disclosure in order to provide a basic understanding of some aspects of the disclosure. This overview is not a comprehensive overview of the disclosure. It is neither intended to identify the key or important elements of the disclosure, nor to describe any scope of a particular implementation of the disclosure or any scope of the claims. Its sole purpose is to present some concepts of the disclosure in a simplified form as a prelude to a more detailed description presented later.

[0005] In an exemplary embodiment, a method for manufacturing a dielectric barrier discharge (DBD) structure includes forming a patterned electrode layer around a substrate composed of a dielectric material. The patterned electrode layer includes a plurality of electrodes around the substrate and gaps between adjacent electrodes in the plurality of electrodes. The method further includes depositing a dielectric layer on at least a first region of the patterned electrode layer to form a DBD region of the DBD structure.

[0006] In an exemplary embodiment, a method includes roughening the surface of a dielectric rod by a grinding operation or a dielectric sandblasting operation to form a roughened surface of the dielectric rod. The method further includes depositing an electrode layer on the roughened surface of the dielectric rod by a metallization process or by an electron beam ion assisted deposition (EB-IAD) process. The electrode layer includes at least one of a metal, a metal alloy, or a conductive oxide. The method further includes removing at least a portion of the electrode layer by a machining process or by an etching process to form a plurality of gaps in the electrode layer. Each gap in the plurality of gaps separates an electrode from an adjacent electrode. The method further includes depositing a dielectric layer on at least a first region of the electrode layer to form a dielectric barrier discharge region.

[0007] In an exemplary embodiment, a method includes smoothing the surface of a dielectric rod by a polishing operation to form a smooth surface of the dielectric rod. The method further includes depositing a mask layer on at least the smooth surface of the dielectric rod. The method further includes patterning the mask layer to expose a plurality of electrode regions on the smooth surface of the dielectric rod. The method further includes depositing a metal layer or a conductive oxide layer on the mask layer and the plurality of electrode regions to form a plurality of electrodes on the plurality of electrode regions. The method further includes removing the mask layer to form a plurality of gaps. Each gap in the plurality of gaps separates an electrode from an adjacent electrode. The method further includes depositing a dielectric layer on at least a first region of the plurality of electrodes to form a dielectric barrier discharge region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure is illustrated by way of example and not by way of limitation in the accompanying figures.

[0009] Figure 1A -D shows a plasma source having a configuration of a plasma generating unit according to aspects of the present disclosure.

[0010] Figure 2 A plasma processing system is shown in accordance with certain embodiments and includes a plasma generation assembly and a chamber body housing a plasma source.

[0011] FIG. 3 illustrates a chamber body housing a plasma source in accordance with certain embodiments.

[0012] Figure 3A A plasma generation unit of a stackable plasma source according to certain embodiments is shown.

[0013] Figure 3B A cross-sectional view of a plasma generation unit of a stackable plasma source is shown in accordance with certain embodiments.

[0014] Figure 3CA cross-sectional view of a plasma generation unit of a stackable plasma source is shown in accordance with certain embodiments.

[0015] Figure 3D A side view of a plasma generation unit of a stackable plasma source is shown in accordance with certain embodiments.

[0016] Figure 4A -B shows an embodiment of a plasma generation unit of a stackable plasma source according to certain embodiments.

[0017] Figure 5A -C is a flow chart of a method of manufacturing a plasma generating unit of a stackable plasma source according to certain embodiments. DETAILED DESCRIPTION

[0018] Today, a common goal for plasma processes is a high uniformity of process results (e.g., uniformity across the wafer all the way to the wafer edge). This goal is often difficult to achieve because it involves many factors, many of which interfere with other factors. Plasma uniformity, chamber design, wafer temperature distribution, bias electrode design, etc. are just some of these factors. In today's semiconductor manufacturing, typical process uniformity targets are about 1% to 2% across the wafer, excluding 1-3mm from the edge. Different uniformity control methods may be effective for some processes and completely useless for others. These tight constraints that are becoming increasingly stringent require new methods to control process uniformity to replace or complement existing methods.

[0019] These problems can be mitigated, and in some cases eliminated, if the conventional hardware architecture that uses a small number of powered elements (1-2 coils; 1-2 regional electrostatic chucks (ESCs), etc.), and a correspondingly very small number of control elements that globally control the plasma, is replaced with hardware that uses hundreds of controlled elements, each of which affects only a small localized area of ​​the wafer or other processing substrate (e.g., a glass plate). The analog process control used in conventional systems can be replaced with digital process control. Digital control is a native method for controlling many identical or similar controlled elements / units (e.g., 200-1000 regional ESCs, etc.). Unlike in an analog system, where these few elements operate at the same time but are powered up to carefully adjusted / controlled levels, in a digital control system, each unit (e.g., pixel) can be powered up / enabled to the same level (e.g., energized), but the exposure time of each unit can be controlled.

[0020] For example, a common plasma source can be replaced by a two-dimensional (2D) array of identical or similar small plasma sources covering the entire area above the substrate and powered by the same power supply. A controllable version of this array allows a single source or region to be turned on and off, wherein each region may contain multiple sources and the number of sources may vary from region to region. Controlling the time (turning on) of plasma generation in a single region or source can control process uniformity across the substrate. The difficulty with this approach is to manufacture a plasma source that can withstand vacuum conditions and / or process temperatures that can be anywhere from room temperature to several hundred degrees Celsius (e.g., 400°C-800°C). Early designs of a single plasma source (e.g., a plasma cell) included electrical connections (e.g., wires) to electrically couple a connection point at a first distal end of the plasma source (for connecting to an external power source) to an electrode disposed at a second distal end of the plasma source. The wires are typically located inside the plasma source. Therefore, early designs of plasma sources included seals (e.g., vacuum seals, sealed interfaces, etc.) where the wires contacted the electrodes and / or where the wires contacted external power lines. These internal wires and associated seals can lead to premature failure of a single plasma source and can introduce manufacturing difficulties.

[0021] Aspects and embodiments of the present disclosure use advanced methods to manufacture a single plasma source (e.g., a plasma cell, a dielectric barrier discharge (DBD) structure, etc.) to address these and other potential shortcomings of the technology. In an exemplary embodiment, a substrate having a circular cross-section or a cross-section having a different shape is provided. The substrate can be substantially rod-shaped (e.g., can be a rod). A patterned electrode layer can be formed around the outer periphery of the substrate. The patterned electrode layer can include multiple pairs of electrodes and gaps separating each pair of adjacent (e.g., adjacent) electrodes. The electrodes can extend from a first distal end of the substrate to a second distal end (e.g., an opposite end) of the substrate (e.g., from the top to the bottom of the rod). The electrodes can be deposited metals as described herein. The electrodes disposed on the outside of the substrate / rod can be configured to conduct power from a connection (e.g., an electrical connection to an external power source) to a DBD region as explained herein. The electrodes act as conductors (e.g., electrical conductors) between the connection to the power source and the DBD region, eliminating wires and seals, etc. of early designs of single plasma sources. A dielectric layer can be deposited on an area of ​​the patterned electrode layer near the second distal end of the substrate. The dielectric layer can electrically insulate the electrodes from each other, forming a DBD region. The DBD region may substantially form a capacitor.In some embodiments, a dielectric sleeve may be disposed over a region of the patterned electrode layer to electrically insulate the patterned electrode layer from a support structure when installing and operating a single plasma source.

[0022] Figures 1A-1DA plasma source of configurations 100A-D of a plasma generating unit 102 with a plasma source according to aspects of the present disclosure is shown. In some embodiments, the plasma generating unit includes a set of addressable plasma elements. In some embodiments, an array of plasma generating units (e.g., identical or similar plasma generating units) can be individually addressed to an on or off state. The on state is associated with the enabling of plasma generation, and the off state can be associated with the deactivation of plasma generation. For example, the addressable plasma element can use a dielectric barrier discharge (DBD) technology that allows each individual unit 102 (e.g., a micro source) to be independently operated using the selectability (addressing) of the unit 102 (e.g., a DBD unit). Alternatively, the addressable plasma assembly may include an individually addressable shutter. The advantage of dielectric barrier discharge is that a common voltage waveform from a single power supply can be applied (e.g., configured to provide) to all units 102 simultaneously, but the discharge will only occur in the previously selected (addressed) unit, which can have a natural memory capability without the need for additional memory retention elements. The remaining units 102 will be idle (no discharge). From an AC voltage (±V s ) can generate a series of identical discharge pulses at a frequency of 2f in these selected cells. A discharge pulse occurs after each polarity change, and the total amount of plasma-related particles (ions, electrons, free radicals) generated in any cell is proportional to the number of pulses generated in the cell.

[0023] Different duration combinations may be used to generate an exposure pattern with independent activation and deactivation of cells 102. In some embodiments, the exposure pattern includes data with a set of exposure durations mapped to individual plasma elements. Individual activation instructions may be stored in an exposure file (e.g., an image file) for each plasma element in a grid format. In some embodiments, the exposure pattern may include duration values ​​in different formats (e.g., an amount of time, a number of plasma pulses, etc.) that may be mapped to cells 102 such that each cell 102 allows passage or generation of a plasma-related flux for the associated exposure duration.

[0024] like Figure 1AAs shown, the cells 102 can be arranged in an organized structure (e.g., a grid, a shape, etc.). Each cell 102 can be assigned an address in a two-dimensional space (X, Y) or (Z, Y) (e.g., axis 104 and axis 106). The former uses a 2-electrode structure, so both electrodes are used for addressing and maintaining. The latter uses 3 electrodes, where an additional electrode is used only for addressing along with the Y (scan) electrode, while the X and Y electrodes are used to maintain the discharge. Both addressing and maintenance schemes can be used to address the electrodes. For example, a cell can be assigned an address with an X address (e.g., an address on axis 104) and a Y address (e.g., an address on axis 106). In some embodiments, the exposure pattern (also called an exposure map) can include a large array of t ik or N ik , where N is the number of pulses, and (i, k) is the node of the array with (i, k) (x i ,y k ) coordinates, where the addresses identified in the exposure pattern correspond to the addresses of the cells in the set of plasma generating cells 102. For example, the addresses in the exposure pattern may contain data indicating the duration or exposure duration for which the associated addressable node (or cell) will be enabled during the plasma process. Each cell may be individually controlled to independently enable and / or disable the plasma cell.

[0025] like Figure 1B As shown, the cells 102 can be arranged in an organized structure (e.g., a grid, a shape, etc.). Each cell can be coupled to adjacent cells so that all cells in the configuration 100B are controlled together. For example, when the configuration 100B of the plasma cell 102 is enabled, the entire array of cells is also enabled. The branches of the electrical leads can be configured so that the A branch directs the electrical signal in a first direction via the plasma cell, and the B branch directs the electrical signal in a second direction. As will be discussed later, the electrical leads can cause the plasma cell to be enabled and generate plasma, such as plasma for substrate processing.

[0026] like Figure 1C As shown, the cells 102 can be arranged in an organized structure (e.g., a grid, a shape, etc.). Each cell can include a first electrical lead corresponding to the first axis 104 and a second lead corresponding to the second axis 106. In this configuration, each cell can be controlled together (e.g., one cell is enabled / disabled together with another cell). Each cell can be connected to other plasma cells in the same column using the first lead and connected to other plasma cells in the same row using the second lead, such as Figure 1C shown.

[0027] like Figure 1DAs shown, the cells 102 can be arranged in an organized structure (e.g., a grid, a shape, etc.). The cells can be divided into separate regions and wired so that plasma cells located in the same region are enabled / disabled together. For example, a first region shown by a cell coupled to the darker "Region 1 (a, b)" line is connected to the first region, and a second region shown by a cell coupled to the lighter "Region 2 (a, b)" line represents a second region. Figure 1D As shown, these regions may be divided into locations of the array, such as a central region and a border region.

[0028] In some embodiments, Figure 1A The connected units shown can be controlled by selectively addressing and enabling / disabling individual units in a manner similar to Figure 1B-1D The configurations 100B-100C shown are controlled. Each unit 102 may include a dielectric rod having one or more pairs of electrodes arranged around the periphery of the dielectric rod. The electrodes may extend from the top of the dielectric rod to the bottom of the dielectric rod. At least one area of ​​the electrode may be coated with a dielectric layer. Plasma discharge may be generated at the gap between the electrode pairs. In some embodiments, the unit 102 is manufactured according to the embodiments described herein.

[0029] Figure 2A plasma processing system 200 is shown according to certain embodiments, which includes a plasma generation assembly 202 and a chamber body 214 containing a plasma source. The processing system 200 may include a processing chamber 210 and a plasma source 202. The plasma source 202 includes a wall 220 (e.g., to maintain a vacuum and / or gas delivery volume 204), a gas inlet 212, a gas delivery volume 204 bounded by the wall 220, and a plasma generation assembly 230. The processing chamber 210 includes a chamber body 214 that maintains an internal vacuum and provides support for the plasma source 202, a substrate support structure 208, and a gas outlet 216. The gas inlet 212, the plasma generation assembly 230, and the gas outlet 216 can provide a feed gas flow through the processing system at a process gas pressure. The feed gas can include any of air, oxygen (O2), nitrogen (N2), argon (Ar), ammonia (NH3), helium (He), and / or other suitable process gases. The plasma source 202 can include a gas expansion volume (e.g., without plasma) of a gas injector. The plasma source 202 may be configured to deliver plasma (e.g., generate plasma or facilitate plasma flow) to a processing chamber 210. The plasma source delivers plasma via a plasma generation assembly 230. The processing chamber 210 accommodates a substrate disposed on a substrate support structure 208 to be processed by the processing system 200. The processing system 200 may be a plasma chamber, including an etching chamber, a deposition chamber (including atomic layer deposition, chemical vapor deposition, physical vapor deposition), and the like. For example, the plasma chamber may be a chamber for a plasma etcher, a plasma cleaner, and the like.

[0030] The plasma generating assembly 230 may include a holding structure (sometimes referred to as a support structure) and a plasma generating unit (eg, Figures 1A-1D The invention also provides an arrangement of plasma generating units 102 that are selectively coupled to a holding structure (e.g., easily removed from the holding structure but retaining position and / or orientation when coupled). In some embodiments, the holding structure includes a frame or skeleton for holding each plasma generating unit.

[0031] The plasma generation assembly 230 is positioned above the substrate on the substrate support structure 208. The plasma source 202 forms an internal volume, which serves as the gas delivery volume 204. The feed gas is received by the gas inlet 212 and delivered to the various plasma generation units of the plasma generation assembly 230. For example, the feed gas enters the gas distribution volume 204, diffuses above the plasma generation assembly 230 and enters the plasma unit. Plasma is generated in the units placed in the holding structure, which together form the plasma generation assembly 230. The plasma is provided to the processing chamber 210. In some aspects, the plasma is prevented from flowing into the gas distribution volume 204.

[0032] Figure 3A 301 of a stackable plasma source 300A according to some embodiments is shown. In some embodiments, portions of the stackable plasma source 300A (e.g., connection structure 302, wall 333, electrodes 352A-B, dielectric layer 354, etc.) may correspond to Figures 1A-1D Unit 102 of

[0033] The stackable plasma source 300A may include elements discussed in conjunction with other figures described herein. For example, the stackable plasma source 300A may include a connection structure 321 (e.g., a cover structure, a metal plate, a top of a processing chamber, etc.) and a retaining structure 331 (e.g., a housing structure, a skeleton, a ceramic panel, etc.). The connection structure 302 and the retaining structure 331 may form a region 330 that directs the flow of process gas to the plasma generating unit 300B. The process gas may be directed into the region 330 using a gas inlet structure 312. In some embodiments, the gas inlet structure 312 may correspond to Figure 2 The gas inlet 212 in the.

[0034] The stackable plasma source 300A includes a plasma generating unit ( Figure 3AOnly one is shown in the figure). The plasma generating unit 301 includes a base structure 302 (e.g., a rod) having a set of electrodes. The base structure 302 can be a dielectric substrate or a dielectric rod. The base structure can be solid, or can be hollow (e.g., a tube) with one or both ends blocked. The base structure can have a cross-section of any shape, such as a cross-section having a circular, square, rectangular, pentagonal, hexagonal, etc. In some examples, the base structure 302 is made of a dielectric material. In some examples, the base structure 302 is made of alumina, quartz, or sapphire. However, the base structure 302 can be made of other materials consistent with the description provided herein. The retaining structure 331 includes a wall 333 disposed between the plasma generating units 301 (only one plasma generating unit is shown, but similar to other embodiments, an arrangement (e.g., an array) of plasma generating units can be incorporated into the stackable plasma source 300A). The plasma generating unit is designed to receive a processing gas from the region 330 via a channel 332 of the retaining structure 331 and generate a plasma-related flux 324. In some embodiments, the retaining structure 331, the channel 332 and / or the wall 333 may correspond to Figure 2 The plasma generating component 230 in.

[0035] like Figure 3A As shown, the base structure may include electrodes 352A-B extending along the outer surface of the base structure 302. In some embodiments, the electrodes are deposited onto the surface of the base structure 302 along the outer perimeter of the base structure 303. The bottom of the base structure 302 can be further covered with a thin dielectric layer 354 to form a dielectric barrier discharge region (e.g., a DBD region). For example, the electrodes 352A-B can be sufficiently covered so as not to be exposed at any point below the retaining structure 331 (e.g., the electrodes 352A-B are not exposed to the vacuum conditions of the processing chamber). The base structure 302 can be inserted into the rod structure 314. The rod structure 314 can extend through the connecting element 322. In some embodiments, the connecting element 322 and the connecting structure 321 can correspond to Figure 2 In some embodiments, the rod structure 314 is a dielectric sleeve (e.g., a dielectric insulating layer) to electrically insulate the electrode 352 from the connecting structure 321 and / or the retaining structure 331. In some embodiments, the joint between the base structure 302 and the rod structure 314 forms a seal. In some embodiments, the rod structure 314 is an insulator configured to electrically insulate the electrode from the connecting structure 321. In some embodiments, the rod structure 314 is a dielectric deposited on the base structure 302 as described herein. In some embodiments, the base structure 302, the electrode 352, the dielectric layer 354 and / or the rod structure 314 (e.g., a dielectric sleeve, a dielectric insulating layer, etc.) can form a DBD structure.

[0036] like Figure 3A As shown, in some embodiments, the electrodes are arranged vertically and extend toward the top (e.g., the atmosphere), and these electrodes can be connected to an electrical connector at the top to receive an enable / disable signal (e.g., from an external power source). In some embodiments, the electrodes cover most of the surface area of ​​the base structure 302. As discussed in other embodiments, more than one pair of electrodes can be used. For example, two pairs of electrodes, three pairs of electrodes, etc. can be used. In some embodiments, eight pairs of electrodes are used. Adjacent electrodes (e.g., adjacent electrodes) can be separated by gaps. Multiple pairs of electrodes can be connected in parallel, for example, to coordinate the activation and deactivation of adjacent electrodes. The retaining structure 331 can have auxiliary horizontal electrodes (e.g., electrodes forming a ring) buried in the wall 333, and the wall 333 is connected to other auxiliary electrodes located at the top of the retaining structure 331. The auxiliary electrodes can be connected to each other in rows.

[0037] Figure 3B 3 shows a cross-sectional view of a plasma generating element 300B of a plasma source 300A according to some embodiments. In some embodiments, the plasma generating element 300B can correspond to the plasma generating element 301. In some embodiments, the cross-section of the base structure 302 is circular (e.g., Figure 3B However, in some embodiments, the base structure 302 may have an elliptical cross-section, a triangular cross-section, a square cross-section, a rectangular cross-section, a pentagonal cross-section, or a hexagonal cross-section (e.g., Figure 3C ). In some embodiments, the base structure 302 includes a plurality of planes. In some embodiments, the cross-section of the base structure 302 is between approximately 5 mm and 30 mm. For example, the cross-section of the base structure 302 can have a diameter between approximately 5 mm and 30 mm. As discussed herein, the base structure 302 can be partially (e.g., a first portion of the base structure 302) defined by the first electrode 352A and partially (e.g., a second portion of the base structure 302) defined by the second electrode 352B. In some embodiments, the electrodes can extend around the azimuthal direction of the base structure 302, while in other embodiments, the electrodes can extend along the latter direction (e.g., as Figure 3B as seen).

[0038] In some embodiments, each of the electrodes 352 may form a patterned electrode layer around the periphery of the base structure 302. In some embodiments, the electrodes 352 may be deposited on the surface of the base structure 302 as described herein. In some examples, the electrodes 352 are deposited by a metallization process, an electron beam ion assisted deposition (EB-IAD) process, or another process described herein. In some embodiments, the thickness of the electrodes 352 may be between about 0.1 microns and 20 microns.

[0039] In some embodiments, the first electrode 352A and the second electrode 352B are separated by a gap 353. In some embodiments, the gap size of each gap 353 is about 0.5 mm and 8 mm. In embodiments where there are multiple pairs of electrodes, the gap 353 separates each adjacent electrode. In embodiments, different electrode pairs can have gaps of the same size or gaps of different sizes. Figure 3B As shown, the electrode and base structure can be covered by a covering layer 354, which can include a dielectric material. The covering layer 354 can include the first layer and / or the second layer described herein. In some embodiments, the covering layer 354 is deposited on the region of the electrode 352 (e.g., the region of the patterned electrode layer) to form a dielectric layer. The dielectric layer can be deposited by plasma spraying (PS) technology and / or physical vapor deposition (PVD) technology described herein. In some embodiments, the thickness of the dielectric layer (e.g., covering layer 354) is between about 25 microns and 1000 microns. In some embodiments, the covering layer 354 is composed of a dielectric oxide layer (e.g., the first layer). The dielectric oxide layer can be a material selected from a group including aluminum oxide, yttrium oxide and / or magnesium oxide. In some embodiments, the covering layer 354 additionally includes a metal oxide layer (e.g., the second layer) deposited on the dielectric layer. The metal oxide layer can include aluminum oxide and / or yttrium oxide.

[0040] Figure 3C A cross-sectional view of a plasma generating element 300C of a stackable plasma source 300A according to certain embodiments is shown. In embodiments, the plasma generating element 300C may correspond to the plasma generating element 301. In some embodiments, the base structure 302 (e.g., a substrate) has a hexagonal cross-section as shown and described herein. In some embodiments, the base structure 302 has a triangular cross-section, a square cross-section, a rectangular cross-section, a pentagonal cross-section, etc. The electrode 352 may be deposited on a flat surface of the base structure 302. Depositing the electrode 352 on a flat surface of the base structure 302 may reduce the cost associated with depositing the electrode 352 compared to depositing the electrode 352 on a curved surface (e.g., such as when the base structure 302 has a circular or oval cross-section). In some embodiments, the flat surface of the base structure 302 may have a width between about 4 mm and 15 mm.

[0041] Figure 3DA side view of a plasma generating element 300D of a stackable plasma source 300A according to certain embodiments is shown. In embodiments, the plasma generating element 300D may correspond to the plasma generating element 301, the plasma generating element 300B, and / or the plasma generating element 300C. In some embodiments, the electrode 352 is deposited on a plane of the base structure 302. A dielectric layer may be deposited on the electrode 352 and the gap 353 to form a DBD region 319. In some embodiments, a dielectric sleeve 315 is deposited on the electrode 352 to form an insulating region. The dielectric sleeve 315 may at least partially overlap the deposited dielectric layer. In some embodiments, the dielectric sleeve 315 is an electrical insulator to insulate the electrode 352 from a support structure (e.g., a retaining structure 331, a connecting structure 321). A vacuum seal 317 may be deposited at the end of the dielectric sleeve 315 to seal the interface of the dielectric sleeve 315 and a dielectric layer (not shown), and / or to seal the interface of the dielectric sleeve 315 and the (upper) end of the base structure 302 and the electrode 352. In one embodiment, the vacuum seal is achieved by applying an epoxy or other bonding material between the dielectric sleeve and the base structure 302. The epoxy or other bonding material may form a bond with the base structure 302 sufficient to maintain a vacuum. In some embodiments, the electrode 352 extends upward from below the dielectric sleeve 315 by about 1-10 cm, opposite the DBD region 319. In some embodiments, the electrode 352 may extend more than 1 cm or less than 1 cm from below the dielectric sleeve 315 to interface with an electrical connector (e.g., to couple the electrode 352 to an external power source). The electrode 352 may be configured to conduct power from the top distal end (as shown) to the DBD region 319.

[0042] Figures 4A-4B Electrode configurations of plasma generation units 400A-B according to certain embodiments are shown. Plasma generation units 400A-B may correspond to plasma generation unit 102 in embodiments.

[0043] In some embodiments, Figure 4A As shown, a first electrical lead 406A can be coupled to a first electrode 404A that surrounds the outer perimeter of the base structure 402. A second electrical lead 406B can be coupled to a second electrode 404B that surrounds the outer perimeter of the base structure 402. The two perimeters can be displaced a distance with a dielectric material between them. Figure 4A Electrode 404A may completely surround the base structure, but form a gap so that lead 406B of another electrode can extend and receive the enable / disable signal. Electrodes 404A and 404B may include one or more features and / or details of other electrodes described herein.

[0044] In some embodiments, Figure 4B As shown, electrodes 452A-B can be disposed along the outer surface of base structure 456. The electrodes can extend around the base structure while advancing in the longitudinal direction of base structure 456. For example, Figure 4B As shown, the electrodes may be arranged in a spiral structure (eg, helical, spiral, etc.).

[0045] Figures 5A-5C is a flow chart of a method of manufacturing a plasma generating unit of a stackable plasma source according to certain embodiments. Figures 5A-5C The method may be used to manufacture a plasma generating unit as shown and described with reference to any of the preceding figures. Figure 5A is a flow chart of a method 500A of manufacturing a plasma generating unit of a stackable plasma source according to certain embodiments.

[0046] Figure 5B is a flow chart of a method 500B of forming a patterned electrode layer on a plasma generating unit according to some embodiments.

[0047] Figure 5C is a flow chart of a method 500C for forming a patterned electrode layer on a plasma generating unit by a mask process according to some embodiments.

[0048] refer to Figure 5A At block 502, a dielectric substrate or rod (e.g., Figures 3A-3D The patterned electrode layer is formed around the outer periphery of the base structure 302. In some embodiments, the patterned electrode layer can be formed by a deposition process, a machining process, and / or a mask process as described herein. In some embodiments, the patterned electrode layer includes multiple pairs of electrodes (e.g., one to eight pairs of electrodes, Figures 3A-3D The electrodes 352 may be arranged substantially around the periphery of the substrate. The electrodes may extend from a first end of the substrate to an opposite second end of the substrate (e.g., from the top of a rod-shaped substrate to the bottom).

[0049] Adjacent electrodes (eg, adjacent electrodes) may be separated by gaps (eg, Figure 3B-3DThe electrode pairs may be separated by gaps 353 of 353. Each gap may be formed by a machining process and / or a mask process as described herein. In some embodiments, as described herein, the width of each gap is between about 0.5 mm and 8 mm. In some embodiments, the width of each gap is between about 1 mm and 6 mm. However, in some embodiments, the width of each gap is between about 2 mm and 5 mm. Different electrode pairs may have gaps of the same size or gaps of different sizes. In some embodiments, as described herein, the patterned electrode layer has a thickness between about 0.1 micron and 20 microns. In some embodiments, the patterned electrode layer has a thickness between about 0.5 micron and 10 microns. In some embodiments, the patterned electrode layer has a thickness between about 0.3 micron and 1 micron (e.g., wherein the patterned electrode layer is composed of ITO or a metal alloy on a polished quartz substrate). In some embodiments, the thickness of the patterned electrode layer is between about 6 microns and 14 microns (e.g., wherein the patterned electrode layer is composed of a metallized metal on an alumina substrate). In some embodiments, the patterned electrode layer is composed of a metal or a metal alloy. In some examples, the patterned electrode layer is composed of a manganese-molybdenum alloy and / or a silver-palladium alloy and / or any alloy of chromium, nickel and / or silver. In some embodiments, the patterned electrode layer may include other metals and / or materials described herein. In some examples, the patterned electrode layer may include one or more of TiN, TiB2, MoSi2, BaTiO3, (Fe, Ti)2O3, ReO3, RuO2, IrO2, TiO, V2O3+Ti, etc. In some embodiments, the patterned electrode layer includes Inconel or other high-temperature nickel-based and / or cobalt-based superalloys. In some embodiments, the patterned electrode layer may include a sandwich structure. For example, a sandwich structure may include a main conductor layer sandwiched between two thin layers of another metal (such as chromium, etc.). In some examples, the sandwich structure may include structures such as Cr-Cu-Cr, Cr-Ag-Cr, Cr-Au-Cr, Cr-Ir-Cr. In some embodiments, the patterned electrode layer may include a conductive oxide layer and / or a conductive ceramic layer.

[0050] At block 504, a first dielectric layer (eg, Figures 4A-4B The dielectric layer 454 is deposited on the region (eg, the first region) of the patterned electrode layer. The dielectric layer deposited on the region of the patterned electrode layer may form a dielectric barrier discharge (DBD) region (eg, Figure 3DDBD region 319). In some embodiments, as described herein, the dielectric layer can have a thickness between about 25 microns and 1000 microns. In some embodiments, the dielectric layer has a thickness between about 20 microns and 200 microns. In some embodiments, the contact pads (e.g., electrode connection pads, connection areas, etc.) of the patterned electrode layer can be masked during deposition of the dielectric layer. The contact pads can be disposed at the upper end of the substrate and can be configured to electrically couple the electrode to a power source, as described herein.

[0051] Coatings (e.g., metal layers, electrode layers, dielectric layers, dielectric sleeves, etc.) according to embodiments described herein can be formed using a deposition process selected from chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), plasma enhanced physical vapor deposition (PEPVD), and atomic layer deposition (ALD). CVD is a well-known technique for depositing pure metal coatings. In a typical CVD process, a substrate is exposed to at least one volatile precursor under ultra-high vacuum conditions. The at least one precursor reacts or decomposes on the surface of the substrate to form a film. The reaction chamber is then purged with an inert gas flowing through the reaction chamber. In the PECVD process, the chemical reaction is initiated by generating a plasma of a reactive precursor gas. In the ALD process, a thin film layer is grown by repeatedly exposing the surface of the substrate to pulses of a gaseous chemical precursor, which chemically reacts with the surface one at a time in a self-limiting manner. CVD and ALD are non-line-of-sight processes that can be used to coat high aspect ratio features. PVD processes are also performed under vacuum conditions and typically involve sputtering and / or evaporating a target material to form a gas that is deposited and / or reacted on the substrate surface. PVD (typically including evaporation, plasma spray, etc.) is a line-of-sight process. In a PEPVD process (typically including ion-assisted deposition, ion-assisted evaporative deposition, ion-assisted sputtering deposition, ion plating, etc.), plasma or high-energy ions are generated to react with the deposited material from the PVD, such as an ion beam, and involve sputtering or evaporation of the target material. PEPVD is a line-of-sight process, but can be changed to a non-line-of-sight process if the substrate is biased during the deposition process. Compared to ALD, PVD and PEPVD can deposit relatively thick coatings (up to about 500μm, or up to about 250μm, or about 5μm to about 250μm) at relatively low deposition temperatures (<200°C).

[0052] In some embodiments, the dielectric layer is deposited by a glaze process (e.g., a glazing process). The glaze process may be similar to (e.g., substantially similar to) a dip coating process. In some embodiments, a substrate having a patterned electrode layer may be immersed in a solution (e.g., a coating solution, a glaze solution, etc.) and subsequently removed from the solution. The solution may be cured on the substrate and the patterned electrode layer. In some embodiments, the solution is dried or heated (e.g., the substrate may be "fired", etc.) to cure the solution on the substrate and the patterned electrode layer. In some embodiments, the dielectric layer deposited by the glaze process is one of silicon dioxide or aluminum oxide. In some embodiments, a first protective layer (e.g., a thin oxide layer) may be deposited on the substrate and / or the patterned electrode layer before the glaze process as described below.

[0053] In some embodiments, the dielectric layer includes an oxide layer. In some embodiments, the oxide layer may include a material selected from one of aluminum oxide (e.g., Al2O3), yttrium oxide (Y2O3), and / or magnesium oxide (MgO). The oxide layer may be deposited by a process as described herein.

[0054] In some embodiments, at block 505, a second dielectric layer is formed on top of the first dielectric layer. In an embodiment, the second dielectric layer includes a metal oxide layer (e.g., a rare earth metal oxide layer). The metal oxide layer may include a material selected from aluminum oxide or yttrium oxide. The metal oxide layer may be deposited by a process as described herein. The first dielectric layer and the second dielectric layer may be deposited by the same deposition process or by different deposition processes. The second dielectric layer may be a protective layer deposited on top of the first dielectric layer to protect the first dielectric layer. In some examples, the second dielectric layer may be stronger than the first dielectric layer (e.g., more resistant to plasma, etc.). The first dielectric layer and the second dielectric layer may include the same material or different materials (e.g., different oxides). In one embodiment, the first dielectric layer includes aluminum oxide, yttrium oxide, or magnesium oxide, and the second dielectric layer includes aluminum oxide. In an embodiment, the first dielectric layer may have a thickness of 25-200 microns, and the second dielectric layer may have a thickness of 10-50 microns. In some embodiments, the first or second dielectric layer is deposited by atomic layer deposition (ALD).

[0055] In some embodiments, at least one of the first dielectric layer or the second dielectric layer includes aluminum oxide, yttrium oxide, magnesium oxide, Y2O3, Er2O3, Y3Al l5 O 12 (YAG), Er3Al5O 12(EAG), yttria stabilized zirconia (YSZ), SiO2-Al2O3 mixture or Y4Al2O9 (YAM). The rare earth metal-containing oxide layer can also be YAlO3 (YAP), Er4Al2O9 (EAM), ErAlO3 (EAP), a solid solution of Y2O3-ZrO2 and / or a ceramic compound containing a solid solution of Y4Al2O9 and Y2O3-ZrO2.

[0056] Regarding the solid solution of Y2O3-ZrO2, the rare earth metal-containing oxide layer may include Y2O3 at a concentration of 10-90 molar ratio (mol%) and ZrO2 at a concentration of 10-90 mol%. In some embodiments, the solid solution of Y2O3-ZrO2 may include 10-20 mol% Y2O3 and 80-90 mol% ZrO2, may include 20-30 mol% Y2O3 and 70-80 mol% ZrO2, may include 30-40 mol% Y2O3 and 60-70 mol% ZrO2, may include 40-50 mol% Y2O3 and 50-60 mol% ZrO2, may include 60-70 mol% Y2O3 and 30-40 mol% ZrO2, may include 70-80 mol% Y2O3 and 20-30 mol% ZrO2, may include 80-90 mol% Y2O3 and 10-20 mol% ZrO2, and so on.

[0057] Regarding the ceramic compound containing Y4Al2O9 and Y2O3-ZrO2 solid solution, in one embodiment, the ceramic compound includes 62.93 mol% Y2O3, 23.23 mol% ZrO2, and 13.94 mol% Al2O3. In another embodiment, the ceramic compound may include Y2O3 in the range of 50-75 mol%, ZrO2 in the range of 10-30 mol%, and Al2O3 in the range of 10-30 mol%. In another embodiment, the ceramic compound may include Y2O3 in the range of 40-100 mol%, ZrO2 in the range of 0.1-60 mol%, and Al2O3 in the range of 0.1-10 mol%. In another embodiment, the ceramic compound may include Y2O3 in the range of 40-60 mol%, ZrO2 in the range of 30-50 mol%, and Al2O3 in the range of 10-20 mol%. In another embodiment, the ceramic compound may include Y2O3 in the range of 40-50 mol%, ZrO2 in the range of 20-40 mol%, and Al2O3 in the range of 20-40 mol%. In another embodiment, the ceramic compound may include Y2O3 in the range of 70-90 mol%, ZrO2 in the range of 0.1-20 mol%, and Al2O3 in the range of 10-20 mol%. In another embodiment, the ceramic compound may include Y2O3 in the range of 60-80 mol%, ZrO2 in the range of 0.1-10 mol%, and Al2O3 in the range of 20-40 mol%. In another embodiment, the ceramic compound may include Y2O3 in the range of 40-60 mol%, ZrO2 in the range of 0.1-20 mol%, and Al2O3 in the range of 30-40 mol%. In other embodiments, other distributions of the ceramic compound may also be used.

[0058] Any of the above rare earth metal-containing oxide layers may include trace amounts of other materials, such as ZrO2, HfO2, Al2O3, SiO2, B2O3, Er2O3, Nd2O3, Nb2O5, CeO2, Sm2O3, Yb2O3 or other oxides.

[0059] At block 506, a dielectric sleeve (e.g., Figure 4A The rod structure 414 is positioned above the region (eg, the second region) of the patterned electrode layer. The dielectric sleeve may be an insulating layer to separate the patterned electrode layer (eg, Figures 4A-4B In some embodiments, the dielectric sleeve forms an insulating region of the plasma generating unit. In some embodiments, the dielectric sleeve electrically insulates the electrode from the connection structure of the stackable plasma source (e.g., Figure 4AThe dielectric sleeve may be insulated from the connection structure 406, the cover structure, the metal plate, the top of the processing chamber, etc. of the dielectric sleeve. The dielectric sleeve may at least partially overlap with the dielectric layer deposited at frame 504. The thickness of the dielectric sleeve may be greater than the thickness of the dielectric layer as described herein. In some examples, the dielectric sleeve may have a thickness of more than 200 microns. In some embodiments, a substrate having a patterned electrode layer is inserted into the dielectric sleeve. In some embodiments, the dielectric sleeve is deposited on the patterned electrode layer (e.g., covering the electrode and the gap). The dielectric sleeve may partially overlap with the dielectric layer. In some embodiments, the dielectric sleeve is made of a dielectric material described herein (e.g., aluminum oxide, yttrium oxide, magnesium oxide, etc.). In some embodiments, approximately 1 cm of the substrate and the patterned electrode layer may not be covered by the dielectric sleeve and / or the dielectric layer to facilitate electrical connection of the electrode to an external power source.

[0060] At box 508, a gap filler (e.g., vacuum seal 417 of FIG. 4D) may be applied to the edge of the dielectric sleeve and / or the gap between the dielectric sleeve and the dielectric substrate. The gap filler may be applied to fill any gap between the dielectric sleeve and the substrate. The gap filler may be applied to bond the dielectric sleeve to the patterned electrode layer, the dielectric layer, and / or the substrate. In some embodiments, the gap filler may be an epoxy, a dielectric adhesive (e.g., a dielectric glue), a dielectric epoxy, and / or a dielectric glass. In some embodiments, the gap filler is applied using vacuum infiltration. In some embodiments, the gap filler is injected into the gap between the dielectric sleeve and the substrate. In some embodiments, the gap filler is a glass frit filled into the gap between the dielectric sleeve and the substrate. The glass frit may then be cured by firing (e.g., heating, such as in a kiln, etc.). In some embodiments, the gap filler may be painted onto the substrate (e.g., and / or the patterned electrode layer), and the dielectric sleeve is pushed onto the substrate and the gap filler. The gap filler may form a vacuum seal at the interface between the dielectric sleeve deposited at block 506 and the dielectric layer deposited at block 504. After applying and curing the gap filler, the plasma cell may be cleaned and / or prepared for ultra-high vacuum (UHV) processing.

[0061] Figure 5B 5 is a flow chart of a method 500B for forming a patterned electrode layer on a plasma generating unit according to certain embodiments. The method 500C may be performed, for example, at block 502 of the method 500A. At block 512, an outer surface of a substrate may be prepared. In some embodiments, an outer surface of a dielectric substrate (e.g., an aluminum oxide substrate) or a rod is roughened in preparation for depositing a metal on the roughened surface of the substrate at block 514. In some embodiments, the roughening of the outer surface of the substrate may be accomplished by an abrasive machining operation (e.g., grinding, etc.) and / or by a blasting process (e.g., sandblasting, media blasting, etc.).

[0062] In some embodiments, the outer surface of the substrate can be prepared by polishing. In some examples, the outer surface of the substrate is smoothed by a polishing operation to form a smooth surface. In some examples, the outer surface of a sapphire substrate or a quartz substrate (e.g., a fused silica substrate) is polished to prepare for metal deposition on the substrate at frame 514 (e.g., before the EB-IAD operation). In some embodiments, the polishing of the substrate surface can be completed by a machining operation and / or a flame polishing operation. Flame polishing can include exposing the surface of the substrate to a flame and / or heat to temporarily melt the surface of the substrate. The surface tension of the molten surface can make the surface smooth.

[0063] At frame 514, metal can be deposited on the outer surface of the substrate. Metal can be deposited to form an electrode layer on the outer surface of the substrate. In some embodiments, the metal can be deposited on the substrate by a dip coating process, by a paint coating process and / or by a screen printing process. In some embodiments, the metal is deposited by a PVD process (e.g., sputtering coating). In some embodiments, the metal is deposited by an electroless plating (EP) process. The metal can be deposited on a dielectric substrate such as an aluminum oxide substrate or an yttrium oxide substrate by the aforementioned process. The metal can be one of a manganese-molybdenum alloy, a silver-palladium alloy, copper, gold, palladium platinum and / or silver. Other conductive materials can also be used, which can be other metals or other conductive materials (e.g., conductive oxides, conductive ceramics, etc.). In some embodiments, the metal can be metalized on the substrate surface by a heating metallization process (e.g., a metallization process). The metal (e.g., or conductive materials, conductive oxides, conductive ceramics, etc.) can react with silicon in the substrate during the metallization process to form a metal silicide layer on the substrate surface. In some embodiments, the metal is deposited on the substrate by an EB-IAD process. The metal deposited by the EB-IAD process may include at least one of Cr, Ni, Au, Cu, Ag, Pd, Pt, indium tin oxide (ITO), TiN, TiB2, MoSi2, BaTiO3, Fe2O3, TiO3, ReO3, RuO2, IrO2, TiO, or V2O3.

[0064] At block 516, the electrode layer (eg, deposited at block 514) may be patterned to form a patterned electrode layer (eg, Figure 3A-3B In some embodiments, the electrode layer can be patterned using a process selected from the group consisting of a machining operation, a laser etching operation, and / or a masking operation. In some examples, portions of the electrode layer can be removed (e.g., by a machining tool and / or by a laser etching tool) to form gaps in the electrode layer (e.g., Figure 3B-3D gap 353).

[0065] In some examples, the masking operation of the patterned electrode layer includes depositing a mask on the electrode layer deposited on the surface of the substrate. The mask can then be patterned. The mask can be patterned, for example, via selective exposure to radiation (e.g., by photolithography). An etching process can then be performed to etch only the portion of the mask exposed to the radiation or only the portion of the mask not exposed to the radiation, leaving the exposed portion of the electrode layer. The exposed portion of the electrode layer (e.g., the portion of the electrode layer exposed by the patterned mask) can be etched (e.g., by an etching process, such as a plasma etching process, an acid etching process, a laser etching process, a chemical etching process, etc.) to form a gap 353. After the etching is completed, the mask can be removed.

[0066] The patterned electrode layer can form gaps between individual electrodes (e.g., Figure 3B-3D In some embodiments, one to eight pairs of electrodes are formed in the electrode layer by patterning, and each pair of adjacent electrodes is separated by a gap. In some embodiments, more than eight pairs of electrodes are formed in the electrode layer.

[0067] Figure 5C 5 is a flow chart of a method 500C for forming a patterned electrode layer on a plasma generating unit by a mask process according to some embodiments. For example, the method 500C may be performed at block 502 of the method 500A. At block 522, a mask layer may be deposited over an outer surface of a substrate (e.g., such as a rod). The mask layer may be deposited around a periphery (e.g., an outer perimeter) of the substrate.

[0068] At block 524, the mask layer can be patterned to expose a plurality of surface regions of the substrate. In some examples, each surface region corresponds to a portion of the substrate surface where an electrode is to be deposited (e.g., at block 526). The exposed surface regions can be electrode regions on the substrate surface. In some embodiments, the surface regions of the substrate are disposed on a plane of the substrate (e.g., in embodiments where the substrate includes a plane, such as when the substrate has a triangular cross-section, a square cross-section, a rectangular cross-section, a pentagonal cross-section, or a cross-section such as Figure 3C In some embodiments, adjacent surface regions may be separated by a distance of 0.5 mm to 8 mm.

[0069] At block 526, a metal layer may be deposited over the mask layer (e.g., by an EB-IAD process, by a printing process, etc.) and the plurality of exposed surface areas of the substrate. The metal layer may be deposited onto the surface of the substrate to form individual electrodes (e.g., one to eight pairs of electrodes in some embodiments). In some embodiments, a conductive material layer may be deposited over the mask layer and the plurality of exposed surface areas of the substrate. In some embodiments, a conductive oxide layer or a conductive ceramic layer may be deposited to form individual electrodes.

[0070] At block 528, the mask layer may be removed, leaving the electrodes (eg, Figure 3A-Figure 4B of electrodes 352) and gaps between adjacent electrodes (e.g., Figure 3B After removing the mask layer, the patterned electrode layer may remain on the substrate.

[0071] The foregoing description sets forth many specific details, such as examples of specific systems, components, methods, etc., in order to provide a good understanding of some embodiments of the present disclosure. However, it will be apparent to those skilled in the art that at least some embodiments of the present disclosure may be practiced without these specific details. In other cases, well-known components or methods are not described in detail, or are presented in a simple block diagram format to avoid unnecessarily obscuring the present disclosure. Therefore, the specific details set forth are merely exemplary. Specific implementations may differ from these exemplary details and are still considered to be within the scope of the present disclosure.

[0072] References in this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places in this specification do not necessarily refer to the same embodiment. In addition, the word "or" is intended to mean an inclusive "or" rather than an exclusive "or". When the term "about" or "approximately" is used herein, it means that the nominal value provided is accurate to within ±10%.

[0073] Although the operations of the methods herein are shown and described in a particular order, the order of the operations of each method may be changed so that some operations may be performed in reverse order, or so that some operations may be performed at least partially simultaneously with other operations. In another embodiment, instructions or sub-operations of different operations may be performed in an intermittent and / or alternating manner.

[0074] It should be understood that the above description is intended to be illustrative, rather than restrictive. After reading and understanding the above description, many other embodiments will be apparent to those skilled in the art. Therefore, the scope of the present disclosure should be determined with reference to the appended claims and the full scope of equivalents enjoyed by these claims.

Claims

1. A method for manufacturing a dielectric barrier discharge (DBD) structure, the method comprising: forming a patterned electrode layer around an outer periphery of a substrate composed of a dielectric material, the patterned electrode layer comprising a plurality of electrodes around the outer periphery of the substrate and gaps between adjacent electrodes of the plurality of electrodes; as well as A dielectric layer is deposited on at least a first region of the patterned electrode layer to form a DBD region of the DBD structure.

2. The method according to claim 1, further comprising: positioning a dielectric sleeve on at least a second region of the patterned electrode layer to form an insulating region of the DBD structure, wherein a first thickness of the dielectric sleeve is greater than a second thickness of the dielectric layer; and A gap filler is applied to fill any gap between the dielectric sleeve and the substrate and to bond the dielectric sleeve to the substrate.

3. The method of claim 1, wherein the patterned electrode layer has a thickness between approximately 0.1 micrometers and 20 micrometers, and wherein the dielectric layer has a thickness between approximately 25 and 1000 micrometers.

4. The method according to claim 1, further comprising: depositing a conductive material on the outer surface of the substrate to form an electrode layer; as well as The electrode layer is patterned to form the patterned electrode layer, wherein the patterned electrode layer includes one to eight pairs of electrodes.

5. The method of claim 4, wherein the patterning the electrode layer is performed using a process selected from the group consisting of: a) machining; b) Laser etching; as well as c) depositing a mask layer on the electrode layer; patterning the mask; etching a portion of the electrode layer exposed by the patterned mask; as well as The mask is removed.

6. The method according to claim 4, further comprising: roughening a surface of the substrate at the outer periphery of the substrate; as well as A metallization process is performed to deposit the metal on the rough surface.

7. The method of claim 4, wherein depositing the conductive material comprises: Electron beam ion assisted deposition (EB-IAD) is performed to deposit the conductive material, wherein the conductive material includes at least one of a metal, a metal alloy, a conductive oxide, or a conductive ceramic.

8. The method of claim 7, wherein the conductive material comprises at least one of Cr, Ni, Au, Cu, Ag, Pd, Pt, ITO, TiN, TiB2, MoSi2, BaTiO3, Fe2O3, TiO3, ReO3, RuO2, IrO2, TiO, or V2O3.

9. The method according to claim 7, further comprising: Before performing the EB-IAD, the surface of the substrate is polished at the outer periphery of the substrate.

10. The method of claim 1, wherein the patterned electrode layer comprises one of a manganese-molybdenum alloy or a silver-palladium alloy.

11. The method of claim 1, wherein the dielectric layer comprises a first oxide layer selected from the group consisting of aluminum oxide, yttrium oxide, silicon dioxide, and magnesium oxide. 12 . The method of claim 1 , wherein depositing the dielectric layer comprises performing a plasma spray (PS) process, a physical vapor deposition (PVD) process, or a frit process.

13. The method according to claim 1, further comprising: A metal oxide layer is deposited on the dielectric layer.

14. The method of claim 13, wherein the metal oxide layer comprises at least one of aluminum oxide or yttrium oxide.

15. The method according to claim 1, wherein forming the patterned electrode layer comprises: depositing a mask layer over the outer periphery of the substrate; patterning the mask layer to expose a plurality of surface areas of the substrate; depositing a metal layer on the mask layer and a plurality of exposed surface areas of the substrate; as well as The mask layer is removed.

16. The method of claim 1, wherein a cross-section of the substrate has a shape selected from the group consisting of a circle, an oval, a square, a rectangle, a pentagon, and a hexagon.

17. The method of claim 1, wherein each of the gaps has a gap size between 0.5 mm and 8 mm.

18. The method of claim 1, wherein the dielectric material comprises at least one of alumina, quartz, or sapphire.

19. A method comprising: roughening the surface of the dielectric rod by a grinding operation or a media blasting operation to form a roughened surface of the dielectric rod; depositing an electrode layer on the roughened surface of the dielectric rod by a metallization process or by an electron beam ion assisted deposition (EB-IAD) process, wherein the electrode layer comprises at least one of a metal, a metal alloy, or a conductive oxide; removing at least a portion of the electrode layer by a machining process or an etching process to form a plurality of gaps in the electrode layer, wherein each gap of the plurality of gaps separates an electrode from an adjacent electrode; as well as A dielectric layer is deposited on at least a first region of the electrode layer to form a dielectric barrier discharge region.

20. A method comprising: Smoothing the surface of the dielectric rod by a polishing operation to form a smooth surface of the dielectric rod; depositing a mask layer on at least the smooth surface of the dielectric rod; patterning the mask layer to expose a plurality of electrode regions on the smooth surface of the dielectric rod; depositing a metal layer or a conductive oxide layer on the mask layer and the plurality of electrode regions to form a plurality of electrodes on the plurality of electrode regions; removing the mask layer to form a plurality of gaps, wherein each gap of the plurality of gaps separates an electrode from an adjacent electrode; as well as A dielectric layer is deposited on at least a first region of the plurality of electrodes to form a dielectric barrier discharge region.

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