Current sampling circuit and integrated circuit

Abstract

The invention discloses a current sampling circuit and an integrated circuit. The current sampling circuit includes: an output power element; a power tube current sampling element group, a voltage tracking element group and a current mirror element group; the power tube current sampling element group comprises a power tube current sampling element used for sampling output current of an output power element; and the first bias current source is used for controlling the current of the first tracking element and the current of the second tracking element to be the same. According to the invention, an additional bias current source is arranged in a power tube current sampling element group, and a current compensation path is additionally arranged in a current mirror module, so that the output currents of the drains of two voltage tracking elements are kept at the same level; therefore, the interelectrode voltage of the output power element and the interelectrode voltage of the power tube current sampling element can be accurately matched, the sampling precision of the current sampling circuit is improved, and the problem that the precision is sharply reduced when the output power element works in a linear region is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a current sampling circuit and an integrated circuit. Background Art

[0002] In the current related technologies, the solution of using current mirror to realize current sampling is widely used. In the sampling circuit, it is generally necessary to respectively set a voltage tracking MOS connected to the output power element and a voltage tracking MOS connected to the power tube current sampling element. However, since the current of the voltage tracking MOS connected to the output power element is a preset bias current, and the current of the voltage tracking MOS connected to the power tube current sampling element is a power tube sampling current, the drain currents of the above two groups of voltage tracking MOS are different, which further leads to a deviation in the drain-source voltage. This deviation reduces the accuracy of current sampling due to the low drain-source voltage when the output power element and the power tube current sampling element work in the linear region. Summary of the invention

[0003] The present application provides a current sampling circuit and an integrated circuit.

[0004] The current sampling circuit involved in the embodiment of the present application is characterized in that the current sampling circuit includes:

[0005] Output power components;

[0006] A power tube current sampling element group, used for sampling the output current of the output power element group;

[0007] A voltage tracking element group, used to track the drain voltage of the output power element so that the drain voltage of the power tube sampling element group is consistent with it, thereby ensuring the accuracy of current sampling; and

[0008] A current mirror element group, used for replicating current to cooperate with the voltage tracking element group to perform current bias, current compensation, and replicating current to complete current sampling;

[0009] The power tube current sampling element group includes:

[0010] A power tube current sampling element, used for sampling the output current of the output power element group;

[0011] The first bias current source is used to adjust the current of the voltage tracking element connected to the power tube current sampling element group to make it the same as the current flowing through another voltage tracking element.

[0012] In some embodiments, the output power element and the power tube current sampling element are power MOS tubes of the same type, and the ratio of the gate trench width of the output power element to the gate trench width of the power tube current sampling element is a preset value greater than or equal to 1.

[0013] In some embodiments, the source of the output power element and the source of the power tube current sampling element are both connected to a power supply, the gate of the output power element and the gate of the power tube current sampling element are electrically connected and have equal potentials, and the drain of the output power element is connected to the current output port of the voltage tracking element group circuit.

[0014] In some embodiments, a first end of the first bias current source is connected to a source of the power tube current sampling element, a second end is connected to a drain of the power tube current sampling element, and a current direction of the first bias current source points to the drain of the power tube current sampling element.

[0015] In some embodiments, the voltage tracking element group includes a first tracking element and a second tracking element, the first tracking element and the second tracking element are the same MOS tube, and the first tracking element is connected to the gate of the second tracking element.

[0016] In some embodiments, the source of the first tracking element is connected to the drain of the output power element, the source of the second tracking element is connected to the drain of the power tube current sampling element, and the drain and gate of the first tracking element are short-circuited;

[0017] A drain of the first tracking element and a drain of the second tracking element are connected to the current mirror element group.

[0018] In some embodiments, the current mirror element group includes a first bias module and a second bias module, the first bias module is configured to replicate current to cooperate with tracking correction for the first tracking element, and the second bias module is configured to replicate the current corrected by the second tracking element to complete current sampling.

[0019] In some embodiments, the first bias module includes a second bias current source, a first current mirror element, a second current mirror element, and a third current mirror element, wherein the first current mirror element, the second current mirror element, and the third current mirror element are all MOS tubes of the same type;

[0020] The second bias current source is connected to the drain of the first current mirror element, and the current direction of the second bias current source points to the drain of the first current mirror element.

[0021] In some embodiments, the gates of the first current mirror element, the second current mirror element and the third current mirror element are electrically connected and the sources of the three are connected to the same potential;

[0022] The gate and drain of the first current mirror element are short-circuited, the drain of the second current mirror element is connected to the drain of the first tracking element, and the drain of the third current mirror element is connected to the drain of the second tracking element.

[0023] In some embodiments, the second bias module includes a fourth current mirror element, a fifth current mirror element, and a sixth current mirror element, wherein the fourth current mirror element, the fifth current mirror element, and the sixth current mirror element are all MOS tubes of the same type;

[0024] The gates of the fourth current mirror element, the fifth current mirror element and the sixth current mirror element are electrically connected and the sources of the three are connected to the same potential;

[0025] The drain of the fourth current mirror element is connected to the drain of the second tracking element, and the drain and gate of the fourth current mirror element are short-circuited;

[0026] The drain of the fifth current mirror element is connected to the drain of the first tracking element.

[0027] In this way, the present application maintains the output currents of the drains of the two voltage tracking elements at the same level by setting an additional bias current source in the power tube current sampling element group and an additional current compensation path in the current mirror module, so that the inter-electrode voltages of the output power element and the power tube current sampling element can be accurately matched, thereby improving the sampling accuracy of the current sampling circuit and avoiding the problem of a sharp drop in accuracy when the output power element operates in the linear region.

[0028] The integrated circuit in the implementation manner of the present application includes the above-mentioned current sampling circuit.

[0029] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0031] Figure 1 Schematic diagram of the module structure of the current sampling circuit in the implementation manner of the present application;

[0032] Figure 2 Schematic diagram of the circuit structure of the current sampling circuit in the embodiment of the present application.

[0033] Among them: PM1, output power element; PM2, power tube current sampling element; PM3, first tracking element; PM4, second tracking element; CS1, first bias current source; NM1, first current mirror element; CS2, second bias current source; NM2, second current mirror element; NM3, third current mirror element; NM4, fourth current mirror element; NM5, fifth current mirror element; NM6, sixth current mirror element; OUT, power tube output port. DETAILED DESCRIPTION

[0034] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions from beginning to end. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of the present application, and cannot be understood as limiting the embodiments of the present application.

[0035] See also Figure 1 , the current sampling circuit in the implementation mode of the present application includes:

[0036] Output power components;

[0037] A power tube current sampling element group, used for sampling the output current of the output power element group;

[0038] A voltage tracking component group, used for tracking the drain voltage of the output power component, so that the drain voltage of the power tube sampling component group is consistent with the drain voltage of the output power component; and

[0039] A current mirror element group, used for replicating current to cooperate with the voltage tracking element group to perform current bias, current compensation, and replicating current to complete current sampling;

[0040] The power tube current sampling component group includes:

[0041] A power tube current sampling element, used for sampling the output current of the output power element group;

[0042] The first bias current source is used to control the current of the first tracking element and the current of the second tracking element to be the same, wherein the first tracking element is connected to the output power element, and the second tracking element is connected to the power tube current sampling element group.

[0043] Specifically, the current sampling circuit in the embodiment of the present application mainly includes four components, namely, an output power element, a power tube current sampling element group, a voltage tracking element group and a current mirror element group. The output power element is the target element to be sampled. The power tube current sampling element group includes a power tube current sampling element for sampling the output power element. The voltage tracking element group is used to track the drain voltage of the output power element so that the drain voltage of the power tube sampling element group is consistent with it, thereby ensuring the accuracy of current sampling. In order to achieve the above purpose, the voltage tracking element group generally includes two tracking elements, and the above two voltage tracking elements are respectively connected to the output power element and the power tube current sampling element. The current mirror element group is used to provide a bias current for the voltage tracking element group, compensate for the current flowing through the two voltage tracking elements, and copy the sampled power tube current to the output end.

[0044] In most application scenarios, if the current flowing through the two tracking elements is not current compensated, the current difference between the two tracking elements is large, which will cause a deviation in the inter-electrode voltage of the two tracking elements. When the power element and the power tube current sampling element work in the saturation region, the sampling effect can still meet the requirements. When the power element and the power tube current sampling element work in the linear region, the sampling accuracy will drop sharply.

[0045] In order to solve the above problems, in an embodiment of the present application, a group of bias current sources are additionally provided in the power tube current sampling element group, and the bias current source provides an additional bias current for the tracking element connected to the power tube current sampling element group. At the same time, through the cooperation of the current mirror element group, the current flowing through the tracking element connected to the power tube current sampling element and the current flowing through the tracking element connected to the output power element are kept the same, thereby ensuring that the inter-electrode voltages of the two tracking elements can be kept as equal as possible, thereby maintaining the overall sampling accuracy of the sampling circuit.

[0046] See also Figure 2 In some embodiments, the output power element PM1 and the power tube current sampling element PM2 are MOS tubes of the same type, and the ratio of the gate trench width of the output power element PM1 to the gate trench width of the power tube current sampling element PM2 is a preset value greater than or equal to 1.

[0047] In some embodiments, the source of the output power element PM1 and the source of the power tube current sampling element PM2 are both connected to the power supply, the gate of the output power element PM1 and the gate of the power tube current sampling element PM2 are electrically connected and have equal potentials, and the drain of the output power element PM1 is connected to the power tube output port OUT.

[0048] In some embodiments, a first end of the first bias current source CS1 is connected to the source of the power tube current sampling element PM2, and a second end is connected to the drain of the power tube current sampling element PM2. The current direction of the first bias current source CS1 points to the drain of the power tube current sampling element PM2.

[0049] Specifically, see Figure 2 , Figure 2 Schematic diagram of the circuit structure of the current sampling circuit in the implementation mode of the present application. The current sampling circuit is externally connected to a power supply, and the positive voltage is VCC. The output power element PM1 and the power tube current sampling element PM2 are MOS tubes of the same type. Exemplarily, PM1 and PM2 are both PMOS tubes. Generally, in order to ensure the effect of current sampling, a fixed proportional relationship is set on the gate channel widths of PM1 and PM2. Generally speaking, the ratio of the gate channel width of PM1 to the gate channel width of PM2 is a fixed value M greater than or equal to 1. The specific value of M can be adjusted according to actual conditions. The solution provided in the present application does not specifically limit the specific value of M.

[0050] Furthermore, the gates of PM1 and PM2 are connected together, thereby maintaining the gate voltage V G In addition, the sources of PM1 and PM2 are connected to an external power supply, the drains of both are connected to a voltage tracking element group, and the drain of PM1 is also connected to the power tube output port OUT, thereby outputting current to an external circuit.

[0051] The power tube current sampling element group includes a power tube current sampling element PM2 and a first bias current source CS1, wherein two ends of CS1 are respectively connected to the source and drain of PM2, and the current direction generated by CS1 points to the drain of PM2.

[0052] Please continue reading Figure 2 In some embodiments, the voltage tracking element group includes a first tracking element PM3 and a second tracking element PM4. The first tracking element PM3 and the second tracking element PM4 are the same MOS tubes, and the gates of the first tracking element PM3 and the second tracking element PM4 are connected.

[0053] In some embodiments, the source of the first tracking element PM3 is connected to the drain of the output power element PM1, the source of the second tracking element PM4 is connected to the drain of the power tube current sampling element PM2, and the drain and gate of the first tracking element PM3 are short-circuited;

[0054] The drain of the first tracking element PM3 and the drain of the second tracking element PM4 are connected to the current mirror element group.

[0055] Specifically, the voltage tracking element group includes two groups of tracking elements, and the two groups of tracking elements are the same MOS tubes. Exemplarily, Figure 2 In the illustrated case, the voltage tracking element group includes a first tracking element PM3 and a second tracking element PM4, and PM3 and PM4 are the same PMOS tubes.

[0056] Furthermore, the gates of PM3 and PM4 are connected together, so that the gate voltages of PM3 and PM4 are kept equal. In addition, the source of PM3 is connected to the drain of the output power element PM1, the gate and drain of PM3 are short-circuited, and the drain of PM3 is connected to the current mirror element group. The source of PM4 is connected to the drain of PM2, and the drain of PM4 is connected to the current mirror element group.

[0057] In some embodiments, the current mirror element group includes a first bias module and a second bias module, the first bias module is configured to replicate the current source current to provide a bias current for the first tracking element PM3, and to provide a shunt current for the second tracking element PM4, the second bias module is configured to replicate the sampling current, provide a bias current for the first tracking element PM3, and replicate the sampling current to the sampling current output terminal to complete current sampling.

[0058] In some embodiments, the first bias module includes a second bias current source CS2, a first current mirror element NM1, a second current mirror element NM2, and a third current mirror element NM3, wherein the first current mirror element NM1, the second current mirror element NM2, and the third current mirror element NM3 are all MOS tubes of the same channel type;

[0059] The second bias current source CS2 is connected to the drain of the first current mirror element NM1 , and the current direction of the second bias current source CS2 points to the drain of the first current mirror element NM1 .

[0060] In some embodiments, the gates of the first current mirror element NM1, the second current mirror element NM2, and the third current mirror element NM3 are electrically connected and the sources of the three are connected to the same potential;

[0061] The gate and drain of the first current mirror element NM1 are short-circuited, the drain of the second current mirror element NM2 is connected to the drain of the first tracking element, and the drain of the third current mirror element NM3 is connected to the drain of the second tracking element PM4.

[0062] In some embodiments, the second bias module includes a fourth current mirror element NM4, a fifth current mirror element NM5, and a sixth current mirror element NM6, wherein the fourth current mirror element NM4, the fifth current mirror element NM5, and the sixth current mirror element NM6 are all MOS tubes of the same type;

[0063] The gates of the fourth current mirror element NM4, the fifth current mirror element NM5 and the sixth current mirror element NM6 are electrically connected and the sources of the three are connected to the same potential;

[0064] The drain of the fourth current mirror element NM4 is connected to the drain of the second tracking element PM4, and the drain and gate of the fourth current mirror element NM4 are short-circuited;

[0065] The drain of the fifth current mirror element NM5 is connected to the drain of the first tracking element.

[0066] For details, please continue to see Figure 2 The current mirror element group includes two groups of bias modules, wherein the first bias module is arranged on one side of the output power element PM1 and the first tracking element PM3, and the second bias module is arranged on one side of the power tube current sampling element PM2 and the second tracking element PM4. The first bias module and the second bias module are connected at the same potential.

[0067] The first bias module specifically includes a first current mirror element NM1, a second current mirror element NM2, a third current mirror element NM3 and a second bias current source CS2. The current mirror formed by the first bias module can copy the current generated by the second bias current source CS2 to PM3, providing a bias current for the first tracking element PM3; and at the same time copy the current to the second tracking element PM4, shunting the bias current from the drain of PM4. Among them, NM1, NM2 and NM3 are MOS tubes of the same type. Figure 2 In the case shown, the above three are all NMOS tubes.

[0068] Further, the gates of NM1, NM2 and NM3 are connected together, the drain of NM1 is connected to CS2, and the drain of NM1 is short-circuited to the gate, and the current direction generated by CS2 points to the drain of NM1. The drain of NM2 is connected to the drain of PM3, and the drain of NM3 is connected to the drain of PM4. In addition, the sources of NM1, NM2 and NM3 are connected together at the same potential. In order to achieve the technical effect in the above embodiment, the bias current generated by CS1 should be the same as the bias current generated by CS2.

[0069] The second bias module specifically includes a fourth current mirror element NM4, a fifth current mirror element NM5, and a sixth current mirror element NM6. The current mirror formed by the first bias module can shunt the bias current of the current flowing through the second tracking element PM4 to the sixth current mirror element NM6, and the current magnitude is the sampling current, so that the above current is outputted externally by using NM6, so as to perform other circuit actions based on the above current. At the same time, the sampling current is copied by NM5 and superimposed on the first tracking element PM3, so that the current flowing through the first tracking element PM3 is completely consistent with the current flowing through the second tracking element PM4. Among them, NM4, NM5 and NM6 are MOS tubes of the same type. Figure 2 In the case shown, the above three are all NMOS tubes.

[0070] Furthermore, the gates of NM4, NM5 and NM6 are connected together, the drain of NM4 is connected to the drain of PM4, the gate and drain of NM4 are short-circuited, and the drain of NM5 is connected to the drain of PM1. In addition, the sources of NM4, NM5 and NM6 are connected together at the same potential. The source of NM6 derives the sampling current based on the current mirror principle, thereby completing the current sampling process.

[0071] Then the process of performing current sampling based on the current sampling circuit in the above embodiment can refer to the following description:

[0072] Driven by the power supply VCC, the output current flowing out of the output power element PM1 is I power , the sampling current flowing out of the power tube current sampling element PM2 is I sense , through the current sampling circuit setting in the above embodiment, the gate-source voltage V GS equal, and at the same time, the drain-source voltage V DS are also approximately equal, so from the quantitative relationship between the gate trench widths of PM1 and PM2, we can see that:

[0073]

[0074] Since PM3 and PM4 are the same PMOS tube, according to the following formula, the gate-source voltage V of PM3 is GS3 The gate-source voltage V GS4 If the potential at the drain of the power tube current sampling element PM2 is approximately equal to the potential at the output port OUT of the power tube at the drain of PM1, then the potential at the drain of the power tube current sampling element PM2 is approximately equal to the potential at the output port OUT of the power tube at the drain of PM1:

[0075] V(PM2 Drain )=V(OUT)-V GS3 +V GS4 ≈V(OUT)

[0076] Where V(PM2 Drain ) is the drain potential of PM2, and V(OUT) is the potential of the power tube output port OUT.

[0077] As in the above embodiment, in order to ensure that the currents flowing through PM3 and PM4 are equal, thereby avoiding the deviation between the drain-source voltage of PM3 and the drain-source voltage of PM4, and further avoiding the reduction of the overall working accuracy of the current sampling circuit when the PMOS tube works in the linear region, the current sampling process can achieve the above purpose in the following manner:

[0078] First, the bias current I generated by the first bias current source CS1 b Based on the connection relationship between CS1 and PM2, it can be known that the current flowing through the source of the second tracking element PM4 is I b +I sense The bias current generated by the second bias current source CS2 is also I b Based on the current mirror principle, the first bias module composed of NM1, NM2 and NM3 converts the above bias current I b The current is copied to the drain of PM3, providing a bias current I for PM3. b .

[0079] Secondly, the drain of the fifth current mirror element NM5 is connected to the drain of the first tracking element PM3, and the third current mirror element NM3 is connected to the drain of the second tracking element PM4. Based on the operating principle of the current mirror, on the basis of setting the first bias current source CS1 and the second bias current source CS2, the current I flowing through the third current mirror element NM3 b It can shunt the current flowing out of the PM4 drain, so that the current flowing through NM4 is I sense At the same time, the setting of the fifth current mirror element NM5 can change the bias current I flowing through PM3 b Add I sense , so that the current flowing through PM3 is I b +I sense , and the current flowing through NM5, NM4 and NM6 is I sense , that is, the sampling current I is converted by using the second bias module based on the operating principle of the current mirror sense The current is copied to the source of NM6 for output, thus completing the current sampling process.

[0080] In this way, the current flowing through PM3 and PM4 is I b +I sense , that is, the current flowing through the first tracking element PM3 and the second tracking element PM4 is the same, then the gate-source voltage V GS3The gate-source voltage V GS4 That is, it can be accurately matched, so that the drain-source voltage V DS1 The drain-source voltage V DS2 It can be kept equal, so that the overall sampling accuracy of the current sampling circuit can be maintained at a relatively high level regardless of working in the saturation region or the linear region.

[0081] In some examples, for MOS tube components such as PM1 to PM4 and NM1 to NM6, their types can be reversed compared to the above examples. For example, illustratively, the channel type of PM1 to PM4 can be N-type, and correspondingly, the channel type of NM1 to NM6 is P-type. The channel type of the above components can be adjusted according to actual conditions, and the specific circuit connection mode is adaptively adjusted as the channel type changes, and this application does not make specific limitations.

[0082] In this way, the present application maintains the output current of the output power element and the drain of the power tube current sampling element at the same level by setting an additional bias current source in the power tube current sampling element group and an additional current compensation path in the current mirror module, so that the inter-electrode voltage of the output power element and the power tube current sampling element can be accurately matched, thereby improving the sampling accuracy of the current sampling circuit and avoiding the problem of a sharp drop in accuracy when working in the linear region.

[0083] The integrated circuit in the implementation manner of the present application includes the above-mentioned current sampling circuit.

[0084] In the description of this specification, the descriptions with reference to the terms "certain embodiments", "in an example", "exemplarily", etc., mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0085] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0086] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A current sampling circuit, characterized in that: The current sampling circuit comprises: Output power components; A power tube current sampling element group, used for sampling the output current of the output power element group; A voltage tracking element group, used for tracking the drain voltage of the output power element, so that the drain voltage of the power tube sampling element group is consistent with the drain voltage of the output power element; and A current mirror element group, used for replicating current to cooperate with the voltage tracking element group to perform current bias, current compensation, and replicating current to complete current sampling; The power tube current sampling element group includes: A power tube current sampling element, used for sampling the output current of the output power element group; The first bias current source is used to control the current of the first tracking element and the current of the second tracking element to be the same, wherein the first tracking element is connected to the output power element, and the second tracking element is connected to the power tube current sampling element group.

2. The circuit according to claim 1, characterized in that The output power element and the power tube current sampling element are power MOS tubes of the same type, and the ratio of the gate groove width of the output power element to the gate groove width of the power tube current sampling element is a preset value greater than or equal to 1.

3. The circuit according to claim 2, characterized in that The source of the output power element and the source of the power tube current sampling element are both connected to a power supply, the gate of the output power element and the gate of the power tube current sampling element are electrically connected and have equal potentials, and the drain of the output power element is connected to the current output port of the voltage tracking element group circuit.

4. The circuit according to claim 2, characterized in that The first end of the first bias current source is connected to the source of the power tube current sampling element, and the second end is connected to the drain of the power tube current sampling element. The current direction of the first bias current source points to the drain of the power tube current sampling element.

5. The circuit according to claim 2, characterized in that The voltage tracking element group includes a first tracking element and a second tracking element. The first tracking element and the second tracking element are the same MOS tube. The gates of the first tracking element and the second tracking element are connected.

6. The circuit according to claim 5, characterized in that The source of the first tracking element is connected to the drain of the output power element, the source of the second tracking element is connected to the drain of the power tube current sampling element, and the drain and gate of the first tracking element are short-circuited; A drain of the first tracking element and a drain of the second tracking element are connected to the current mirror element group.

7. The circuit according to claim 5 or 6, characterized in that: The current mirror element group includes a first bias module and a second bias module, the first bias module is configured to copy current to cooperate with the tracking correction of the first tracking element, and the second bias module is configured to copy the current corrected by the second tracking element to complete current sampling.

8. The circuit according to claim 7, characterized in that The first bias module includes a second bias current source, a first current mirror element, a second current mirror element and a third current mirror element, wherein the first current mirror element, the second current mirror element and the third current mirror element are all MOS tubes of the same type; The second bias current source is connected to the drain of the first current mirror element, and the current direction of the second bias current source points to the drain of the first current mirror element.

9. The circuit according to claim 8, characterized in that The gates of the first current mirror element, the second current mirror element and the third current mirror element are electrically connected and the sources of the three are connected to the same potential; The gate and drain of the first current mirror element are short-circuited, the drain of the second current mirror element is connected to the drain of the first tracking element, and the drain of the third current mirror element is connected to the drain of the second tracking element.

10. The circuit according to claim 7, characterized in that The second bias module includes a fourth current mirror element, a fifth current mirror element and a sixth current mirror element, wherein the fourth current mirror element, the fifth current mirror element and the sixth current mirror element are all MOS tubes of the same type; The gates of the fourth current mirror element, the fifth current mirror element and the sixth current mirror element are electrically connected and the sources of the three are connected to the same potential; The drain of the fourth current mirror element is connected to the drain of the second tracking element, and the drain and gate of the fourth current mirror element are short-circuited; The drain of the fifth current mirror element is connected to the drain of the first tracking element.

11. An integrated circuit, characterized in that: The integrated circuit comprises the current sampling circuit as claimed in any one of claims 1 to 10.

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